Virtuoso RF Schematic-Driven Flow
The Virtuoso RF Solution uses the Layout XL Generate All From Source (GFS) command and LVS capabilities in Virtuoso to fill the verification void present in many current design flows. In a typical Virtuoso RF Schematic-Driven flow, you export a die symbol from Virtuoso Layout Suite MXL (Layout MXL) to create a die symbol and an annotated abstract. This symbol can be used in conjunction with components sourced from different vendors or in-house libraries to create a package schematic in Virtuoso Schematic Editor. The schematic can be used as a connectivity reference to create a package layout using GFS. The package layout can be edited using package editing capabilities that allow the native creation and manipulation of packaging world concepts, such as curved shapes, voiding planes, and mechanical drill holes.
The package layout can be verified using a high accuracy 3D extractor, such as Clarity 3D Solver. Logic changes to the schematic and LVS checks while editing the layout allow the layout to be LVS clean through the design creation and editing process. At any point in the layout editing process, the design can be exported to the Allegro platform for further editing and imported back into the Virtuoso Studio. The round trip allows the connectivity reference in the Virtuoso schematic to guide the resolution of any connectivity conflicts between the Allegro edited layout and the schematic. The layout can be exported to Allegro Package Designer Plus to finalize the layout for manufacturing.
The flow involves various tools, such as Allegro, Sigrity™, Virtuoso Schematic Editor, Virtuoso ADE Explorer, Virtuoso ADE Assembler, Design Data Translators, and Virtuoso Visualization and Analysis XL.
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