Troubleshoot Performance
You can face the following issues related to performance:
Design Fails to Open or Takes a Long Time to Open
If you design takes a long time to open in Layout XL, or fails to open at all, try the following.
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If your design has many devices which overlap but have not been abutted previously, and you start Layout XL with full connectivity extraction, by default the software attempts to automatically abut the devices in question. To prevent this, set the lxLocalAbutment environment variable to
t. -
If your design is hierarchical, it might be that the logical elaboration performed by Configure Physical Hierarchy is causing the problem.
You can use the physical stop view list to limit the logical elaboration by switching on the cphStopLogicalElabAtPhysLeaf environment variable. This stops the elaboration of the logical design hierarchy when a node is reached which maps to one of the view names specified in the Physical stop view list field.
WhencphStopLogicalElabAtPhysLeafis set tot, global nets below the leaf instance in the schematic are not considered during the elaboration. If your design relies on such nets, Cadence recommends that you do not switch on this environment variable.
Layout XL Is Slow
The following considerations can help you improve Layout XL performance speed.
- Instead of displaying flight lines for all the incomplete nets in the design, use the highlighting features of the path command or probing to determine connections or display only nets you are working on or that are relevant to the current task.
- If you need extra pins in the layout for feedthrough nets or substrate connections, consider adding those after you have completed the main portion of the design. Adding extra pins increases the number of nets the extractor manages and degrades performance.
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Specify only layers to be used as interconnect in the
validLayersconstraint Using more layers than necessary causes the extractor to check all shapes on those layers, which slows performance. If you do not have interconnect to wells, do not specify the well in thevalidLayersconstraint.
Related Topics
Technology File Requirements for Layout XL
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