Declaring Nettypes

SV real and electrical nettypes are declared with the keyword nettype, and include a data type and optionally a resolution function. It can carry one or more values over a single net. 

Syntax

nettype datatype nettype_identifier with resfuncname;

Where:

• datatype is the base type for the net to be defined. It can be built-in real/elecrical, user-defined type, or structure of multiple values.
• nettype_identifier is the identifier for the nettype to be defined.
• resfuncname is the optional resolution function to be used. It can be the Cadence built-in resolution function or user-defined functions.

The following is an example of how you can declare a basic SystemVerilog nettype (single-value real) without any resolution function. Nettype can be declared inside or outside the module. This type of declaration can have only a single driver. The real variable or a nettype has a default value of 0 when created. The $display (I1=1.1, I2=0) prints immediately, while the $strobe (I1=1.1, I2=1.1) buffers the print statement and prints after all evaluations have been completed at the end of that time point.

nettype real realnet; //Nettype declaration

module top;
  nettype real realnet;
  real I1 = 1.1;
  realnet I2;
  assign I2 = I1;
  initial begin
    $display("display -> I1=%g, I2=%g", I1, I2);
    $strobe("strobe -> I1=%g, I2=%g", I1, I2);
  end
endmodule

The following example illustrates how to declare a user-defined nettype with a UDR. 

//Declaring a User Defined Nettype with a UDR
nettype T wTsum with Tsum;

// User Defined Type (UDT), T
typedef struct {
 real A;
 real B;
 integer N=0;
} T;

// User Defined Resolution Function (UDR), Tsum
function automatic T Tsum (input T dr[]);
  foreach (dr[i]) begin
    Tsum.A += dr[i].A;
    Tsum.B += dr[i].B;
    Tsum.N += dr[i].N;
  end
endfunction

Related Topics

• Examples of Using Built-In Nettypes