Wreal wires are defined as follows in the Real net declarations section of the Verilog-AMS LRM 2.3.
The wreal or real net data type, represents a real-valued physical connection between structural entities. A wreal net shall not store its value. A wreal net can be used for real-valued nets, which are driven by a single driver, such as a continuous assignment. If no driver is connected to a wreal net, its value shall be zero (0.0). Unlike other digital nets, which have an initial value of ‘z’, wreal nets shall have an initial value of zero.
Wreal nets can only be connected to compatible interconnect and other wreal or real expressions. They cannot be connected to any other wires, although the connection to explicitly declared 64-bit wires can be done via system tasks $realtobits and $bitstoreal. Compatible interconnect are nets of type wire, tri, and wreal where the IEEE std 1364-2005 Verilog HDL net resolution is extended for wreal. When the two nets connected by a port are of net type wreal and wire/tri, the resulting single net is assigned as wreal. Connection to other net types results in an error.
The Verilog-AMS LRM lists the following restrictions on wreal nets:
- Can have at most one driver
- Can only connect to other wreals, wires, or real-valued expressions
- Scalar only and no support for arrays
The wreal functionality is useful for practical designs. Standard mathematical functions, such as sin, cos, abs, log, min, and max are support by real variables in standard verilog. This enables basic modeling capabilities when combining the real calculations with wreal wire connections. However, the limitations introduced by the LRM definitions have a substantial impact on usability. As a result, Cadence extended the wreal support beyond the LRM limitations, enabling a huge variety of applications with the extended wreal features. Details are given in the next chapter.