Product Documentation
Real Number Modeling Guide
Product Version 22.09, September 2022

Verilog-AMS Wreal Examples

In Verilog-AMS, the concept of a truly real-valued net/wire was introduced, called wreal – a real valued wire. These nets represent a real-valued physical connection between structural entities. The examples listed shows how a real-valued net can be used instead of a bit vector used in a traditional Verilog representation.

Example 1

The following is an example of using the bit vector representation (for example, 64-bit vector) in traditional Verilog.

module top();
    wire [63:0] bitvector;
    source I1 (bitvector);
    sink I2 (bitvector);
endmodule

module source(r);
    output r;
    wire [63:0] r;
    real realnumber;
    reg [63:0] bitvector;
    initial begin
      while (realnumber < 10.0) begin
        #1 realnumber = realnumber + 0.1;
        bitvector = $realtobits(realnumber);
      end
      $stop;
    end
    assign r = bitvector;
endmodule // send

module sink(r);
    input r;
    real realnumber;
    wire [63:0] r;
      always @(r) begin
      realnumber = $bitstoreal(r) ;
      $display(" real value = %f \n", realnumber);
    end
endmodule

Example 2

The following example illustrates the same connection between the blocks source and sink as we saw in the previous one. However, there is no type conversion needed and the connecting wire is a scalar value.

`include "disciplines.h"

module top();
    wreal real_wire;
    source I1 (real_wire);
    sink I2 (real_wire);
endmodule

module source(r);
    output r;
    wreal r;
    real realnumber;
    initial begin
      while (realnumber < 10.0) begin
        #1 realnumber = realnumber + 0.1;
      end
      $stop;
    end
    assign r = realnumber;
endmodule // send

module sink(r);
    input r;
    wreal r;
    always @(r) begin
      $display(" real value = %f \n", r);
    end
endmodule

Example 3

The following example illustrates the use of a real wire type as in input port of a voltage-controlled oscillator (VCO). The real value vin is used in an always block. This is possible due to the event-based nature of a wreal net—calculating the output frequency of the VCO.

‘include "disciplines.vams"

‘timescale 1s/1ps

module top ();
    wreal w_in;
    real r_in;
    vco vco(w_in, clk);
    always begin
      r_in = 1.0;
      #10 r_in = 1.2;
      #10 r_in = 0.2;
      #10 r_in = -0.2;
      #10 r_in = 1.345;
      #10 $finish;
end    
assign w_in = r_in;
endmodule

module vco(vin, clk);
    input vin;
    wreal vin;
    output clk;
    parameter real center_freq=1.0e9; // freq in HZ
    parameter real vco_gain=1.0e9; // freq gain in
    real freq=center_freq;
    real clk_delay= 1.0/(2*center_freq) ;
    reg clk=1'b0;
    always @(vin)begin
      freq = center_freq + vco_gain*vin;
      clk_delay = 1.0/(2*freq);
    end
    always #clk_delay clk = ~clk;
endmodule

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