In traditional Verilog, real values were modeled using 64-bit vectors, which encoded the real value in the IEEE floating-point format.
Verilog is built on a single type – binary. Inside a module, real-valued variables can be used; however, real values cannot be passed directly through ports. Two system tasks, $realtobits and $bitstoreal, were provided to encode and decode the real values in the 64-bit vectors. However, this use model does not support reconfigurable models under a schematic-based environment. In this environment, you model a real value with a single, scalar entity, which does not map into the traditional Verilog representation of a 64-bit vector real. This also proved difficult in the mixed-language world with VHDL reals not mapping cleanly to the 64-bit vectors used in traditional Verilog. This adds a lot of type conversion effort to the modeling. Moreover, the bit vector representation (for example, 64-bit vector) of the block interconnect is not matching with the physical connection (single wire).
Wreal is a native Verilog-AMS feature, which is more advanced in the area of connect modules and interfacing with the analog design portion. Verilog-AMS wreal language includes all the benefits of a digital signal in Verilog-AMS, which makes it the preferred language for Verilog users. Some of the benefits are:
- Easy interaction with the analog portion of the design.
- A wreal net can be directly connected to the electrical nets by using automatically inserted E2R and R2E connect modules.
- Discipline association: The discipline concept is widely used in Verilog-AMS to check connectivity, customize connect modules, and apply resolution functions.
- Multiple wreal driver support.
- The ability for scope-based wreal driver resolution function specification.
- Identification of high impedance/unknown state(X/Z support) for real values.
- Fully supported in dfII environment, thus bridging analog and digital use models.