Appendix A: Updating Legacy Libraries and Netlists

Before using existing libraries with the AMS Designer simulator, you may have to make modifications to the libraries. The following are some of the modules and libraries are that you can modify:

• Verilog-A Modules: The Verilog^®-A language is a subset of Verilog-AMS, but some of the language elements in that subset have changed since the release of Verilog-A. As a result, you might need to revise your Verilog-A modules before using them as Verilog-AMS modules. For more information, see Updating Verilog-A Modules
  
  In addition, some Verilog-A modules can be made more efficient by rewriting them to take advantage of the digital and mixed-signal aspects of Verilog-AMS. In these cases, you might want to generate an alternate cellview for use with the AMS Designer simulator. For more information, see Mixed-Signal Aspects of Verilog-AMS.
  
• Libraries of Analog Masters: The AMS Designer simulator uses analog primitive tables to accelerate the processing of Spectre/SPICE model files. Each model card has a unique name, referred to as the analog master, which allows it to be accessed by Verilog-AMS. Before you can use model files in your designs you must create analog primitive table files for them. See Analog Primitives and Subcircuits.
• Verilog Modules: A module written for the purely digital Verilog language can often be used unchanged in the AMS Designer simulator. However, it might be necessary to make some minor changes, such as escaping or modifying keywords, to make the module legal for both Verilog and Verilog-AMS. If it is not possible to modify a Verilog module to make it compliant with both languages, you can use the unmodified file by compiling it without using the -AMS option for the xrun/xmvlog command.
  
  For example, you might have a Verilog module that uses branch as a variable. That is legal in Verilog but illegal in Verilog-AMS (which recognizes branch as a keyword). As a result, you must compile the module without using the -AMS option so that the module is compiled as Verilog, not as Verilog-AMS.
• VHDL Blocks: With the Spectre AMS Designer Simulator, you can use VHDL textual data directly, without importing models. Any VHDL block that runs with the NC-VHDL simulator runs with the AMS Designer simulator too.
• Legacy Netlists: Netlists used for analog-only simulators, such as the Spectre^®circuit simulator, serve a number of purposes, including instantiating components, setting initial conditions, defining models, and specifying analyses. In the Spectre^®AMS Designer simulator, instantiation and model specification are separated from the simulator controls and some of the analog controls are separated from the rest of the simulation controls. As a result, the primary way of controlling the analog solver is to define an analog simulation control file. The controls you can use in the analog simulation control file differ slightly from those in netlists, so you might need to rewrite legacy netlists to use the controls described in Controls for the Analog Solvers. 
  The AMS Designer simulator does not support everything used in existing netlists. For information about unsupported features, see the Spectre AMS Simulator Known Problems and Solutions.
• Existing Designs: Designs entered using Virtuoso Schematic Editor in flows such as the Cadence^®analog design environment flow are automatically translated to Verilog-AMS netlists. Issues including some of those mentioned above must first be addressed before the AMS netlister can properly work. For guidance about complying with the AMS design guidelines, see the "Designing for Virtuoso AMS Compliance" chapter, of Virtuoso AMS Environment User Guide.