SPICE Nets inside a Verilog Design

You can use the following special instances to access SPICE nets in a Verilog design:

Instance Type	Description
`cds_spice_a2d`	Analog-to-digital connection from SPICE to Verilog (analog drives)
`cds_spice_d2a`	Digital-to-analog connection from Verilog to SPICE (digital drives)
`cds_spice_bidir`	Bidirectional connection between Verilog and SPICE
`cds_spice_a2a`	Analog-to-analog connection from Verilog to SPICE (such as driving a SPICE port from the top level)

To use these instances, specify the full hierarchical path to the SPICE net you want to access as the parameter of the instance and the Verilog net as the port connection. Here are some examples:

cds_spice_d2a #("test.top.I0.I1.X1.X2.drive") d2a1(drive);

cds_spice_a2d #("test.top.I0.I1.X1.X2.read") a2d1(read);

cds_spice_d2a #("TestBench.SPICEblock.X2.regf") D2A1 (fault);

cds_spice_a2d #("TestBench.SPICEblock.X2.rega") A2D1 (chk1);

cds_spice_a2d #("TestBench.SPICEblock.X2.regb") A2D2 (chk2);

cds_spice_a2d #("TestBench.SPICEblock.X2.regc") A2D3 (chk3);

Consider the following digital testbench code (Verilog):

module TB;    // the testbenchdut

DUT(in1, in2); // instantiation of the device under test (the DUT)

reg in1, in2;          // drivers of the DUT
wire chk1, chk2, chk3; // signals used to check inside the DUT for
                       // erroneous conditions

reg fault;    // a signal used to generate a fault

initial begin // assign values to the DUT drivers
  in1 = 1'b1; in2 = 1'b1;
end

initial begin // generate a fault condition at 20 ticks
  TB.DUT.fault = 1'b0;
  #20 fault = 1'b1;
end

// monitoring of checks - an error is printed if they trigger
always @(chk1) $strobe("error chk1 triggered!\n");
always @(chk2) $strobe("error chk2 triggered!\n");
always @(chk3) $strobe("error chk3 triggered!\n");

// These statements make connections from the local testbench
// signals to the DUT. It might be convenient for the
// testbench to alias signals in the DUT to local
// signals in the testbench so that if the pathnames get
// changed in the design process, you can adapt the testbench
// easily by just changing this block and
// not the complex logic of the testbench
.assign TB.A.DD.f = fault;
assign chk1 = TB.A.DD.a;
assign chk2 = TB.A.DD.b;
assign chk3 = TB.A.DD.c;

endmodule

Perhaps the Verilog code for the DUT looks something like this:

module dut(in1, in2); blockA A(in1); blockB B(in2); endmodule module blockA(in); blockC CC(in); blockD DD(in); endmodule

module blockB(in); blockE EE(in); endmodule module blockCC(in); endmodule module blockDD(in); reg a,b,c,d; reg f; ...etc endmodule module blockEE(in); endmodule

// Design Structure // // TB (the testbench) // | // DUT // | // --------------- // | | // A B // | | // ------ EE // | | // CC DD

Perhaps the SPICE representation of blockA looks something like this:

subckt blockA(in) X1 in blockCC X2 in blockDD ends subckt blockDD(in) X1 in a X2 a b blockXXX X3 b c blockYYY X4 c d f blockZZZ ends

// Design Structure with blockA as SPICE // // TB (the testbench) // | // DUT // | // --------------- // | | // A B // | | // ------ | // | | EE // X1 X2

To account for a SPICE block substitution in the testbench code, you could have the following:

... // No changes to the testbench code before this point... `ifdef AMS_MODE // Add these lines for SPICE block substitution cds_spice_d2a #("TB.A.X2.f") D2A1 (fault); cds_spice_a2d #("TB.A.X2.a") A2D1 (chk1); cds_spice_a2d #("TB.A.X2.b") A2D2 (chk2); cds_spice_a2d #("TB.A.X2.c") A2D3 (chk3); `else // pure-digital configuration assign TB.A.DD.f = fault; assign chk1 = TB.A.DD.a; assign chk2 = TB.A.DD.b; assign chk3 = TB.A.DD.c; `endif ...

The following table outlines the effective module definitions for these instance types as well as the resulting interface elements (IEs) the software inserts in your design:

Instance Type	Effective Module Definition	Interface Element
`cds_spice_a2d`	`module cds_spice_a2d(e); output e; electrical e; parameter spicenet = "null"; endmodule`	analog-to-digital
`cds_spice_d2a`	`module cds_spice_d2a(e); input e; electrical e; parameter spicenet = "null"; endmodule`	digital-to-analog
`cds_spice_bidir`	`module cds_spice_bidir(e); inout e; electrical e; parameter spicenet = "null"; endmodule`	bidirectional
`cds_spice_a2a`	`module cds_spice_a2a(e); input e; electrical e; parameter spicenet = "null"; endmodule`	none

SPICE Nets inside a Verilog Design

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