Verilog-AMS Connect Modules for VHDL-SPICE Connection

You can use the AMS Designer built-in CMs ( *_0_CE ) present in the AMSD built-in connectLib library instead of VHDL-AMS model in std_logic and electrical signal connections for VHDL-SPICE connections. This provides significant performance improvements for VHDL-SPICE applications.

To use the Verilog-AMS CMs for VHDl-SPICE connections, you need to compile the AMSD built-in connect element (CE) into a test case library, as shown below.

xrun -compile `cds_root xrun`/tools/affirma_ams/etc/vhdlams_connectlib_samples/*.vhms

This feature does not change the use model of the ce statement in the amsd block and the CE report for VHDL-SPICE connections.

This feature is enabled by using the xmelab or xrun option -use_cm.

Currently, this feature supports only std_logic and electrical connections.

The following are not supported:

• VHDL real and SPICE electrical connection
• VHDL subtypes of std_logic and VHDL record types

Related Topics

• Connecting VHDL Blocks to SPICE Blocks
• VHDL-SPICE Conversion Element Optimization