Connecting VHDL Blocks to SPICE Blocks

Direct instantiation of SPICE blocks within a VHDL scope is supported only using the xrun command flow. The three step method is not supported for VHDL-SPICE flows. Analogous to the Verilog-SPICE solution, AMSCB flow is required to specify SPICE blocks, boundary port maps and binding information. You can use the portmap and config mstatements in an amsd block to specify port bindings at VHDL-SPICE boundaries.

Here are some examples:

amsd{
    portmap subckt=dummy_spice autobus=yes refformat=vhdl
    config cell=dummy_spice use=spice
    }

and:

amsd{
    portmap subckt=dummy_spice2 autobus=yes reffile=ref.vhd refformat=vhdl
    config cell=dummy_spice2 use=spice
    }

In the example immediately above, the reffile contains a VHDL module that defines the port bindings to use from a VHDL parent to a SPICE subcircuit or instance. The config statement specifies which SPICE cell (subcircuit) or instance.

You can have user-defined types, subtypes, and records where VHDL connects to SPICE.

Consider the following example of a 16x16-bit multiplier (.SUBCKT mult16x16_spice) with two 16-bit inputs (A<15:0> and B<15:0>), a clock input (CLK), and a 32-bit output (P<31:0>).

* SPICE file: "mult16.net"
***** This is a 16-bit x 16-bit parallel unsigned multiplier **********
*
*   A<15:0> 16-bit multiplicant input
*   B<15:0> 16-bit multiplier input
*   P<31:0> 32-bit product output
*   PRD<31:0> 32-bit product output befor the output register
*   CLK  clock input
*   RegA 16-bit input register(postive edge triggered)
*   RegB 16-bit input register(postive edge triggered)
*   RegP 32-bit output register(postive edge triggered)
*
*                    ----
*               16  |    |
*   A<15:0> ----/-->|RegA|--------+
*                   |    |        |
*             +---->|    |        v
*             |      ----    ----------  PRD<31:0>
*             |             |          |        ----
*             |             |  16x16   |  32   |    |
*             |             |Multiplier|---/---|RegP|--/--> P<31:0>
*             |             |  array   |       |    |  32
*             |             |          |   +-->|    |
*             |              ----------    |    ----
*             |      ----        ^         |
*             | 16  |    |       |         |
*   B<15:0> ----/-->|RegB|-------+         |
*             |     |    |                 |
*             +---->|    |                 |
*             |      ----                  |
*      CLK  --+----------------------------+
*
***********************************************************************

You can create a VHDL reffile such as the following that defines the directions for the interface elements between SPICE and VHDL:

-- VHDL reffile: "mult16x16_spice.vhd"

LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.ALL;
ENTITY mult16x16_spice IS
    PORT (
        A : in std_logic_vector ( 15 DOWNTO 0 );
        B : in std_logic_vector ( 15 DOWNTO 0 );
        CLK : in  std_logic;
        P :  out std_logic_vector( 31 DOWNTO 0 ));
END ENTITY mult16x16_spice;

Your VHDL testbench might look like this:

LIBRARY ieee;
USE ieee.math_real.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE     IEEE.ELECTRICAL_SYSTEMS.all;
LIBRARY STD;
USE STD.textio.all;

LIBRARY worklib;
USE worklib.ALL;

ENTITY top ISEND  top;

ARCHITECTURE bhv OF top IS
  SIGNAL sa : std_logic_vector (15 downto 0);
  SIGNAL sb : std_logic_vector (15 downto 0);
  SIGNAL sp : std_logic_vector (31 downto 0);
  SIGNAL sclk : std_logic;

BEGIN
   Iclk: ENTITY work.clk_gen
              PORT MAP ( clk => sclk);
                    Iab: ENTITY work.a_b_gen
           PORT MAP ( clk => sclk, a => sa, b => sb);
          SPICE_DUT: ENTITY worklib.mult16x16_spice
      PORT MAP (sa , sb, sclk, sp);
       checka_d_da:  ENTITY worklib.DA_AD_GENERIC_CHECKS;
END ARCHITECTURE bhv;

In your control file, you include the SPICE file (which contains the mult16x16_spice subcircuit definition) using an include statement, and you specify the port bindings you want the elaborator to use at VHDL-SPICE boundaries using portmap and config statements in an amsd block as follows:

include "mult16.net"

amsd{
     portmap subckt=mult16x16_spice autobus=yes refformat=vhdl
              reffile=source/mult16x16_spice.vhd
     config cell=mult16x16_spice use=spice
}

The portmap statement, above, indicates that you want the elaborator to use the port bindings you defined in the VHDL file, mult16x16_spice.vhd , and apply them to the SPICE subcircuit, mult16x16_spice. The config statement indicates that you want the elaborator to use the SPICE definition for the mult16x16_spice cell.

Further, you can specify conversion elements for the VHDL-to-SPICE connections using ce statements:

amsd{
     portmap subckt=mult16x16_spice autobus=yes refformat=vhdl
             reffile=source/mult16x16_spice.vhd
     config cell=mult16x16_spice use=spice
      ce name=worklib.std_logic2e dir=input type=std_logic genericmap="vsup 2.5"
      ce name=worklib.e2std_logic dir=out type=std_logic genericmap="vsup 2.5"
}

Connecting VHDL Blocks to SPICE Blocks

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