If you are using the AMS Designer simulator with the Spectre solver and the simulation front end (SFE) parser, you can use a .ahdl_include statement in a SPICE netlist to include behavioral or structural Verilog-A modules.
The .ahdl_include statement has the following format:
.ahdl_include " filename "
For filename, you can specify either a full or a relative path that resolves across your network to the file containing the Verilog-A modules. The file name must have a .va extension to indicate that the included modules Verilog-A language models.
When you use the .ahdl_include statement to include a Verilog-A module in a SPICE netlist, the name of the instance that instantiates the Verilog-A behavioral module must not begin with Y.
Verilog-AMS Vector Buses with SPICE Subcircuits
You can connect Verilog-AMS vector buses directly to SPICE buses using the sourcefile property to specify the name of the SPICE file and the sourcefile_opts property to specify the Verilog-AMS to SPICE bindings. For details, see "sourcefile Property", "sourcefile_opts Property", and "The Port Mapping File".