Product Documentation
Dracula User Guide
Product Version IC23.1, September 2023

Index

Symbols

... in syntax 10
.CEL extension for cell-mode HLPE netlist
.DAT extension for composite-mode HLPE netlist
.erc file
.inp file ,
.log file
EXPAND stage and Hcell selection
HDRC output
HERC output
reallocating memory
.mlg file ,
.msm file ,
.SUBCKT
global signals
in transistor-level netlist for HLPE
names must match layout for HLVS/HLPE ,
pin names for HLVS/HLPE
required for composite mode HLVS ,
used to generate text for LVS
.sum file ,
*.EQUIV
in SPICE netlists with node numbers
preparing the netlist
*.GLOBAL
add to HLVS netlist
preparing the netlist
*.NOPIN
preparing the netlist
removing global signals from a subcircuit
*.PIN
add to HLVS netlist
preparing the netlist

Numerics

2.5D MB parasitic extraction
2D3B parasitic extraction

A

A option
EXPLODE
LPESELECT
accuracy
2.5D MB parasitics
constants
electromigration checks
fabrication and masking effects
allocating swap space
analysis, piecewise fringe capacitance ,
AND
grouping to improve performance
passing nodal information
angles, flagging
antenna check
Applicon
database conversion
input format
area
exact contact size check
for 2.5D MB parasitics
for sidewall capacitance with fringing effects
in capacitance output format
in EQUATION
overlap capacitance
parameter in PARSET
ratio for antenna checks
with ATTRIBUTE CAP
arrays
check using RAM-CELL
choosing Hcells
environment
See gate arrays
HDRC for
Assura RCX
and the dracToRCX interface
commands
ATTACH
for Cadence-format input data
used with GEN-TEXT-LAYER
using
ATTRIBUTE CAP
constants with
debugging capacitance extraction
definition
examples
colinear edge capacitance
correcting for resistor cuts
directional sidewall capacitance
fringe capacitance in PRE
internal cell nodes to parent cell nodes
multiple for 2.5D MB extraction
simple capacitance
single-layer fringe capacitance
two-layer fringe capacitance
two-layer metal
piecewise analysis
replace with extractParasitic()
sidewall capacitance with fringing effects
specifying area and perimeter
values for single-layer fringe
ATTRIBUTE RES
definition
examples
contact
controlling contact cuts
diffusion
simple metal and poly
two-layer metal
replace with extractParasitic()

B

B option for SIZE
backannotation
using extractParasitic()
BASE-LAYER
definition ,
for gate arrays
for HERC
in both cell and composite runs for a design
bipolar
recognition region for devices
rules file example
bounding box
created by CELLBOX-LAYER
displayed by SHORTBOX
for HLVS
generated by Dracula
specifying width with HCELL FRAME BY
using your own with CELLBNDY
BREAK
example
ungroups stages

C

C option
C parameter in PARSET
Cadence
See also DFII
output from Virtuoso
using Cadence-format layout in Dracula
CALCULATE
definition
example
CANDIDAT.DAT
capacitance
2.5D MB
2D3B
accuracy
C parameter in PARSET
colinear
edge correction
edge extraction ,
combined with resistance extraction ,
connecting power and ground
cross-coupled
definition
hierarchical extraction limitation
LPESELECT limitation
debugging
colinear edge correction
fringe
using constants
directional sidewall
definition
illustration
using extractParasitic()
extraction functions ,
flattening to extract
fringe
CLL value in 2.5D MB
debugging
definition
effects on sidewall capacitance
extracting with extractParasitic()
in 2.5D MB extraction
in 2D3B extraction
in PRE
piecewise analysis , ,
single layer ,
single net
TPR value in 2.5D MB
two layers ,
ground
lump sum
definition
in hierarchical extraction
internal cell nodes to parent cell nodes
LPESELECT C option omits
output as lump sum or cross-coupled
overlap
definition
example
extracting with extractParasitic()
rules file
two-layer metal
with fringing effects
over-the-cell wire
piecewise analysis ,
power
sidewall
colinear edges
correcting after resistor cuts
directional ,
simple ,
single net
two-layer fringe
UNIT function
capgen
CASE
for Cadence-format input data
case sensitivity
Cadence-format input data
troubleshooting problems
CDLOUT
netlisting global signals
retains case information
cdsd
CDSIN
requirements
specifying the path to your libraries
using purpose data
when to use
CEL extension for cell-mode HLPE netlist
cell mode
description
for HLVS
HDRC error cells
products supported
text for
when to use ,
CELLBNDY, using in composite mode
CELLBOX-LAYER
definition , ,
using
CELL-CHILD-TEXT
definition ,
using
CELL-ERROR-REP
ALL output
definition
generates Hcell errors
CHECK-MODE
cell ,
composite
flat
for HDRC
for HERC
for HLPE
for HLVS
for HPRE
hierarchical
ALL error output
HIER error output
invoking
ONCE error output
viewing error cells
multilevel
checks
antenna rules
contact enclosure
corner
crosstalk
edge-related
electromigration
See ENC
exact size
in-the-direction-of
metal reflection
See ENC; EXT; INT; WIDTH
CHKPAR
definition
examples
electromigration checks , ,
using
clipping
current direction rules where allowed
current direction rules where not allowed
definition
CLL
calculation
definition
CMOS
extracting parasitic resistors
extracting two-layer metal parasitics
rules file examples
CNAMES-CSEN
for Cadence-format input data
colinear
edge capacitance extraction ,
edge correction for parasitic extraction
See rules file
See functions
comments on output for InQuery
composite mode
creating a pad layer
description
for HLVS
frames in HLVS
HDRC error cells
HERC error cells
products supported
text for
when to use ,
composite plane
definition
COMPUTE
criteria
definition
examples
antenna check
electromigration check , ,
MAX option
MIN option
MINGATE option
SUM option
conjunctive rules
for edge checks
LENGTH in
CONNECT
connections not made
determining master layer for
does not require flat layers for HERC/HLVS
examples
antenna check
connecting power and ground
contact resistors
diffusion resistors
electromigration check
fringe capacitance in PRE
fuse extraction
over-the-cell routing wire capacitance to cell
for resistance extraction with extractParasitic()
in device extraction
intervening layers
requires master layer
when flat layers are required
CONNECT-LAYER
layers for contact resistance
master layer for contact layers
constants
for debugging capacitance
use by Dracula
with ATTRIBUTE CAP
contacts
as Hcells
basic enclosure check
connecting multiple layers
controlling resistor cuts
dimensions used in electromigration checks
divided
exact size check
extracting perimeter with EXT
extracting resistance ,
in CONNECT functions
intervening layers
in-the-direction-of checks
master layer for
ratio of gate width to contact area
ratio of gate width to contact perimeter
ratio of gate width/length to contact area
ratio of gate width/number to contact area
conventions
rules file examples 10
syntax 10
user-defined arguments 10
coordinate system
in EDTEXT file
CORNER
example
to flag angles
corner
checks
markers
resistance
cross-coupled capacitance
between internal cell nodes and parent cell nodes
definition
hierarchical extraction limitation
LPESELECT limitation
crosstalk checks
CTEXT
definition ,
layer for GEN-TEXT text
limitation ,
using in cell mode
using in composite mode
current
drive , , ,
in-the-direction-of checks
predicting peak
supplying values with CHKPAR
value, electromigration
CUT
definition
syntax
CUT-TERM
definition
ease of use
examples
contact
correcting capacitance for resistor cuts
fringe capacitance in PRE
poly
simple metal and poly
two-layer metal
extracts corner and junction resistance
limitations
MAXNS option
replaced by extractParasitic()
single-net extraction

D

D2RXRF
DAT extension for composite-mode HLPE netlist
database
See also layout
Dracula sets up for hierarchical processing
extracting a complete netlist in HLPE
format conversion
overlapping cells
size
large ,
medium
small
x to y ratio
dbRead.cxt
ddbToRcx
debugging
capacitance
fringe
rules file
using constants
resistance
See DFII
devices
bipolar
CMOS
extracting
NMOS
recognition region
DFII
See also Cadence
creating layout database
installation hierarchy
layer syntax in rules file
using layer purpose pairs
directional
DRC check in current direction
sidewall capacitance ,
disk space
allocating with TRANSISTOR
allocating with TRANSISTOR-NUM
reduced requirements for composite mode
reduced requirements for hierarchical mode
distributed Dracula
description
when to use
dracToRCX ,
modules
RCX commands
running the interface
Dracula
distributed
full functionality
hierarchical
Dracula To RCX Interface
See dracToRCX
DRAMs
checking
multilevel mode for
DRC
checks
antenna
corner
crosstalk
edge length
edge-related
electromigration
See ENC
exact size
gate widths
in-the-direction-of
metal reflection
See ENC; EXT; INT; WIDTH
grouping checks to improve performance
hierarchical
multilevel
rules file example
drive current , , ,
DSPF file
creating
rules file

E

edge
capacitance extraction, colinear
checks
converting partial edges to full edges
flagging angles
measuring edge length
using conjunctive rules
correction for colinear sidewall capacitance
EDTEXT
for composite mode
to correct case problems
ELCOUNT
in HERC composite run
results passed to Hcell pins
electromigration
checks
fuse extraction
gate approximation
definition
fuse extraction
ratio of gate width to contact area
ratio of gate width to contact perimeter
ratio of gate width/length to contact area
ratio of gate width/number to contact area
ELEMENT
example, MOS devices
single-net extraction
elements
resistors in HPRE
ENC
R and R' region options for edge checking
RC options to flag angles
RT options for measuring edge length
S square boundary option
basic check
description
in-the-direction-of check with no clipping
sizing R' results in edge checking
T option to convert partial edges to full edges
TR options to convert partial edges to full edges
when flat layers are required
See ENC
environment
and composite data
automatically set
definition
for arrays
for memories
multiple overlaps
ENVIRONMENT-MAX
definition
minimizing redundant checking
misses errors if too small
using
EQUATION
definition , ,
examples
2.5D MB extraction
colinear edge correction
conjunctive rules
contact resistance
diffusion resistance
extract colinear edge capacitance
omit for default equation
EQUIV
in SPICE netlists with node numbers
preparing the netlist
ERC
flat processing moved from HDRC
hierarchical
rules file examples
error cells
composite
HDRC
HERC
for CELL-ERROR-REP=ALL
for CELL-ERROR-REP=HIER
for CELL-ERROR-REP=ONCE
Hcell
HDRC
HERC
names
exact size checks
examples
2.5D MB piecewise analysis
2D3B capacitance
antenna check
colinear
capacitance extraction ,
sidewall capacitance correction
colinear edge capacitance ,
conjunctive rules
contact resistors ,
controlling contact resistor cuts
corner check
correcting sidewall capacitance for resistor cuts
diffusion resistors
directional sidewall capacitance ,
electromigration checks
fuse extraction
gate width to contact area
gate width to contact perimeter
gate width/length to contact area
gate width/number to contact area
exact size checks
flattening layers to extract capacitance
fringe capacitance in PRE
fuse extraction
gate width check
HCELL FRAME BY
in-the-direction-of checks
metal and poly resistors
overlap and sidewall capacitance ,
over-the-cell routing overlap capacitance with cell geometries
pad check
poly resistors
region option with spacing checks
sheet resistance
sidewall capacitance with fringing effects ,
single-layer fringe capacitance ,
two-layer fringe capacitance ,
two-layer metal parasitics
EXCEPTION-ON
definition
use for hierarchical SIZE
use to avoid redundant checking
use to disallow Hcell overlaps
with EXPLODE
EXPAND stage
EXPLODE
A option for merging cell and composite data
connections made with
example
extracting capacitance with
in rules file
EXT
can’t be used hierarchically
extract contact perimeter
pad check
R and R' region options for edge checking
RT options for measuring edge length
sizing R' results in edge checking
TR options in electromigration check
use to extract perimeter of contacts
when flat layers are required
extraction
capacitance ,
colinear edge capacitance ,
contact perimeter
devices
fuse network
hierarchical
layer purposes
nodal information ,
resistance ,
single net
text for HLVS
extractParasitic()
2D3B parasitics
colinear edge capacitance
contact resistance
description
directional sidewall capacitance
examples
four metal layers
two metal layers
layer definition
limitations
one-layer fringe capacitance
overlap capacitance
resistance
sheet resistance
sidewall capacitance
single-net extraction
syntax
two-layer fringe capacitance

F

fabrication effects
feedthroughs
files
.erc
.inp ,
See log file
.mlg ,
.msm ,
.sum ,
See DSPF file
See EDTEXT
gen.rul
See GEN-TEXT-FILE
See HCELL-FILE
HDRC output
See HEDTEXT
HERC output
InQuery
See PRINTFILE
See rules file
See SPICE
flagging angles
flat mode
description
for distributed processing
use for large number of overlapping cells
when to use
FLATTEN
definition ,
examples
extracting capacitance
pad check
for large-value spacing checks
for pad layer
flattening
checks that require
EXPLODE
for HDRC nodal checks
generated pad layer
move from HDRC to HERC
not required for HERC/HLVS
to extract capacitance
FLATTEN-PWRGND
definition
using
format conversion
FRAME BY
and Hcell bounding box
and HERC
for composite-mode HLVS
may mask potential problems
not used in HERC
frames
for HLVS
using GEN-TEXT-FRAME
using HCELL FRAME BY
FRINGE CAP
definition
examples
interconnect in PRE
two-layer fringe
two-layer metal
using resistor terminals
R option extracts capacitance in resistor layers
replaced by extractParasitic()
fringe capacitance
2.5D MB considerations
CLL value in 2.5D MB
debugging
definition
effects on sidewall capacitance
extracting with extractParasitic()
in PRE
piecewise analysis ,
single layer ,
TPR value in 2.5D MB
two-layer ,
FTHRU#
functions
See AND
antenna checks
See ATTACH
See ATTRIBUTE CAP
See ATTRIBUTE RES
See BASE-LAYER
See BREAK
See CALCULATE
See CASE
CELLBNDY
See CELLBOX-LAYER
See CELL-CHILD-TEXT
See CELL-ERROR-REP
See CHECK-MODE
See CHKPAR
See CNAMES-CSEN
See COMPUTE
See CONNECT
CONNECT-LAYER
See CORNER
See CTEXT
See CUT
See CUT-TERM
See EDTEXT
See ELCOUNT
See ELEMENT
See ENC
See ENVIRONMENT-MAX
See EQUATION
See EXCEPTION-ON
See EXPLODE
See EXT
extraction
capacitance ,
resistance ,
See extractParasitic()
See FLATTEN
See FLATTEN-PWRGND
See FRINGE CAP
See GEN-TEXT-FILE
See GEN-TEXT-FLTNODE
GEN-TEXT-FRAME
See GEN-TEXT-LAYER
GEN-TEXT-WIRE
grouping
See HCELL
HCELL-COLUMN-1
See HCELL-FILE
See HCELL-HEIGHT-LIM
HCELL-MAX-PLACEMENTS ,
See HCELL-MAX-SEGMENTS
See HCELL-RULE
See HEDTEXT
HERC
See HIERARCHEN
HLPE and HPRE
HLVS
See INDISK
See INDISK-FILE
KEEPDATA
See LENGTH
See LEXTRACT
See LIBRARY
LINK
See LPESELECT
See LVSCHK
See MODEL
See MULTILAB
NEIGHBOR
See NOT
See NOT-HCELL
See PAD-LAYER
See PARASITIC CAP
PARASITIC DIO
See PARASITIC RES
See PARSET
See PATHCHK
PLENGTH
See PRINTFILE
RAM-CELL
See RCONNECT
See RCONNECT-LAYER
RELOCATE
requiring flat layers
See RSPFSELECT
SCONNECT
See SELECT
See SIZE
SMART-LPE
SOFTCHK
See STAMP
SUBNODE-DELIM
SYSTEM
See TEXT
See TNAMES-CSEN
TRANSISTOR
TRANSISTOR-NUM
See UNIT
See WIDTH
fuse extraction

G

gate arrays
CELLBNDY with
limitations
using BASE-LAYER
gates
bent, measuring width of
finding width
parasitic resistor terminals
ratio of width to contact area
ratio of width to contact perimeter
ratio of width/length to contact area
ratio of width/number to contact area
sorting by number in series
sorting by size
GDSII
converting rules file to Cadence-format input
database conversion
input format
output from Virtuoso
GEN-TEXT
functions to extract Hcell text
using to create text file
using to text hierarchy
GEN-TEXT-FILE
definition
for HLVS cell mode
using
GEN-TEXT-FLTNODE
definition
using for feedthroughs
GEN-TEXT-FRAME
GEN-TEXT-LAYER
definition
example
using
GEN-TEXT-WIRE
GENXCN
GLOBAL
add to HLVS netlist
preparing the netlist
global signals
adding to all subcircuits
adding to SPICE/CDL netlist
removing from SPICE/CDL subcircuits
ground
flattening text from Hcell to composite level
global signal in SPICE/CDL netlist
included in extraction
netlisted by CDLOUT
required for capacitance extraction
text requirement
cell mode
composite mode
grouping functions

H

HCELL
and automatic Hcell selection
definition , ,
for HLVS cell mode
for HLVS composite mode
FRAME BY option
HLVS example
selection criteria
using to alter selection criteria
HCELL-COLUMN-1
HCELL-FILE
definition , ,
to correct case of names
to match schematic and layout names ,
HCELL-HEIGHT-LIM
definition ,
using to alter selection criteria
HCELL-MAX-PLACEMENTS ,
HCELL-MAX-SEGMENTS
definition ,
using to alter selection criteria
HCELL-RULE
definition
using to alter selection criteria
Hcells
.SUBCKT requirement for HLVS
altering selection criteria
bounding boxes
bringing up child cell text
candidates
checking in cell mode
choosing to improve performance
correcting case of cell names
cross-referencing names between schematic and layout ,
disallowing overlap
error cells ,
extracting text for HLVS
feedthroughs
frames in HLVS
frames not used in HERC
global signals
improving performance ,
list of candidates
minimizing redundant checking
multilevel criteria
multiple levels
no candidates identified
over-cell wire capacitance
overlapping ,
selecting
for cell mode
for multilevel mode
to improve performance
text from external files
cell
composite
text from layout
cell
composite
text layer limitations
text requirements
cell mode
composite mode
using GEN-TEXT to supply text
verifying in cell mode
what is checked in hierarchical mode
HDRC
areas processed
automatic Hcell selection
ENVIRONMENT-MAX used in
error cells
flat checks in
generates Hcell error cells
grouping checks to improve performance
hierarchical mode
multilevel mode
for memories
using
output files
rules file
limitation ,
writing
what is checked in composite mode
when flat layers are required
HEDTEXT
created by GEN-TEXT-FILE
definition
for composite mode
generated by GEN-TEXT
layer for GEN-TEXT
to correct case problems
HERC
error cells
output files
rules file
run modes
run with HLVS and HLPE
SHORTBOX cell
what is checked in composite mode
HIERARCHEN
definition
used in rules file
hierarchical mode
checks that can’t be used
description
product supported
when to use
hierarchy
checks that can’t be used
extracting a complete netlist
for HDRC
location of Hcells in
multiple levels
RC extraction limitations
texting with GEN-TEXT
using in Dracula
HLPE
extracting a netlist of the complete database
over-cell wire overlap capacitance
rules file 181
run HERC with
what is checked in composite mode
HLVS
extracting text in cell mode
netlist for
rules file
limitation ,
writing
run HERC with
what is checked in composite mode
HPRE
composite mode for timing
resistance extraction limitations 181
rules file 181
what is checked in composite mode
htv command

I

INDISK
converting GDSII rules to Cadence
when to use
INDISK-FILE
contents
use to reference libraries
input formats
Applicon
Cadence
converting
GDSII ,
InQuery
installation
hierarchy
instructions
instdir
INT
R and R' region options for edge checking
RT options for measuring edge length
when flat layers are required
interface, Dracula To RCX
See dracToRCX
in-the-direction-of checks
italics in syntax 10

J

junction resistance

K

KEEPDATA = INQUERY
keywords 10

L

L option for SIZE
LABEL, when flat layers are required
layers
associating comments with
Cadence syntax
DFII syntax
for MULTILAB check
for parasitic capacitance with extractParasitic()
grouping to improve performance
intervening, no connection made
master layer for CONNECT
purposes
using layer purpose pairs
layout
See also database
features that prevent connection
feedthroughs on
overlapping cells
Virtuoso output
x-to-y ratio problem
LENGTH
can’t be used hierarchically
exact contact size check
input always partial edges in conjunctive checks
LEXTRACT
definition , ,
examples
2.5D MB extraction
antenna checking , , , ,
colinear edge capacitance
colinear edge correction
conjunctive rules
contact resistance
diffusion resistance
directional sidewall capacitance
electromigration check , ,
omit for default equation
use in Flexible LPE
libraries
file requirements for Cadence input
license server requirements for Cadence input
multiple Cadence-format
specifying path
verified in cell mode
LIBRARY
converting GDSII rules file to Cadence
when to use
license server daemon
LINK, when flat layers are required
literal characters 10
log file
EXPAND stage for Hcell selection statistics
HDRC
HERC
reallocating memory
logical operations
checking for exact contact size
creating a pad layer
creating capacitor recognition layers
creating resistor recognition layers
examples
antenna checking ,
capacitor recognition layers
colinear sidewall correction
create field poly
creating CMOS device layers
creating contact layers
creating parasitic diode layers
exact size checking
finding gates of different sizes
finding gates that are/are not in series
finding source/drain contacts
flat layers for capacitance extraction
pad check
extracting devices
extracting parasitic capacitance
passing node information
results in HDRC output cells
LOGLVS
CASE function for Cadence-format input data
htv command to generate InQuery files
using for HLVS
LPE
extracting parasitic capacitance
hierarchical
rules file examples
using external files
LPECHK
example
location in rules file
not needed in antenna check rules file
LPESELECT
A option to include power/ground nodes
C option to output cross-coupled capacitance
definition ,
examples
2.5D MB extraction
contact resistance
contact resistors
controlling contact cuts
debugging colinear edge capacitance
extracting colinear edge capacitance ,
extractParasitic()
fuse extraction
simple capacitance ,
simple metal and poly resistors ,
single-layer fringe capacitance ,
two-layer fringe capacitance ,
two-layer metal resistors
not needed in antenna check rules file
piecewise analysis
S option for schematic node names ,
T option includes power/ground in report
to specify netlist name
lump-sum capacitances
between internal cell nodes and parent cell nodes
definition
in hierarchical extraction
LPESELECT C option omits
LVS
hierarchical
matching devices
rules file example
using external files
LVSCHK
example ,
location in rules file
not needed in antenna check rules file

M

masking process effects
master layer for network connection
memories
checking using RAM-CELL
choosing Hcells
environment
HDRC for
multilevel HDRC for
metal reflection checks
avoiding false errors
example
metal resistors
four metal layers
one metal layer
two metal layers ,
minimizing disk space
composite mode
hierarchical mode
MODEL
definition
modes
cell
Hcell error cells
HERC
HERC MULTILAB errors
HLPE
HLVS
HLVS cell names ,
using BASE-LAYER
when to use
composite
HERC ,
HLPE
HLVS ,
HLVS cell names ,
HLVS frames
using BASE-LAYER
when to use
distributed
flat
description
for distributed processing
use for large number of overlapping cells
when to use
for HDRC
for hierarchical products
hierarchical
automatic Hcell selection
error output ,
FLATTEN
Hcell error cells
improving performance
when to use
multilevel
memories and arrays
when to use
modules for dracToRCX
MULTILAB
layers in output cell
SHORTBOX cell for
multilevel mode
description
for memories
when to use

N

NEIGHBOR in large spacing checks
netlist
compiling for HLVS
no feedthroughs in
preparing for HLVS
SPICE/CDL
for cell mode LVS/LPE
with node numbers
NMOS
device extraction
rules file examples
nodal information
checks and operations in flat mode
composite node numbers assigned by EXPLODE
extract for electromigration check
extract to use in antenna checking
for divided contact
for single node
fringe capacitance between different nodes
MULTILAB
node names in SPICE file
node numbers in netlist
passed by AND and NOT
requires flat layers
STAMP for antenna checking
texting for cell mode
transfer with AND
transfer with STAMP
use by HDRC and HERC
node names
attached to layers with GEN-TEXT-LAYER
changing SPICE node numbers to
global in SPICE/CDL
LVSCHK outputs schematic node names
NOPIN
preparing the netlist
removing global signals from a subcircuit
NOT
grouping to improve performance
passing nodal information
NOT-HCELL
definition
using to alter selection criteria

O

output
associating comments with
bounding box overlay
cell-mode netlist
composite-mode netlist
EXPLODE options
generating for capacitance extraction ,
generating for resistance extraction ,
HDRC
HEDTEXT file
HERC
LPESELECT options
of CUT function
schematic node names
selecting capacitance format
viewing shorts with SHORTBOX
overlap capacitance
definition
example ,
rules file
two-layer metal
with fringing effects
overlap perimeter
definition
example
used in sidewall-down capacitance calculation
overlapping Hcells
disallowing overlap
minimizing redundant checking
over-the-cell wire overlap capacitance
OVPR
definition
examples
2.5D MB
colinear edge capacitance
colinear edge correction
conjunctive rules
correcting capacitance for resistor cuts
diffusion resistors
directional sidewall capacitance
in Flexible LPE

P

pad layer
flattening in HDRC
generating for resistance extraction
requirement for extracting resistance
PAD-LAYER
definition
for composite mode
terminates resistance
using
pad-to-metal check
parameters
examples
2.5D MB extraction
antenna checking
colinear edge capacitance
colinear edge correction
contact resistors
correcting capacitance for resistor cuts
diffusion resistors
directional sidewall capacitance ,
electromigration , ,
in Flexible LPE
parameter set
PARASITIC CAP
2.5D MB extraction
constants
definition
examples
colinear edge capacitance
correcting capacitance for resistor cuts
directional sidewall capacitance
internal cell nodes to parent cell nodes
simple capacitance
single-layer fringe capacitance
two-layer metal
piecewise analysis
replaced by extractParasitic()
PARASITIC DIO
See capacitance; resistance
PARASITIC RES
constants
definition
examples
contact
controlling contact cuts
diffusion
fuses
simple metal and poly
two-layer metal
replaced by extractParasitic()
PARSET
creating subtypes
definition
examples
2.5D MB extraction
antenna checking , , , , ,
colinear capacitance
colinear edge correction
contact resistors
correcting capacitance for resistor cuts
diffusion resistors
electromigration , ,
in Flexible LPE
not required with extractParasitic()
omit for default equation
PATHCHK
in HERC composite run
results passed to Hcell pins
performance
See also run times
improving by choosing Hcells
improving by grouping functions
PERI
perimeter
contacts
for sidewall capacitance with fringing effects
in capacitance output format
in EQUATION
in extractParasitic()
on one layer
overlapping a second layer
piecewise analysis ,
PIN
add to HLVS netlist
preparing the netlist
pin purpose input
PLENGTH
poly resistors ,
power
flattening text from Hcell to composite level
global signal in SPICE/CDL netlist
included in extraction
netlisted by CDLOUT
required for capacitance extraction
text requirement
cell mode
composite mode
PRE
cell mode limitation
extracting fringe capacitance
extracting parasitic resistance
hierarchical
rules file example
using external files
PRINTFILE
HDRC output files
HERC output files
purposes

R

R option
edge checking
flagging angles
measuring edge length
sizing results
R' option
RAM-CELL
ratios
area sum, antenna
field poly to gate
gate width to contact area
gate width to contact perimeter
gate width/length to contact area
gate width/number to contact area
layer to devices on node
layout x-to-y
maximum area, antenna
minimum area, antenna
smaller of sum of areas, antenna
RCONNECT
definition
examples
contact resistors
controlling contact cuts
correcting capacitance for resistor cuts
diffusion
simple metal and poly
two-layer metal
RCONNECT-LAYER
contact resistors illustration
definition
examples
contact resistors
diffusion
fringe capacitance in PRE
simple metal and poly
two-layer metal
reducing disk space
composite mode
hierarchical mode
reflection rules
avoiding false errors
example
region options
RELOCATE
resistance
2.5D MB
accuracy
contact ,
controlling contact cuts
corner
correcting sidewall capacitance for
creating recognition layers
debugging
diffusion
four-layer metal
hierarchical extraction limitations
junction
pad layer required
poly
sheet
simple metal and poly ,
single net
terminals used for fringe capacitance
two-layer metal ,
validate capacitance before extracting
resolution unit
creating corner markers
criterion for edge length check
represents perimeter in electromigration check
used to convert edge portions to full edges
width of border in creating corner marker
width of error flags in region edge check
rotation
and RAM-CELL
to correct x-to-y ratio problem
RSPFSELECT
definition ,
rules file
Cadence-format input
capacitance
2D3B
colinear sidewall
correct for resistor cuts
debugging colinear capacitance
directional sidewall ,
fringe capacitance in PRE
overlap and sidewall ,
sidewall capacitance with fringing effects ,
single-layer fringe ,
two-layer fringe ,
two-layer metal
converting GDSII input to Cadence input
creating
database format conversion
DFII layer syntax
electromigration , , , ,
fuse extraction
HDRC/HLVS limitation ,
HLPE 181
HLVS ,
HPRE 181
mixing flat and hierarchical commands
optimizing
output error cells in HDRC
parasitic extraction ,
piecewise analysis ,
resistance
contact , ,
controlling contact cuts
diffusion
four-layer metal
metal and poly resistors ,
two-layer metal ,
single-net extraction
using BASE-LAYER
using TEXT and CTEXT
run modes
cell
composite
distributed
flat
hierarchical
multilevel
run times
HDRC limitations
reducing with black box LVS
reducing with distributed Dracula
reducing with Hcell selection
reducing with hierarchical mode

S

S option
ENC
LPESELECT ,
SCONNECT
SELECT
grouping to improve performance
results in HDRC output cells
when flat layers are required
SHORTBOX cell
sidewall capacitance
2.5D MB considerations
colinear edge correction
sidewall-down ,
sidewall-up ,
with fringing effects ,
signals
correcting case of signal names
global
adding to SPICE/CDL netlist
removing from subcircuits in netlist
single-net extraction
SIZE
B and L options for sizing regions
creating pad layer
creating pad layer in composite mode
for in-the-direction-of checks
for pad check
on the result of region operations
results in HDRC output cells
using for hierarchical sizing
sizing
for edge checks
for flattened pad layer check
for in-the-direction-of checks
hierarchical
to account for process effects
to create pad layer
SMART-LPE
SOFTCHK in HERC composite run
See ENC; EXT; INT; WIDTH
SPFSELECT
definition ,
examples
simple metal and poly resistors
SPICE
changing node numbers to node names
for cell mode LVS/LPE
global signals in
STAMP
definition
examples
antenna checking , ,
contact resistors
diffusion resistors
sidewall capacitance
simple metal and poly resistors
two-layer metal
when flat layers are required
subcircuits
global signals
in HLPE netlist
names must match layout for HLVS/HLPE ,
pin names for HLVS/HLPE
removing global signals
required for composite mode HLVS
required for HLVS Hcells
used to generate text for LVS
SUBNODE-DELIM
swap space, preallocating
syntax conventions 10
SYSTEM function for Cadence rules file

T

T option
LPESELECT
spacing checks
TEXT
See also EDTEXT; HEDTEXT; text
for Cadence-format input data
limitation ,
using
text
bringing up to Hcell level
cell mode requirements
excluded by FRAME BY
extracting from layout
cell
composite
flat mode requirements
from external files
cell
composite
generating with GEN-TEXT
Hcell layer limitations
hierarchy
in Cadence-format input data
in HDRC
in HERC/HLVS
requirements for composite mode
using cell mode to extract
TNAMES-CSEN
for Cadence-format input data
TPR
calculation
definition
TR options
TRANSISTOR
TRANSISTOR-NUM
transistors
estimate to preallocate swap space
not required in composite mode HLVS

U

UNIT
definition ,
examples
antenna checking
single-layer fringe capacitance
two-layer fringe capacitance
output in SPICE file

V

Virtuoso

W

WIDTH
exact contact size check
R and R' region options for edge checking
sizing R' results in edge checking
using to create resistor recognition areas
width
for exact size checks
fringe capacitors
gate
finding with EXT
in electromigration calculation
wire
current flow of parasitic resistors on
fringe capacitance
overlap capacitance, over-the-cell
over-the-cell overlap capacitance
types automatically generated

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