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Contents

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Preface

Related Documents

Typographic and Syntax Conventions

1

Interfaces to Dracula

Overview of This Chapter

Using Cadence Data in Dracula

Preparing To Use a DFII Database

Specifying the Path to Your Layout

Controlling Case Sensitivity

Extracting Objects from a DFII Layout

Sample Rules File

Converting a GDSII Rules File for Cadence Input

2

Writing Rules for Dracula

Writing Dracula Rules Files

Using Rules File Examples

Techniques for Preparing Your Rules File

Writing DRC Checks

Writing Antenna Checks

Writing In-the-Direction-Of Checks

Writing Exact Contact Size Checks

Writing Metal Reflection/ Crosstalk Checks

Writing Electromigration Checks

Writing Corner Checks

Writing Edge Checks

Defining Devices

Connecting Your Network

Determining the Master Layer

Connecting Multiple Layers

Preparing To Use Dracula Interactive

3

Working With 32 and 64-bit Applications

4

Selecting a Run Mode

About Run Modes

Using Flat Mode

Running Dracula in Flat Mode

When To Use Flat Mode

Verifying Gate Arrays

Texting for Flat Mode

Using Dracula Distributed Processing

When To Use Dracula Distributed Processing

Using Hierarchical Mode

Running Dracula in Hierarchical Mode

What the Hierarchical Design Rule Checker Checks

When To Use the Hierarchical Design Rule Checker

Using Multilevel Mode

Running Dracula in Multilevel Mode

Selecting Hcells for a Multilevel Run

When To Use Multilevel Mode

Using Cell Mode

Running Dracula in Cell Mode

When To Use Cell Mode

Texting for Cell Mode

Using Composite Mode

Running Dracula in Composite Mode

Checks in Composite Mode

When To Use Composite Mode

Composite Mode and Blackbox LVS

Texting for Composite Mode

Improving Performance

Grouping Functions

Preallocating Swap Space

Optimizing Rules

X-to-Y Ratio of the Circuit

5

Extracting RC Parasitics

About RC Extraction

Ensuring Accuracy in RC Extraction

Providing Constants

Adjusting Your Design Database for Fabrication Effects

Using Equations with Flexible LPE

Extracting Parasitic Capacitance

Preparing To Extract Capacitance

Constants for Debugging Capacitance

Extracting Overlap and Sidewall Capacitance

Extracting Directional Sidewall Capacitance

Correcting for Colinear Sidewall Capacitance

Extracting Single-Layer Fringe Capacitance

Extracting Two-Layer Fringe Capacitance

Extracting Over-the-Cell Routing Wire Overlap Capacitance with Cell Geometries in HLPE

Extracting Parasitic Resistance

Preparing to Extract Resistance

Creating Resistor Recognition Layers

Extracting Simple Metal and Poly Resistors

Extracting Two-Layer Metal Parasitics

Extracting Contact Resistors

Extracting Diffusion Resistors

Correcting Sidewall Capacitance

Extracting Fringe Capacitance in PRE

Controlling How Contacts Are Cut

Extracting 2.5D MB Parasitics

Dracula 2.5D MB Capabilities

Using Piecewise Analysis

Extracting Sidewall Capacitance with Fringing Effects

Using One Function to Extract RC Parasitics

Defining Parasitics Layers

Extracting Overlap and Sidewall Capacitance

Extracting Directional Sidewall and Colinear Edge Capacitance

Extracting 2D3B Capacitance

Extracting One- and Two-Layer Fringe Capacitance

Modifying the Coefficient Generator Interface with Dracula to Improve LPE Accuracy

Extracting Sheet Resistance

Extracting Multiple Resistance on the Same Metal Layer

Extracting Contact Resistance

Capacitance or Resistor Model in the Extracted Netlist

Function Syntax

Before You Start

Creating Additional Subtypes

Examples

Extracting a Single Net

Before You Start

Coding Single-Net Extraction

The Dracula To RCX (dracToRcx) Interface

Module Descriptions

RCX Commands

Running the DracToRCX Interface

6

Setting up Hierarchical Dracula

About Hierarchical Dracula

Prerequisites

Hierarchical Products and Modes

Running a Hierarchical Design Rule Check

Writing Hierarchical Design Rules

Checking Memories and Arrays

Using HDRC Output

Selecting Hcells

Selecting Hcells Automatically

Selecting Hcells Manually To Improve Performance

Running a Multilevel Design Rule Check

Understanding Multilevel Processing

Running a Multilevel Hierarchical DRC

Running a Hierarchical Electrical Rules Check

Writing Hierarchical Electrical Rules

Deciding What To Check

Connecting the Network

Flattening Power and Ground Text

Excluding Hcell Geometries in HERC

Using Composite Plane Geometries in Hcells

Using HERC Output

Running a Hierarchical Network Comparison

Writing Hierarchical Network Comparison Rules

HLVS Prerequisites

Excluding Hcell Geometries in HLVS

Using Cell Boundaries

Marking Feedthroughs on the Layout

Using a Cross-Reference File for Hcell Names

Preparing Your Netlist

Compiling Your Netlist

Running Hierarchical Parameter Extractions

About Hierarchical Parameter Extraction

Writing Parameter Extraction Rules

Using a Cross-Reference File for Hcell Names

Using HLPE To Extract a Complete Netlist

Making Hierarchical Dracula Run Faster

Maximizing Operations

Minimizing Redundant Checking

Altering the Hcell Selection Criteria

Index

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