Product Documentation
Dracula User Guide
Product Version IC23.1, September 2023

6

Setting up Hierarchical Dracula

In this chapter, you’ll learn about the following:

About Hierarchical Dracula

You can use the Dracula hierarchical tools (HDRC, HERC, HLVS, HLPE, and HPRE) on hierarchical designs in the same way you use the corresponding tools on flat designs. The basic differences are as follows:

In the sections that follow, you will learn

For more information about when to use hierarchical Dracula, see Chapter 4, “Selecting a Run Mode.”

Prerequisites

To run hierarchical Dracula, you must know how to run the Dracula verification tools in flat mode.

Also, you need to be familiar with how Dracula forms a two-level hierarchy consisting of the composite and Hcell planes. For a complete description of how Dracula constructs its hierarchy, see “Hierarchical Structure” in the “Overview” chapter of the Dracula Reference.

Hierarchical Products and Modes

This table shows the products you can run in hierarchical Dracula and the modes you can use to run them. For more information about these modes, see Chapter 4, “Selecting a Run Mode.”

CHECK-MODE= HDRC HERC HLVS HLPE HPRE

HIER

x

CELL

x*

x

x

x

COMP

x*

x

x

x

x

MULTI

x

Running only cell and composite mode HDRC is not recommended because these modes do not provide Hcell-to-Hcell or Hcell-to-composite checks. Use hierarchical mode instead.

Running a Hierarchical Design Rule Check

You use hierarchical Dracula in the same way you use flat Dracula to check your design rules. When you run a hierarchical design rule check (HDRC) job, Dracula verifies your database completely. Hierarchical Dracula checks cells with highly repetitive placements only once, and then checks them against the surrounding geometries. The hierarchical output is easier to debug than flat output because errors are reported only once for all placements of a given cell.

You might need to use some or all of the hierarchical functions listed in the following table. To find more information about using the function, look in the Description column of the table.

Writing Hierarchical Design Rules

The rules file you use for a hierarchical DRC run is essentially the same as a rules file for a flat run, with the addition of several hierarchy-related functions. The following table lists the hierarchical functions that you might want to include. For more information about these functions, see the Dracula Reference manual.

You cannot use the LENGTH, EXT[G], and RELOCATE functions in hierarchical rules files. Also, you must use flat layers for nodal functions, as described in the “Using Flat Layers for Nodal Information” section

.

Hierarchical Functions for HDRC
Function Description Rules file block

CELL-ERROR-REP

Specifies the format of cell-based error segments generated by HDRC; ONCE, HIER, ALL, ORIG-ALL, ORIG-DRC, or cellname. See Using HDRC Output.

*DESCRIPTION

CELLBOX-LAYER

Creates cell boundaries for each Hcell on the layer you specify. See Using Cell Boundaries.

CHECK-MODE

Set to HIER for HDRC.

*DESCRIPTION

ENVIRONMENT-MAX

Specifies the upper limit for the width of the Hcell environment. See Specifying a Maximum Environment Value.

EXCEPTION-ON

Set to [HSP-OUTPUT] and use with SIZE to output SIZE results hierarchically. This option also disallows overlapping Hcells during automatic Hcell selection. See Preventing Hcell Overlap.

HCELL

Specifies which cells are Hcells. See Altering the Hcell Selection Criteria.

HCELL-FILE

Specifies a file containing a set of HCELL statements. See Using a Cross-Reference File for Hcell Names.

HCELL-HEIGHT-LIM

YES sets a limit of 1000 microns for the maximum Hcell height. NO specifies that there is no height limit.

HCELL-MAX-SEGMENTS

Specifies the maximum number of line segments for a cell to be an Hcell candidate, to avoid selecting large cells.

*DESCRIPTION

HCELL-MAX-PLACEMENTS

Specifies the maximum number of placements for a cell to be an Hcell candidate, to avoid selecting small cells with a large number of placements.

HCELL-RULE

Specifies the minimum number of placements and segments for a cell to be an Hcell candidate.

NOT-HCELL

Specifies cells that cannot be Hcell candidates.

CELLBNDY

Specifies the digitized layer that contains rectilinear cell boundaries. See Using Cell Boundaries.

*INPUT-LAYER

FLATTEN

Creates a flat layer from a hierarchical layer. See Flattening Layers.

*OPERATION

HIERARCHEN

Creates a hierarchical layer from a flat layer.

Specifying a Maximum Environment Value

When you run HDRC in hierarchical mode, Dracula surrounds every Hcell with a box that extends beyond the Hcell for a given distance. This distance is called the “environment value.” Dracula automatically sets the environment value to be equal to the largest value used in any spacing check in the Operation block on data that has not been flattened.

Composite geometries that fall within the environment area are checked as part of the Hcell, as shown:

The larger the environment value, the larger the amount of composite data that is checked for each Hcell instance.

For example:

ENVIRONMENT-MAX = 10 MIC
;
; <functions omitted>
;
EXT      METAL           LT  5.0      OUT      METERR55
ENC      CONT    METAL   LT  1.5      OUT      CONERR56
EXT      POLY    DIFF    LT  3.0      OUT      PLYERR57
EXT      PAD     METAL   LT  30.0     OUT      PADERR58

The default environment value for this job is 30 microns. In this case, Pdracula warns you that the 30 micron spacing check exceeds the maximum environment value of 10 microns.

In response to the warning, you can do one of the following:

If the ENVIRONMENT-MAX value you set is larger than the largest spacing check value, Dracula reduces the environment value to the lower spacing check value.

The ENVIRONMENT-MAX function works with HDRC hierarchical mode only.
If you set ENVIRONMENT-MAX to 1 micron and you do a 3-micron spacing check, Dracula can miss errors. An error that is 2 microns out is not included in the environment.

Preventing Hcell Overlap

While selecting Hcells automatically, Dracula might choose overlapping cells. If the amount that two Hcells overlap is greater than half the area of either of the Hcells, Dracula chooses only one of the cells as an Hcell. Generally, Dracula chooses the cell with the least amount of overlapped data.

Dracula expands cells that do not qualify as Hcells and brings them up to the composite level. If the cells are nested in an Hcell, Dracula brings them up to the Hcell level and maps them to that instance of the Hcell.

Some designs run more efficiently in hierarchical mode if the Hcells Dracula uses do not overlap. 

 EXCEPTION-ON = [HSP-OUTPUT]

This function prevents Dracula from choosing as an Hcell any cell that overlaps another cell.

You can also include EXCEPTION-ON = [HSP-OUTPUT] when you use the hierarchical SIZE function, so the results will be clean and correct.

Flattening Layers

The FLATTEN function creates a new flat layer at the top level from a hierarchical layer. It is useful only in hierarchical mode. In flat mode, the FLATTEN function uses the UNIX cp command to copy data from one file to another file with a different name.

You might need to use FLATTEN in your HDRC rules to do

You can also use FLATTEN in HLPE to extract capacitors between an internal cell node and a parent cell. See the “Flattening Layers To Extract Capacitance” section.

You can use both hierarchical and flat layers in the Operation block of an HDRC rules file, but you cannot combine hierarchical and flat layers in a single check.

Avoiding Flat Processing

If you want to take full advantage of the hierarchy of your circuit when running HDRC, you can merge any operations that require flat layers into an ERC job rather than including them in an HDRC job.

Large Spacing Checks

Dracula uses the spacing value for hierarchical checks to determine the environment value, as described in the section about Specifying a Maximum Environment Value. However, Dracula does not include checks on flat layers when determining this value.

Pad-to-metal checks normally use large spacing values and involve many geometries. To avoid affecting the environment value, use the FLATTEN function on the pad and metal layers. To reduce the amount of data that you must process, which in turn reduces the processing time, use logical operations.

The following example creates a layer, PMET, consisting of metal geometries no farther than 30 microns from the pad geometries. Then PAD and PMET are flattened and used in the 30 micron spacing check. 

; The NEIGHBOR function does these two operations:
; SIZE PAD BY 30 SPAD
; AND SPAD METAL PMET
;
NEIGHBOR METAL PAD 30 PMET
;
; <functions omitted>
;
FLATTEN PAD FPAD
FLATTEN PMET FMET
EXT[V] FPAD FMET LT 30 OUT PADERR 58

With these functions, you can perform relatively few large dimensional checks without affecting the performance of the entire HDRC run.

Using Flat Layers for Nodal Information

You must use flat layers for the following HDRC checks and operations that require nodal information:

For information on different flattening requirements for HDRC and HERC, see “Connecting the Network” section.

Checking Memories and Arrays

To process large arrays and memories, you can use the following HDRC features:

The Hcell you specify for the RAM-CELL function must be a repetitive cell with simple, nonrotated placements. Composite geometries cannot overlap the core Hcells in the array.

Using HDRC Output

You view and correct errors from an HDRC run the same way you do for a flat run. The error cells can contain Hcell and composite geometries. Dracula organizes the content of the cells according to the option you specify with the CELL-ERROR-REP function. These options are described later in this section.

Viewing Hcell Error Cells

Hcell error cells contain errors associated with Hcells and any pseudolayers created by logical, SIZE, or SELECT operations that occur for all placements of the Hcells.

Dracula generates Hcell error cells when you run an HDRC in either of the following modes:

The following sample circuit contains two Hcells, INV and JKFF. There are two HDRC checks in the rules file:

 EXT  METAL LT  5  OUT METERR 61
 SIZE POLY  BY .25 OUT SPOLY  22

Hcell error cells from these checks appear as shown:

Dracula uses the layer numbers you give for output error layers to isolate the error within the Hcell output. Each output cell contains error flags on layer 61 and sized data on layer 22, if applicable. The origin of these error cells is in relation to the origin of the corresponding layout cell.

Using Error Reporting Options

You can use the CELL-ERROR-REP options to report errors using two different hierarchy structures:

For more information about these options, see the section about “CELL-ERROR-REP” in the “Description Block Commands” chapter of the Dracula Reference.

Viewing a CELL-ERROR-REP = ONCE Error Cell

When you use CHECK-MODE=HIER with CELL-ERROR-REP = ONCE in your rules file, you get an error cell for each check. These cells contain errors that occur

Viewing a CELL-ERROR-REP = ALL Error Cell

The error cells produced when you set CELL-ERROR-REP=ALL in your rules file are the same as the cells produced by a flat Dracula run.

Viewing a CELL-ERROR-REP = HIER Error Cell

When you use CHECK-MODE=HIER with CELL-ERROR-REP = HIER in your rules file, you get

Here is an example of checks in a rules file:

EXT METAL      LT 5 OUT METERR 61
EXT POLY       LT 3 OUT POLERR 62
ENC CONT METAL LT 2 OUT CONERR 63

These rules produce the following HDRC error cells, which you can overlay on both the Hcell and the top-level design:

Listing HDRC Text Output Files

HDRC text output includes the following files:

where printfile is the name you specify with the PRINTFILE function in the Description block of your rules file.

For a complete description and examples of HDRC output, see “HDRC Error Reports” in the “Checking Design Rules (DRC)” chapter of the Dracula Reference.

Selecting Hcells

You usually let Dracula select Hcells automatically by running HDRC in hierarchical mode first. If the results are not satisfactory, you might want to choose your own Hcells.

To select the Hcells to use in hierarchical Dracula jobs, you need to be familiar with how Dracula forms its two-level hierarchy by creating the composite and Hcell planes. For a complete description of how Dracula chooses Hcells, see “Hierarchical Structure” in the “Overview” chapter of the Dracula Reference.

Selecting Hcells Automatically

For hierarchical and multilevel HDRC, Dracula uses default selection criteria to select Hcells automatically. There is one set of criteria for hierarchical HDRC and a different set for multilevel HDRC. You can find a description of these criteria, along with instructions for changing or overriding them, in the “Selecting HDRC Hcells” in the “Checking Design Rules (DRC)” chapter of the Dracula Reference.

If you are running HDRC, but you did not include an HCELL function in your rules file and Dracula cannot identify any Hcells, Dracula automatically switches to flat mode.

Run HDRC with the default Hcell selection first, particularly if you are not familiar with the layout hierarchy. You can look at the following files to determine which cells Dracula chose to be Hcells:

Selecting Hcells Manually To Improve Performance

If your circuit performs poorly in hierarchical mode, you might be able to improve performance by choosing different Hcells.

General Guidelines

Look for Hcells that have all of these qualities:

The challenge is to find Hcells that are both complex and repetitive. If the Hcell is too simple, most of the processing time is spent on bookkeeping. A contact cell is an example of a poor choice for an Hcell. The cell is repeated many times, but is too simple to improve the processing time for a hierarchical check.

Try to pick Hcells that are near the middle of the hierarchy tree. The cells at the bottom of the hierarchy might have many instances, but they are very simple. Cells near the top of the hierarchy are complex, but may only be placed a few times.

Choose few Hcells rather than many. For memory-based designs, for example, a single Hcell is the best choice.

Getting Started

  1. Start with the basic HCELL-RULE function.
    If you have never selected your own Hcells, the following is a good rule to start with. The rule specifies that, to qualify as an Hcell, a cell must be placed more than 5 times if it contains more than 1000 segments, or more than 10 times if it contains more than 500 segments.
    HCELL-RULE 5,1000 10,500
  2. Check the log file for the Hcell area coverage rate.
    After you run Dracula using these criteria, look at the EXPAND stage of the .log file. This part of the file tells you how much of the total area of your design is covered by Hcells that were selected using your criteria. In the following example, the coverage rate is 86.08%.
    */M** TOTAL NUMBER OF EDGES IF FLATTENED =      7673
      NUMBER OF EDGES IN H-CELLS         =      6605
      H-CELL COVERAGE RATE               =      86.08%
      FULL HIERARCHICAL EDGES            =      2959
      2-LEVEL HIERARCHICAL EDGES          =      3039
    Try to pick Hcells to increase the coverage rate and decrease the number of Hcells listed in the CANDIDAT.DAT file. You want the number of Hcells listed to be less than 200.

Running a Multilevel Design Rule Check

For designs on which the standard two-level HDRC does not run as efficiently as you want, you can use multilevel HDRC. Memory chips where overlap is minimal are the best candidates for multilevel HDRC, as described in “Using Multilevel Mode”.

Understanding Multilevel Processing

To process a multilevel design, Dracula creates multiple two-level hierarchies, starting at the top level. The following figure shows the first level of a multilevel design. Dracula creates the composite layer on the top level. It creates frames for the Hcells and checks the composite layer and its connections to the Hcell frames.

The size of the Hcell environment area is the largest spacing value in a hierarchical DRC check (see Specifying a Maximum Environment Value). However, if there are intrusions into the Hcell, the spacing value is increased.

When Dracula has checked the top level, it goes to the next level, which is the cellA Hcell in the previous example. Treating cellA as the top level, Dracula again creates a composite plane with frames around the Hcells that cellA contains. Dracula continues down the hierarchy in this fashion.

Running a Multilevel Hierarchical DRC

You can use an HDRC rules file for multilevel HDRC. See Running a Hierarchical Design Rule Check.

To run a multilevel HDRC, see “Multilevel Mode” in the “Checking Design Rules (DRC)” chapter of the Dracula Reference.

Running a Hierarchical Electrical Rules Check

To check the electrical parameters of a circuit, you use hierarchical Dracula in the same way you use flat Dracula. You verify your cells prior to verifying the top-level design. Then, when you verify the top-level design, Dracula treats cells as blocks with pin names only, and checks only the external connections to other blocks.

Writing Hierarchical Electrical Rules

The rules file you use for an HERC run is the same as the rules file for a flat run, with the addition of several hierarchy-related functions. The following table lists the Dracula hierarchical functions that you might want to include. For more information about these functions, see the Dracula Reference Manual.

In cell or composite modes, HERC functions can be run with HLVS and HLPE functions in the same rules file, because they use the same mechanism for defining Hcell and cell text

.

Hierarchical Functions for HERC
Function Description Rules file block

CELL-CHILD-TEXT

Cell mode only. For a description of this function, see Bringing Text Up to the Hcell Level. (Not recommended — causes HERC errors.)

*DESCRIPTION

CELLBOX-LAYER

Creates cell boundaries for each Hcell in the OUTDISK file. See the section about Using Cell Boundaries.

CHECK-MODE

Set to CELL or COMPOSITE for HERC.

*DESCRIPTION

FLATTEN-PWRGND

Composite mode only. For a description of this function, see Flattening Power and Ground Text.

HCELL

Specifies which cells are Hcells. Mandatory for HERC. (FRAME BY option not recommended — causes HERC errors.) See Altering the Hcell Selection Criteria.

HCELL-FILE

Specifies a file containing a set of HCELL statements. See Using a Cross-Reference File for Hcell Names.

BASE-LAYER

Specifies layers containing composite-level geometries that must be mapped into Hcells. See Using Composite Plane Geometries in Hcells.

*INPUT-LAYER

CELLBNDY

Specifies the digitized layer that contains rectilinear cell boundaries. See Using Cell Boundaries.

*INPUT-LAYER

CTEXT

Specifies the input layer number of Hcell text.

HEDTEXT

Specifies the file containing Hcell text.

*OPERATION

FLATTEN

Creates a flat layer from a hierarchical layer.

XBOX

Checks for composite geometries on the specified layer that touch or overlap Hcell bounding boxes.

XCELL

Checks for geometries from the layer1 composite plane that overlap Hcell layer2 geometries. Checks for geometries from the layer2 composite plane that overlap Hcell layer1 geometries.

XDEVICE

Outputs composite-to-cell and cell-to-cell devices that are not present in the schematics. Composite mode only.

XVIA

Checks for contacts that are not covered by a related conductor layer in either the composite plane or Hcells.

*OPERATION

Deciding What To Check

When you run HERC in cell mode, Dracula verifies only the Hcells in your database.

When you run HERC in composite mode, Dracula does the following:

For a complete verification, you must run both cell mode and composite mode HERC. All checks that you run in composite mode must be the same checks you ran in cell mode.

Connecting the Network

Although you need to flatten layers to do nodal checks in HDRC, you do not need to flatten the layers you use in CONNECT functions for HERC and HLVS.

HDRC doesn’t use Hcell text labels. In the following figure, A, B, and C are all on the same node. The B geometry in the Hcell has text labels on both sides of the Hcell boundary. In a composite mode HDRC, however, Dracula ignores the boundary text and treats A and C as two different nodes, unless you flatten the layers.

HERC and HLVS require and work with labelled Hcell boundaries. For HERC and HLVS, Dracula makes the connection from the text on the Hcell boundary. HERC/HLVS treat A, B, and C as one node, without requiring flat layers.

Flattening Power and Ground Text

You can flatten the power and ground text from the Hcell level to the composite level. This feature is useful in the following cases:

    FLATTEN-PWRGND = YES

In the following example, VDD and VSS from both Hcells are expanded up to the composite level for use with composite mode HERC. If there is a power or ground short from the MULTILAB function, the output error cell, which lists the shortest distance between two texted points, might be shorter because you have more text. See Viewing the SHORTBOX Cell.

Excluding Hcell Geometries in HERC

Although you can use the FRAME BY option with the HCELL function to remove Hcell geometries from processing, there are reasons to avoid this option in HERC:

The FRAME BY option causes false HERC errors and is not recommended for an HERC run.

Using Composite Plane Geometries in Hcells

In hierarchical Dracula, you can form devices solely within Hcells or solely on the composite plane, but not between the composite plane and Hcells. However, you can use the BASE-LAYER function to include portions of composite geometries in your Hcells to form devices.

You might want to create a flat layer on an otherwise hierarchical circuit. For example, you can create cells in a pwell CMOS process that have no pwell layer. Then, after you create the entire circuit, you can create the pwell layer as a flat layer where needed. You need to map the flat or composite pwell geometries to the Hcell so that the Hcell is complete and n-channel devices can be formed in the Hcells.

For example:

*INPUT-LAYER
ACTIVE = 1
POLY   = 2 TEXT = 61 ATTACH = METAL
METAL  = 3
PWELL  = 6
BASE-LAYER = PWELL
CONNECT-LAYERS = NSUB PWELL PSD NSD POLY METAL
* END
*OPERATION
;
; <functions omitted>
;
ELEMENT MOS[N] NGATE POLY NSD PWELL
*END

You need the pwell layer to form the body of n-channel devices in the Hcells. Dracula includes overlapping portions of the pwell layer from the composite plane in the Hcells, as shown in the following figure.

If you use the BASE-LAYER function in cell mode, you must also use it in the subsequent composite mode run to ensure proper verification.

For a complete description of this function, see the section about the “BASE-LAYER” function in the “Input-Layer Block Commands” chapter of the Dracula Reference.

Using HERC Output

You view and correct errors from an HERC run the same way you do for a flat run. The error cells can contain Hcell and composite geometries.

Viewing Cell Mode Error Cells

A sample circuit contains two Hcells, INV and JKFF. The rules file contains this HERC check:

MULTILAB OUTPUT MULLAB 52

When you include checks that have nodal-type output, such as MULTILAB, Dracula produces multiple layers for that check. For example, if your design has 7 connect layers and 4 contact layers, Dracula outputs 11 different layers to carry the nodal information. The INV_CEL and JKFF_CEL output cells in the following figure contain layers 52 to 62, which all have geometries from the MULTILAB check.

To find out what the output layers are, look in your printfile.erc file MULTILAB summary. The layer numbers start at the layer number you specify for the MULTILAB output cell, and increment by one. In the following example, the output layer number the user specified was 40. There were 3 contact layers specified in CONNECT functions and 6 connection layers specified in the CONNECT-LAYER function. The last layer is the SHORTBOX cell, described in Viewing the SHORTBOX Cell.

***** MULTILAB SUMMARY *****
0 TRAPEZOIDS ARE SELECTED FROM 3METAL   TO SHORTS40 AT LAYER   40
0 TRAPEZOIDS ARE SELECTED FROM 3POLY    TO SHORTS40 AT LAYER   41
0 TRAPEZOIDS ARE SELECTED FROM 3PSD     TO SHORTS40 AT LAYER   42
0 TRAPEZOIDS ARE SELECTED FROM 3NSD     TO SHORTS40 AT LAYER   43
0 TRAPEZOIDS ARE SELECTED FROM 3PWELL   TO SHORTS40 AT LAYER   44
0 TRAPEZOIDS ARE SELECTED FROM 3NSUB    TO SHORTS40 AT LAYER   45
0 TRAPEZOIDS ARE SELECTED FROM 030CONT  TO SHORTS40 AT LAYER   46
0 TRAPEZOIDS ARE SELECTED FROM 030NTAP  TO SHORTS40 AT LAYER   47
0 TRAPEZOIDS ARE SELECTED FROM 030PTAP  TO SHORTS40 AT LAYER   48
0 TRAPEZOIDS ARE SELECTED FROM SHORTBOX TO SHORTS40 AT LAYER   49

Viewing Composite Mode Error Cells

For the following HERC rules

MULTILAB OUTPUT SHORTS 52 1
SAMELAB  OUTPUT OPENS  41 2

the composite error cells for HERC are organized as follows.

The results of ELCOUNT and PATHCHK on the Hcell plane are passed to the pins of the Hcells. Any composite node connecting to those Hcell pins combines the pin information with the composite node.

Viewing the SHORTBOX Cell

The MULTILAB error output shows the composite geometries that represent the shortest path between two texted points where a short occurred. When you include a MULTILAB check in your HERC rules file, Dracula creates a cell called SHORTBOX. The SHORTBOX cell contains the cell bounding boxes through which the composite node passed. Overlay this cell on with your MULTILAB error cell to locate errors, as shown in the right side of the following figure.

Listing HERC Text Output Files

HERC text output includes the following files:

where printfile is the name you specify with the PRINTFILE function in the Description block of your rules file.

For information about HERC output, see “HERC Commands” in the “Checking Electrical Rules (ERC)” chapter of the Dracula Reference.

Running a Hierarchical Network Comparison

To completely verify the connectivity of a circuit, you use hierarchical Dracula in the same way you use flat Dracula. You verify your cells prior to verifying the top-level design.

For more information about HLVS, see “Hierarchical LVS” in the “Comparing Layouts and Schematics (LVS)” chapter of the Dracula Reference.

Writing Hierarchical Network Comparison Rules

The rules file you use for an HLVS run is the same as a rules file for a flat run, with the addition of several hierarchy-related functions. The following table lists the Dracula hierarchical functions that you might want to include in your rules file for an HLVS run. For complete documentation about these functions, see the Dracula Reference.

You cannot form devices by overlapping two Hcells. You can form elements in the Hcells or on the composite plane, but not between a combination of the two. The BASE-LAYER function is the only exception to this rule

.

Hierarchical Functions for HLVS
Function Description Rules file block

CELL-CHILD-TEXT

Cell mode only. For a description of this function, see Using Cell Mode in Chapter 4.

*DESCRIPTION

CELLBOX-LAYER

Creates cell boundaries for each Hcell. See the section about Using Cell Boundaries.

CHECK-MODE

Set to CELL or COMPOSITE.

GEN-TEXT-FILE

Instructs Dracula to automatically text Hcells and place the text in a HEDTEXT file. See “Using GEN-TEXT To Hcell Text”.

GEN-TEXT-FLTNODE

YES assigns text to feedthroughs and floating nodes. NO disables this option.

GEN-TEXT-FRAME

Generates a frame inside Hcell boundaries for automatic texting.

GEN-TEXT-WIRE

YES automatically generates internal-wire and must-join wire types. NO disables this option.

*DESCRIPTION

HCELL

Specifies which cells are Hcells. See “Altering the Hcell Selection Criteria”.

HCELL-COLUMN-1

SVS only. Specifies whether the first column in the HCELL-FILE lists layout or schematic cells.

HCELL-FILE

Specifies a file containing a set of HCELL statements. See Using a Cross-Reference File for Hcell Names.

HCELL-HEIGHT-LIM

YES sets a limit of 1000 microns for the maximum Hcell height. NO specifies that there is no height limit.

HCELL-MAX-SEGMENTS

Specifies the maximum number of line segments for a cell to be an Hcell candidate, to avoid selecting large cells.

HCELL-MAX-PLACEMENTS

Specifies the maximum number of placements for a cell to be an Hcell candidate, to avoid selecting small cells with a large number of placements.

*DESCRIPTION

BASE-LAYER

Specifies layers containing composite-level geometries that must be mapped into Hcells. See “Using Composite Plane Geometries in Hcells”.

*INPUT-LAYER

CELLBNDY

Specifies the digitized layer that contains rectilinear cell boundaries. See “Using Cell Boundaries”.

CTEXT

Specifies the input layer number of the Hcell text.

GEN-TEXT-LAYER

Cell mode only. See Specifying Texting Layers in Chapter 4 of this manual.

HEDTEXT

Specifies the name of the Hcell text file.

*OPERATION

For complete verification, you must run both cell mode and composite mode HLVS.

Each Hcell must have a corresponding .SUBCKT definition in a SPICE/CDL netlist. In composite mode, only the I/Os are required, not the transistors. All I/Os defined in the netlist must be texted on the Hcell with the same name. For more information about texting Hcells, see Texting for Cell Mode in Chapter 4 of this manual.

HLVS Prerequisites

See “Hierarchical LVS” in the “Comparing Layouts and Schematics (LVS)” chapter of the Dracula Reference for the following information:

You might want to create separate composite- and cell-mode rules files, because some functions might be different between the two files.

GEN-TEXT-FILE, HEDTEXT, and CTEXT/ATTACH can be used in both files, depending upon your application.

Functions for Cell Mode HLVS
Type Function Reference

mode

CHECK-MODE = CELL

None

Hcells

HCELL layout netlist

See Using a Cross-Reference File for Hcell Names.

texting

GEN-TEXT-FILE = filename

See “Using GEN-TEXT To Generate Hcell Text” in Chapter 4 of this manual.

layername = #
CTEXT = #
ATTACH = layer

Functions for Composite Mode HLVS
Type Function Reference

mode

CHECK-MODE = COMP

None

Hcells

HCELL layout netlist FRAME BY #

See “Excluding Hcell Geometries in HLVS”.

texting

HEDTEXT = filename

See “Using GEN-TEXT To Generate Hcell Text” in Chapter 4 of this manual.
GEN-TEXT-FILE, HEDTEXT, and CTEXT/ATTACH can be used in both files, depending upon your application.

Excluding Hcell Geometries in HLVS

When you use the FRAME BY option with the HCELL function for composite-mode HLVS, only the data falling within the distance you specify from the Hcell bounding box is processed.

If you are in an intermediate verification stage and need quick results, you can use FRAME BY after you run cell mode HLVS. Because Dracula does not process the entire cell, FRAME BY reduces the amount of data processed in composite mode.

For example, if you include this function in your rules file

HCELL INV INV1 FRAME BY 5

only the internal cell data falling within 5 microns of the Hcell bounding box is processed, as shown.

Do not use FRAME BY in the final verification stages because this function excludes portions of your design, masking potential problems.

Using Cell Boundaries

For each Hcell, Dracula creates a rectangular cell bounding box that surrounds all geometries in the Hcell. These boxes are put in a cell called 0CELLBOX that you can overlay on your output cells. You can specify the layer number for the geometries in this cell with the CELLBOX-LAYER function in the Description block.

The following example shows a nonrectangular Hcell and the bounding box Dracula generates for it.

When you use the HCELL FRAME BY option or the GEN-TEXT-FRAME function for composite-mode HLVS, only data falling within the distance you specify from the Hcell bounding box is processed. For this example, if the Dracula-generated bounding box is used, two pins are lost, and the cell does not match the .SUBCKT I/Os in the netlist.

Dracula uses the CELLBNDY layer for the boundaries you create, and Dracula-generated bounding boxes for the Hcells for which you don’t supply boundaries.

You can also use the CELLBNDY layer with BASE-LAYER for gate arrays. For example, if your cells consist only of metal but diffusion and poly are composite data, devices are electrically inside the cell but built from polygons outside the Dracula bounding box.

Marking Feedthroughs on the Layout

You might have interconnects (feedthroughs) on your layout that run through an Hcell without making connections to any devices in the Hcell. These feedthroughs do not have a counterpart in the netlist Hcells because they are part of the composite plane interconnect, not the Hcell. You must identify feedthroughs in your Hcell layout by giving them a text label of this form:

FTHRU#

where # is a number of your choice.

In cell mode, HVLS ignores feedthroughs. In composite mode, HLVS connects them to nodes.

See “Using GEN-TEXT To Generate Hcell Text” and “GEN-TEXT Commands” in the “Comparing Layouts and Schematics (LVS)” chapter of the Dracula Reference.

Using a Cross-Reference File for Hcell Names

For cell and composite mode HLVS and HLPE, Dracula requires layout cell names to match equivalent schematic .SUBCKT names. If you were not aware of this requirement when you created your schematics and layout, you can correct problems with cell names using an Hcell file (HCELL-FILE = fileName) to match names of Hcells between the schematic and layout.

Here are the contents of a sample HCELL-FILE that matches layout and schematic cell names:

NOR2  no2
NAND2 na2
REG   chip

Preparing Your Netlist

If HLVS is unable to complete the initial correspondence between layout Hcells and schematic Hcells, you might have to edit your netlist. Statements that you might have to include in your netlist are

See the sections that follow for examples of how to use these statements.

For details, see “Compiling Network Descriptions (LOGLVS)” in the Dracula Reference.

Using a Netlist with Node Numbers

If your netlist is in true SPICE format, it uses node numbers rather than node names. To use this netlist in an HLVS run, you must include a local *.EQUIV statement for each Hcell to cross-reference the node numbers in the netlist to node names on the layout.

Here is an example:

.SUBCKT INV 3 17
*.EQUIV OUT=3 IN=17 VSS=0 VDD=99
M1 3 17 99 99 PMOS
M2 3 17  0  0 NMOS
.ENDS
In composite mode, all Hcells must have corresponding .SUBCKT definitions in SPICE/CDL, but they need to define only I/Os, not transistors.

Adding Global Signals

You might have global Hcell I/O signals that are not defined as I/O signals in the .SUBCKT definition, but are required to match the layout Hcell with the netlist Hcell. To define these I/O signals in your SPICE/CDL netlist, use the *.PIN statement.

Any node defined by the *.PIN statement must be previously defined as a *.GLOBAL node. Here is an example:

*.GLOBAL VDD VSS
*.PIN VDD VSS
.SUBCKT INV OUT IN
M1 OUT IN VDD VDD PMOS
M2 OUT IN VSS VSS NMOS
.ENDS

If you put a *.PIN statement outside a .SUBCKT definition, the global signals you define apply to all Hcell .SUBCKTs. If you put the *.PIN within a .SUBCKT definition, the I/Os apply to only that subcircuit.

Removing Global Signals from Selected Subcircuits

For selected subcircuits, you can use the *.NOPIN statement to remove global I/Os that you previously defined in a *.PIN statement. Here is an example where the CXFR transfer gate does not need a connection to VDD on the layout to match the netlist.

*.GLOBAL VDD VSS
*.PIN VDD VSS
.SUBCKT INV OUT IN
M1 OUT IN VDD VDD PMOS
M2 OUT IN VSS VSS NMOS
.ENDS
.SUBCKT CXFR A B C
*.NOPIN VDD
M1 A B C VSS NMOS
.ENDS

Compiling Your Netlist

To compile your netlist, you must run LOGLVS just as you do for flat Dracula.

For details and examples, see “Using Hierarchical LOGLVS” in the “Compiling Network Descriptions (LOGLVS)” chapter of the Dracula Reference.

Running Hierarchical Parameter Extractions

You use hierarchical Dracula in the same way you use flat Dracula when you extract parasitics from your circuit. To avoid duplicate processing, you extract parasitics from your cells prior to extracting the top-level design. Then, when you process the top-level design, cells are treated as blocks with pin names only.

For more information about how to run HLPE and HPRE, see these sections in the Dracula Reference.

About Hierarchical Parameter Extraction

Initially, you might want to verify that your Dracula HLPE/HPRE rules file works on a flat database. You can then use it for hierarchical extraction, to take advantage of the smaller hierarchical netlist.

Extracting Capacitance Hierarchically

Hierarchical Dracula can extract capacitance between internal cell nodes in the same cell with the same placement during the cell mode run. However, nodes in one cell placement cannot be referenced from another cell. So although Dracula can extract internal capacitors, there is no way to describe them in a hierarchical netlist without making every node in every cell a pin on the netlist.

This problem appears in the following cases:

Flattening Layers To Extract Capacitance

You extract capacitors between internal cell nodes and parent cell nodes by flattening layers. To flatten layers, you flatten all nodes in the cell to the parent cell and assign all those nodes to ground. Here is an excerpt from a rules file that uses the flattening method:

;
; <functions omitted>
;
; Create flattened layer
FLATTEN METAL2 FLA2
;
; Set up nodal information for the flattened layer
LINK FLA2 TO VSS
;
; Create capacitance recognition layer
NOT METAL1 METAL2 MT1N2
AND MT1N2 FLA2 CA1F2 ; recognition layer for capacitance 
                     ; between metal1 and fla2
;
; Extract parasitic capacitance
PARASITIC CAP[A] CA1F2 METAL1 FLA2 ; capacitors between
ATTRIBUTE CAP[A] 1 1               ; metal1 and fla2
;
; <functions omitted>
;

Do not build a recognition layer between a flattened layer and BULK if BULK is at the same potential, that is, the flattened layer and BULK have the same signal name.

The parent cell does not have to be the immediate parent. The parent cell and the cell containing the internal node can have several levels of hierarchy between them. You can use the flattening method for both cross-coupled and lump sum formats.

If you list capacitors in cross-coupled format, the capacitors between an internal cell node and the parent cell are listed in lump sum format, which is the only way these capacitors can be listed in a netlist.

When you flatten layers, Dracula finds capacitors between nodes in both the child cell and the parent cell.

You can also use the EXPLODE function to extract capacitors between internal cell nodes and parent cell nodes.

Extracting Resistance Hierarchically

Unlike capacitors, resistors that have one node in an internal cell and one node in the parent cell are not really a problem. When you run extraction on

When you run HPRE to extract resistors hierarchically, each I/O point becomes a different subnode. If you have a signal that leaves the cell at more than one
I/O point, check your output file for problems.

Writing Parameter Extraction Rules

The rules file you use for an HLPE or HPRE run is the same as the rules file for a flat run, with the addition of several hierarchy-related functions. The table in the “Running a Hierarchical Network Comparison” section lists the Dracula hierarchical functions that you might want to include in your rules file for an HLPE or HPRE run. For complete documentation about these functions, see the Dracula Reference.

You cannot form devices by overlapping two Hcells. You can form elements in the Hcells or on the composite plane, but not between a combination of the two. The BASE-LAYER function is the only exception to this rule.

For a complete verification, you must run both cell mode and composite mode HLPE or HPRE.

Using a Cross-Reference File for Hcell Names

For cell and composite mode HLPE, Dracula requires that layout cell names and their equivalent schematic .SUBCKT names must be the same. If you were not aware of this requirement when you created your schematics and layout, you can correct problems with cell names by using an Hcell file (HCELL-FILE = fileName) to match the names of the Hcells in the schematic and layout.

For example, here are the contents of an HCELL-FILE that matches layout and schematic cell names:

NOR2  no2
NAND2 na2
REG   chip

Using HLPE To Extract a Complete Netlist

To use HLPE to extract a netlist of your complete circuit (Hcell plane and composite plane) in hierarchical Dracula, do the following.

  1. Run a cell-mode HLPE.
    The transistor-level netlist contains .SUBCKT definitions for each Hcell listed in your HCELL-FILE. You specify the name of the netlist with the OUTPUT option of the LPESELECT function. 
    LPESELECT[S] CAP GT 0.0 OUTPUT SPICE
    The cell-mode netlist has a .CEL extension.
  2. Run a composite-mode HLPE, using the same OUTPUT file name with the LPESELECT function that you used for the cell-mode run.
    Dracula extracts a netlist with elements and parasitics from the composite plane and calls to the .SUBCKT definitions created in cell mode. This netlist is appended to the netlist extracted from the cell-mode run, making a complete two-level hierarchical netlist.
    The composite-mode netlist has a .DAT extension.
    Dracula does not extract parasitics from composite-to-Hcell or Hcell-to-Hcell overlaps.

Making Hierarchical Dracula Run Faster

Hierarchical Dracula is, in general, faster than flat Dracula on a hierarchical design, because it takes advantage of the repetitive data structures of that design. In this section, you will learn how to improve hierarchical Dracula performance by

For more help with improving hierarchical Dracula’s performance, you can also see “Improving Preformance”.

Maximizing Operations

To process a design, hierarchical Dracula must first set up the database by selecting Hcells, creating Hcell environments, and doing other hierarchical bookkeeping that flat Dracula does not do.

To make the best use of this setup time, include as many design rules as you can in the Operation section of your rules file. Because the setup time is the same whether you run a few rules or many, it is most efficient to run many rules at once.

When you are running hierarchical Dracula, you can improve processing time by removing checks that require nodal information and checks with large spacing values. Run these checks separately in flat mode.

Minimizing Redundant Checking

You can minimize redundant checking by avoiding Hcell overlaps. Dracula sets up Hcells by creating an environment area around them that is as wide as the largest spacing check on hierarchical layers in the Operations block. When Hcells overlap, their environments also overlap. Because Dracula checks the environment of each Hcell, Dracula checks certain overlapping environment areas many times.

You can solve the problem of overlapping Hcells as follows:

If your design contains a large number of overlapping cells, a flat run might take less time than a hierarchical run.

Altering the Hcell Selection Criteria

If you use Dracula’s automatic Hcell selection and your job does not perform well, you may want to choose Hcells yourself. See “Selecting Hcells Manually To Improve Performance”.

You can alter the Hcell selection criteria with these functions:


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