WSP/SP Support for Pin Optimization
Pin Optimizer has been enhanced to support width-aware and constraint (CST)-aware optimization of pins.
Pin Optimizer recognizes the Width Spacing Snap Pattern grid defined using the widthSpacingSnapPatternDef rule in the technology file. The widthSpacingSnapPatternDef definitions are available in the technology database as well as in the design. Pin Optimizer recognizes both global and local widthSpacingSnapPatternDef definitions.
The pin optimization and snapping behavior for connected pins is different from that of unconnected pins. In both cases, the pin width is determined and compared with the WSP/SP track width. The pin width is determined by comparing the width of the pin with the minWidth constraint based on the CST lookup. The larger value is considered.
Pin Optimizer honors the pin layer/side constraints while placing the pins on the WSP/SP tracks. The pin layer/side constraints are honored only when WSP/SP tracks are available on the specified side. For example, consider a technology in which Metal2 WSP tracks are available in the horizontal direction. The pin layer/side constraint on this layer is honored only when the pins are assigned to the Left or Right side. The constraint is not honored when pins are assigned to the Top or Bottom side because there are no WSP/SP tracks on this side.
Related Topics
Setting Pin Layer and Side Constraints for Pin Optimization
Connected Pins
Connected pins are snapped to tracks with widths greater than or equal to the pin width, while ensuring the minimum net length. While snapping, pins are resized to square-shaped pins with dimensions that match the WSP/SP track width. Pins are centered along the WSP/SP tracks on the snapping layer that is identified in the WSP/SP definition.
Set the retainLongPin environment variable to t to retain the dimension of long, rectangular pins while snapping to WSP/SP tracks. The default value is nil, in which case pins are resized to square-shaped pins to match the WSP/SP track width.
The following examples depict the snapping behavior in various scenarios when retainLongPin is set to t.
Example 1: A long pin is snapped to a track of the same width. There is no change in the pin dimensions.
Example 2: A long pin is snapped to a wider track. The pin width is adjusted as per the track width, but the orthogonal pin dimension remains the same.
Example 3: A long pin is snapped to a narrower track. The pin width is adjusted as per the track width, but the orthogonal pin dimension remains the same.
Example 4: A long pin is snapped to an orthogonal edge, typically due to a layer change. The shorter pin dimension is used to find a suitable width-aware track. The shorter pin edge is snapped to the track, and so the orthogonal dimension is maintained.
Example 5: A square pin is snapped to a wider width track. A square pin is created that matches the width of the snapped track.
pin_1 has the side Left edge constraint, then only the tracks on the left side are considered.
In the above figure, for the yellow pins, only those tracks with width >=0.6 are considered for placement; whereas for the red pins, all the tracks are considered.
During pin optimization, the yellow pin is snapped to a track such that the minimum net length is achieved.
The red pin has multiple tracks available. Such pins are snapped to ensure minimal net length, and not minimal pin resize. Further, the pins are placed on the left to ensure minimum net length. While snapping, the pins are resized to square-shaped pins with dimensions that match the WSP/SP track width.
If no matching WSP/SP tracks are found, then the pins are snapped to tracks such that the minimum net length is achieved.
To match a pin’s layer and size to the connected fixed pin’s layer and size, use the options in the Match Fixed Pins Layer/Size section on the Pin Optimization tab of the Pin Placement form.
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Unconnected Pins
Unconnected pins are snapped to WSP/SP tracks with widths equal to or greater than the pin width. While snapping, the pins are resized to square-shaped pins with dimensions that match the WSP/SP track width. The following figures depict the snapping behavior of a pin with an original size 0.03.
In Situation 1, there are two available tracks of widths 0.08 and 0.04. So, the pin is snapped to the WSP/SP track with width 0.04, and resized accordingly.
In Situation 2, there are two available tracks of widths 0.08 and 0.02. This time, the pin is snapped to the WSP/SP track with width 0.08, and resized accordingly.
Blockage Support
Pin Optimizer supports routing blockages. Therefore, during pin optimization, a pin is not placed on a WSP track if the placement would lead to an overlap between the pin and blockages on the pin’s layer.
Pin Snapping for Overlapping Regions
In certain designs, there could be an overlap between two WSP regions that have the same snapping layer. The following types of overlaps are possible:
- Partial, between two regions
- Exact, between two regions of the same size
- Complete enclosure of a smaller region within another larger region
Pin Optimizer follows certain rules that define the pin snapping behavior for such overlapping regions.
Support for the allowedWireTypes Constraint
Pin Optimizer has been enhanced to support the allowedWireTypes constraint. When this constraint is set on a net, pins on that net are placed on tracks with allowed wire types. Pin Optimizer matches the allowedWireTypes constraint specified on the nets with the track wiretype value. If multiple matches are found, then the tack with the minimum net length is chosen for placement.
Pin Optimizer achieves the minimum net length while honoring the constraints and the priority order mentioned below:
Related Topics
Support for Rectangular and Square Pins and Blockages
Support for Pin Group Guides
If a design with WSP patterns has a pin group guide defined on its PR boundary, then the pins in the pin group guide are snapped to nearest WSP/SP track within the guide. However, if a pin group guide only intercepts a WSP/SP track, then the pins cannot be placed on the intercepting track, as shown below:
Related Topics
Cross-Selection of Pins
Any pin that you select in the pin table, as shown below, also gets selected in the navigator assistant and the layout canvas, or vice versa.
If you select a top-level pin in the layout canvas and the Pin Planner tab has the Top Level Pins edit mode selected, the pin table displays the selected pin as highlighted. However, if the edit mode selected in the Pin Planner tab is Level-1 Pins, the form automatically switches to the Top Level Pins mode to show the cross-selection. The automatic mode switching works as long as the selected layout pins belong to the same level—top or level-1. If you select a mix of top-level and level-1 pins in the layout canvas, the Pin Planner tab continues to be in the current selected mode and displays only those pins as highlighted in the pin table that belong to the current edit mode.
The table below summarizes how the Pin Planner tab handles the cross-selection depending on the layout pins selected. Let us assume here that the default edit mode selected is Top Level Pins :
You can also add to your selection set and nullify your selection in the pin table.
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To add to your selection set in the pin table, incrementally select the pins using the
CtrlorShiftkey, as appropriate. -
To nullify your existing selection:
- In the pin table, click any pin. This nullifies the previous selection and shows only the clicked pin as selected.
- In the layout canvas, click anywhere. This nullifies the previous selection and shows no pins as selected. However, if you click a pin in the layout canvas, the previous selection is nullified and the clicked pin appears as selected.
Planning Placement of Top-Level and Level-1 Pins
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