Model Equations

Effective Oxide Thickness, Channel Length and Channel Width

Gate Dielectric Model

The finite chargelayer thickness cannot be ignored when the gate oxide thickness is vigorously scaled down. There are two ways in BSIM4 for modeling this effect in both IV and CV, which can be selected by mtrlmod. When mtrlmod=0 (for SiO2 gate) , the input parameters includes toxe, toxp and dtox. When mtrlmod=1 (for high-k dielectric gate), the input parameters includes eot, weffeot, leffeot, tempeot and vddeot. toxe is equal to eot, and toxp could be calculated by the input parameters.

Poly-Silicon Gate Depletion

Charge distribution in a MOSFET with the poly gate depletion effect is shown in the following figure. The device is in the strong inversion region.

The effective gate voltage Vgse is

For mtrlmod=0

(-1)

For mtrlmod =1(the non-silicon channel or high -k gate insulator

(-2)

Effective Channel Length and Width

(-3)

(-4)

(-5)

(-6)

(-7)

(-8)

WINT represents the traditional manner from which "delta W" is extracted (from the intercept of straight lines on a 1/R_ds~W_drawn plot). The parameters DWG and DWB are used to account for the contribution of both gate and substrate bias effects. For dL, LINT represents the traditional manner from which "delta L" is extracted from the intercept of lines on a R_ds~L_drawn plot.

The remaining terms in dW and dL are provided for your convenience. They are meant to allow you to model each parameter as a function of W_drawn, L_drawn, and their product term. By default, the above geometrical dependencies for dW and dL are turned off.

MOSFET capacitances can be divided into intrinsic and extrinsic components. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction, which is defined by the effective length (L_active) and width (W_active) when the gate to source/drain regions are under flat-band condition. L_active and W_active are defined as

(-9)

(-10)

(-11)

(-12)

The meanings of DWC and DLC are different from those of WINT and LINT in the I-V model. Unlike the case of I-V, these dimensions are bias-dependent. The parameter δL_eff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate patterning, etching, and oxidation) on one side.

The effective channel length Leff for the I-V model does not necessarily carry a physical meaning. It is just a parameter used in the I-V formulation. This Leff is therefore sensitive to the I-V equations and also to the conduction characteristics of the LDD region relative to the channel region. A device with a large Leff and a small parasitic resistance can have a similar current drive as another with a smaller Leff but larger Rds.

The Lactive parameter extracted from capacitance is a closer representation of the metallurgical junction length (physical length). Due to the graded source/drain junction profile, the source to drain length can have a strong bias dependence. Lactive is measured at flat-band voltage between gate to source/drain. If DWC, DLC and the length/width dependence parameters (LLC, LWC, LWLC, WLC, WWC and WWLC) are not specified in technology files, BSIM4 assumes that the DC bias-independent Leff and Weff will be used for the capacitance models, and DWC, DLC, LLC, LWC, LWLC, WLC, WWC, and WWLC will be set to the values of their DC counterparts.

BSIM4 uses the effective source/drain diffusion width W_effcj for modeling parasitics, such as source/drain resistance, gate electrode resistance, and gate induced drain leakage (GIDL) current. W_effcj is defined as:

(-13)

Threshold Voltage Model

Considering non-uniform doping, short-channel effect, DIBL effect, and narrow-width effect, the complete V_th model is:

(-14)

Channel Charge and Subthreshold Swing Models

A unified expression for channel charge from subthreshold to strong inversion regions is

(-15)

In the above equation, Vgsteff (the effective Vgst(Vgse-Vth)) used to describe the channel charge densities from subthreshold to strong inversion is modeled by:

The drain current equation in the subthreshold region can be expressed as:

(-16)

(-17)

Gate Direct Tunneling Current Model

In BSIM4, the gate tunneling current components include the tunneling current between gate and substrate (I_gb), and the current between gate and channel (I_gc), which is partitioned between the source and drain terminals by Igc = Igcs + Igcd. The third component happens between gate and source/drain diffusion regions (Igs and Igd). Following figure shows the schematic gate tunneling current flows.

Igc, Igs, and Igd are turned on when igcmod = 1, 2; Igb is turned on when igbmod = 1; no gate tunneling currents are modeled when igcmod = 0. Vt (= kT/q) is replaced by Vtnom(=kTnom/q) when tempmod = 2. The gate tunneling current components are expressed as following:

(-18)

(-19)

(-20)

(-21)

(-22)

(-23)

(-24)

Drain Current Model

Bulk Charge Effect

The bulk charge effect caused by non-zero Vds is modeled as

(-25)

(-26)

Mobility Model

Several mobility models are provided in BSIM4. For mtrlmod = 0, mobmod = 0 and 1 models  are from BSIM3v3.2.2, mobmod = 2 is a universal mobility model, which is more accurate and suitable. For mtrlmod = 1, a new expression of the vertical field in channel is adopted (introduced by BSIM4.6.1). The mobility model is modified as following:

mobmod=0

(-27)

mobmod=1

(-28)

mobmod=2

(-29)

mobmod=3 for high k/metal gate structure (introduced by BSIM4..2):

(-30)

BSIM4.80 introduces three new mobility models, mobmod=4, mobmod=5, and mobmod=6 as modified versions of mobmod=0, mobmod=1, and mobmod=2 respectively.

mobmod=4

(-31)

mobmod=5

(-32)

mobmod=6

(-33)

Bias-Dependant Source/Drain-Resistance Model

rdsMod=0 (Internal Rds (V))

(-34)

rdsMod=1 (External Rd(V) and Rs(V)

(-35)

(-36)

Saturation Voltage V_dsat

Intrinsic Case

(-37)

Extrinsic Case

(-38)

where

(-39)

(-40)

(-41)

(-42)

Drain Current

Considering only the channel current, the I-V curve can be divided into two parts: the linear region and the saturation region. In the linear region, carrier velocity is not saturated and the drain current has a strong dependence on the drain voltage. In the saturation region, several physical mechanisms affect the output resistance: channel length modulation (CLM), drain-induced barrier lowering (DIBL), and the substrate current induced body effect (SCBE). These mechanisms all affect the output resistance in the saturation range, but each of them dominates in a specific region. The channel current equation for both linear and saturation regions is:

(-43)

where NF is the number of device fingers, and Early voltage.

(-44)

The Early voltage at Vds = Vdsat is

(-45)

The Early voltage due to CLM effect is

(-46)

where

(-47)

The Early voltage due to DIBL effect is

(-48)

The Early voltage due to SCBE effect is

(-49)

The Early voltage due to Drain-Induced Threshold Shift (DITS) by pocket implant is

(-50)

Velocity Overshoot and Source End Velocity Limit Model

In the deep-submicron region, the velocity overshoot and source end velocity limit model should be used. The unified current expression with velocity saturation, velocity overshoot and source velocity limit is:

(-51)

where the current including the velocity overshoot effect is:

(-52)

Body Current Model

I_sub Model

When the electrical field near the drain is large (> 0.1MV/cm), some electrons coming from the source (in the case of NMOSFETs) will be energetic (hot) enough to cause impact ionization. This will generate electron-hole pairs when these energetic electrons collide with silicon atoms. The substrate current Isub thus created during impact ionization will increase exponentially with the drain voltage. A well known Isub model is:

(-53)

In addition to the junction diode current and gate-to-body tunneling current, the substrate terminal current consists of the substrate current due to impact ionization (Iii), and gate-induced drain leakage and source leakage currents (IGIDL and IGISL).

I_ii Model

(-54)

I_GIDL and I_GISL Model

mtrmod=0

(-55)

(-56)

(-57)

mtrmod=1

(-58)

(-59)

Capacitance Model

The following table displays the BSIM4 capacitance model options:

BSIM4 Capacitance Models	Matched capmod in BSIM3v3.2.2
capMod = 0 (simple and piecewise model)	Intrinsic capMod = 0 + overlap/fringing capMod=0
capMod = 1 (single equation model)	Intrinsic capMod = 2 + overlap/fringing capMod = 2
capMod = 2 (default; single-equation and charge-thickness model)	Intrinsic capMod = 3 + overlap/fringing capMod = 2

Intrinsic Capacitance Modeling

The relationship of terminal charges (Qg, Qb, Qs, and Qd) and the channel charge Qinv, accumulation charge Qacc and substrate depletion charge Qsub are:

(-60)

(-61)

(-62)

All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are a total of 16 components. For each component:

(-63)

where i and j denote the transistor terminals. Cij satisfies

(-64)

A new threshold voltage definition is introduced to improve the fitting in subthreshold region. Setting cvchargemod = 1 activates the new Vgsteff, CV calculation which is similar to the Vgsteff formulation in the I-V model. Setting cvchargemod = 0 is corresponding to long-channel charge model which assumes a constant mobility with no velocity saturation.

Intrinsic capacitance model equations

For capmod=0

Accumulation region

(-65)

(-66)

(-67)

Subthreshold region

(-68)

(-69)

(-70)

Strong inversion

(-71)

(-72)

(-73)

Linear Region

(-74)

(-75)

50/50 Charge Partition

(-76)

(-77)

40/60 Channel-Charge Partition

(-78)

(-79)

0/100 Partitioning

(-80)

(-81)

Saturation Region

(-82)

(-83)

50/50 Partitioning

(-84)

40/60 Partitioning

(-85)

(-86)

0/100 Channel-Charge Partition

(-87)

(-88)

For capmod=1

(-89)

(-90)

(-91)

(-92)

(-93)

(-94)

(-95)

(-96)

50/50 Charge Partition

(-97)

40/60 Channel-Charge Partition

(-98)

(-99)

0/100 Charge Partition

(-100)

(-101)

For capmod = 2

(-102)

(-103)

(-104)

(-105)

(-106)

(-107)

When updatelevel=1, a smooth function is applied when calculating (Vgsteff, cv- psidelta)_eff to improve convergence behavior of the model.

(-108)

(-109)

(-110)

(-111)

(-112)

50/50 Partitioning

(-113)

40/60 Partitioning

(-114)

(-115)

0/100 Partitioning

(-116)

(-117)

When updatelevel=0,

(-118)

When updatelevel=1, or version=4.5,

(-119)

Intrinsic Capacitances (with Body Bias and DIBL)

(-120)

(-121)

(-122)

(-123)

Overlap Capacitance Models

capmod=0, Bias-independent overlap capacitance model

(-124)

(-125)

(-126)

capmod 1 and 2, Bias dependent overlap capacitance model

(-127)

(-128)

(-129)

(-130)

(-131)

High Speed/RF Models

Charge-deficit Nonquasi-static (NQS) Model

BSIM4 uses two separate model selectors to turn on or off the charge-deficit NQS model in transient simulation (using trnqsMod) and AC simulation (using acnqsMod). The AC NQS model does not require the internal NQS charge node that is needed for the transient NQS model. The transient and AC NQS models are developed from the same fundamental physics: the channel/gate charge response to the external signal are relaxation-time dependent and the transcapacitances and transconductances (such as Gm) for AC analysis can therefore be expressed as functions for .

MOSGFET channel region is analogous to a bias-dependent RC distributed transmission line as shown section "a" of the figure below. In the Quasi-Static (QS) approach, the gate capacitor node is lumped with the external source and drain nodes as shown in section "b" of the figure below. This ignores the finite time for the channel charge to build-up. One way to capture the NQS effect is to represent the channel with n transistors in series as shown in section "c" of the figure below, but it comes at the expense of simulation time. The BSIM4 charge-deficit NQS model uses Elmore equivalent circuit to model channel charge build-up as shown in section "d" of the figure below.

The Transient Model

The transient charge-deficit NQS model can be turned on by setting trnqsMod = 1 and off by setting trnqsMod = 0.

The figure below shows the RC subcircuit of charge deficit NQS model for transient simulation. An internal node, Q_def(t), is created to keep track of the amount of deficit/surplus channel charge necessary to reach equilibrium. The resistance R is determined from the RC time constant . The current source i_cheq(t) represents the equilibrium channel charging effect. The capacitor C is the value of C_fact (with a typical value of 1 x 10^-9 Farad) to improve simulation accuracy. Qdef now becomes:

(-132)

Considering both the transport and charging component, the total current related to the terminals D, G, and S can be written as:

(-133)

Based on the relaxation time approach, the terminal charge and corresponding charging current are modeled by

(-134)

and

(-135)

(-136)

where D,G,Sxpart are charge deficit NQS channel charge partitioning numbers for terminals D, G, and S; Dxpart + Sxpart = 1 and Gxpart = -1.

The transit time is equal to the product of Rii and W_effL_effC_oxe, where Rii is the intrinsic-input resistance given by

(-137)

where C_oxeff is the effective gate dielectric capacitance calculated from the DC model.

The AC Mode

The small-signal AC charge-deficit NQS model can be turned on by setting acnqsMod = 1 and off by setting acnqsMod = 0.

For small signals in the frequency domain, Qch(t) can be transformed into:

(-138)

where is the angular frequency. It can be shown that the transcapacitances Cgi, Csi, and Cdi (i stands for any of the G, D, S, and B terminals of the device) and the channel transconductances G_m, G_ds, and G_mbs all become complex quantities. For example, now G_m has the form of:

(-139)

and

(-140)

The quantities above with sub "0" are known from OP (Operating Point) analysis.

Gate Electrode and Intrinsic-Input Resistance (IIR) Model

BSIM4 provides four options for modeling gate electrode resistance (bias-independent) and intrinsic-input resistance (IIR, bias-dependent). The IIR model considers the relaxation-time effect due to the distributive RC nature of the channel region, and therefore describes the first-order non-quasi-static effect. Thus, the IIR model should not be used together with the charge-deficit NQS model. The model selector rgateMod is used to choose different options.

rgateMod = 0 (zero-resistance)

In this case, no gate resistance is generated.

rgateMod = 1 (constant-resistance)

In this case, only the electrode gate resistance (bias-dependent) is generated by adding an internal gate node. Rgeltd is given by

(-141)

rgateMod = 2 (IIR model with variable resistance)

In this case, the gate resistance is the sum of the electrode gate resistance and the intrinsic-input resistance Rii. An internal gate node will be generated. trnqsMod = 0 (default) and acnqsMod = 0 (default) should be selected for this case.

rgateMod = 3 (IIR model with two nodes)

In this case, the gate electrode resistance given is in series with the intrinsic-input resistance Rii through two internal gate nodes, so that the overlap capacitance current will not pass through the intrinsic-input resistance. trnqsMod = 0 (default) and acnqsMod = 0 (default) should be selected for this case.

Substrate Resistance Network

For CMOS RF circuit simulation, it is essential to consider the high frequency coupling through the substrate. BSIM4 offers a flexible built-in substrate resistance network. This network is constructed so that little simulation efficiency penalty will result.

Model Selector and Topology

The model selector rbodyMod can be used to turn on or turn off the resistance network.

rbody = 0 (Off)

No substrate resistance network is generated at all.

rbody = 1 (On)

All five resistances in the substrate network as shown schematically below are present simultaneously.

A minimum conductance, GBMIN, is introduced in parallel with each resistance to prevent infinite resistance values which would otherwise cause poor convergence. In the following figure, GBMIN is merged into each resistance to simplify the representation of the model topology.

Noise Models

The following noise sources in MOSFETs are modeled in BSIM4 for noise analysis: flicker noise (also known as 1/f noise), channel thermal noise and induced gate noise and their correlation, thermal noise due to physical resistances such as the source/ drain, gate electrode, and substrate resistances, and shot noise due to the gate dielectric tunneling current.

Flicker Noise Models

BSIM4 provides two flicker noise models: simple model and unified physical model (default model). They can be selected by fnoimod. Both modes come from BSIM3v3, but there are many improvements in unified physical model.

fnoiMod = 0 (simple model)

The noise density is:

(-142)

The total flicker noise density is:

(-143)

The noise density in the inversion region is:

(-144)

lintmoi is an offset to the length reduction parameter (lint) for flicker noise, which is introduced by BSIM4.4.

The noise density in the subthreshold region is:

(-145)

Channel Thermal Noise

BSIM4 provides two channel thermal noise models: charge-based model (default model) and the holistic model. They can be selected by tnoimod. The schematic for BSIM4 channel thermal noise modeling is shown as following:

tnoiMod = 0 (charge-based)

Charge-based model is similar to that used in BSIM3v3.2. The noise current is given by:

(-146)

where

(-147)

tnoiMod = 1 (holistic)

In this thermal noise model, all the short-channel effects and velocity saturation effect incorporated in the IV model are automatically included, hence the name “holistic thermal noise model”. In addition, the amplification of the channel thermal noise through G_m and G_mbs as well as the induced-gate noise with partial correlation to the channel thermal noise are all captured in the new “noise partition” model.

The noise voltage source partitioned to the source side is given by

(-148)

The noise current source put in the channel region with gate and body amplification is given by:

(-149)

where

(-150)

Asymmetric MOS Junction Diode Models

Junction Diode IV Model

In BSIM4, there are three junction diode IV models. When the IV model selector dioMod is set to 0 ("resistance free"), the diode IV is modeled as resistance-free with or without breakdown depending on the parameter values of XJBVS or XJBVD. When dioMod is set to 1 ("breakdown-free"), the diode is modeled in the same way as in BSIM3v3 with current-limiting feature in the forward-bias region through the limiting current parameters IJTHSFWD or IJTHDFWD; diode breakdown is not modeled for dioMod = 1 and XJBVS, XJBVD, BVS, and BVD parameters all have no effect. When dioMod is set to 2 ("resistance-and-breakdown"), BSIM4 models the diode breakdown with current limiting in both forward and reverse operations. In general, setting dioMod to 1 produces fast convergence.

Source/Body Junction Diode

dioMod - 0 (resistance-free)

(-151)

where I_sbs is the total saturation current consisting of the components through the gate-edge (J_sswgs) and isolation-edge sidewalls (J_ssws) and the bottom junction (J_ss).

(-152)

where

(-153)

In the above equation, if XJBVS = 0, no breakdown will be modeled. If XJBVS < 0.0, it is reset to 1.0.

dioMod = 1 (breakdown-free)

The exponential IV term is linearized at the limiting current IJTHSFWD in the forward-bias model only.

(-154)

dioMod = 2 (resistance-and-breakdown)

Diode breakdown is always modeled. The exponential term is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSREV in the reverse-bias mode.

(-155)

for dioMod = 2, if XJBVS <= 0.0, it is reset to 1.0.

Drain/Body Junction Diode

The drain-side diode has the same system of equations as those for the source-side diode, but with a separate set of model parameters.

dioMod = 0 (resistance-free)

(-156)

where I_sbd is the total saturation current consisting of the components through the gate-edge (J_sswgd) and isolation-edge sidewalls (J_sswd) and the bottom junction (J_sd),

(-157)

where

(-158)

In the above equation, when XJBVD = 0, no breakdown is modeled. If XJBVD < 0.0, it is reset to 1.0.

dioMod = 1 (breakdown-free)

No breakdown is modeled. The exponential IV term is linearized at the limiting current IJTHSFWD in the forward-bias model only.

(-159)

dioMod = 2 (resistance-and-breakdown)

Diode breakdown is always modeled. The exponential term is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSFWD in the reverse-bias mode.

(-160)

For dioMod = 2, if XJBVD <= 0.0, it is reset to 1.0.

Total Junction Source/Drain Diode Including Tunneling

Total diode current including the carrier recombination and trap-assisted tunneling current in the space-charge region is modeled by:

(-161)

(-162)

Junction Diode CV Model

Source and drain junction capacitances consist of three components: the bottom junction capacitance, sidewall junction capacitance along the isolation edge, and sidewall junction capacitance along the gate edge. An analogous set of equations are used for both sides but each side has a separate set of model parameters.

Source/Body Junction Diode

(-163)

where C_jbs is the unit-area bottom S/B junction capacitance, C_jbsws is the unit-length S/B junction sidewall capacitance along the isolation edge, and C_jbswgs is the unit-length S/B junction sidewall capacitance along the gate edge.

Cjbs

if V_bs< 0

(-164)

otherwise

(-165)

Cjbsws

if V_bs< 0

(-166)

otherwise

(-167)

Cjbsws

if V_bs< 0

(-168)

otherwise

(-169)

Drain/Body Junction Diode

(-170)

where C_jbd is the unit-area bottom D/B junction capacitance, C_jbswd is the unit-length D/B junction sidewall capacitance along the isolation edge, and C_jbswgd is the unit-length D/B junction sidewall capacitance along the gate edge.

C_jbd

if V_bd < 0

(-171)

otherwise

(-172)

C_jbdsw

f V_bd < 0

(-173)

otherwise

(-174)

C_jbdswg

f V_bd < 0

(-175)

otherwise

(-176)

Layout Dependent Parasitics Models

The following figure shows the geometry definition for various source/drain connections and source/drain/gate contacts. The layout parameters shown in this figure will be used to calculate resistances and source/drain perimeters and areas.

Effective Junction Perimeter and Area

The source-side case is illustrated below. The same approach is used for the drain side. The effective junction perimeter is calculated by:

If (PS is given)

if (perMod = 0)

Pseff = PS

else

(-177)

Else

Pseff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT, and MIN.

The effective junction area is calculated by:

If (AS is given)

A_seff = AS

Else

A_seff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG, DMCGT, and MIN.

In the above, P_seff and A_seff will be used to calculate junction diode IV and CV. P_seff does not include the gate-edge perimeter.

geoMod	End source	End drain	Note
0	isolated	isolated	NF=Odd
1	isolated	shared	NF=Odd, Even
2	shared	isolated	NF=Odd, Even
3	shared	shared	NF=Odd, Even
4	isolated	merged	NF=Odd
5	shared	merged	NF=Odd, Even
6	merged	isolated	NF=Odd
7	merged	shared	NF=Odd, Even
8	merged	merged	NF=Odd
9	sha/iso	shared	NF=Even
10	shared	sha/iso	NF=Even

Temperature Effects Models

Accurate modeling of the temperature effects on MOSFET characteristics is important to predict circuit behavior over a range of operating temperatures (T). The operating temperature might be different from the nominal temperature (TNOM) at which the BSIM4 model parameters are extracted.

Temperature Dependence of Threshold Voltage

The temperature dependence of V_th is modeled by:

(-178)

(-179)

(-180)

(-181)

Temperature Dependence of Mobility

(-182)

(-183)

(-184)

(-185)

Temperature Dependence of Saturation Velocity

(-186)

Temperature Dependence of LDD Resistance

rdsMod = 0 (internal source/drain LDD resistance)

(-187)

(-188)

rdsMod = 1 (external source/drain LDD resistance)

(-189)

(-190)

(-191)

(-192)

Temperature Dependence of Junction Diode IV

Source-side Diode

(-193)

where

(-194)

(-195)

(-196)

where

(-197)

(-198)

(-199)

Drain-side Diode

(-200)

(-201)

(-202)

Trap-assisted Tunneling and Recombination Current

(-203)

(-204)

(-205)

(-206)

(-207)

(-208)

Temperature Dependence of Junction Diode CV

Source-Side Diode

The temperature dependences of zero-bias unit-length/area junction capacitances on the source side are modeled by

(-209)

(-210)

(-211)

The temperature dependences of the built-in potentials on the source side are modeled by

(-212)

(-213)

(-214)

Stress Effects Models

BSIM4 considers the influence of stress on mobility, velocity saturation, threshold voltage, body effect, and DIBL effect. The following diagram displays the LOD instance geometry parameters SA and SB.

(-215)

(-216)

(-217)

(-218)

(-219)

(-220)

(-221)

(-222)

(-223)

(-224)

For irregular LOD device like above figure, more instance parameters (swi, sai and sbi) are needed. Then,

(-225)

(-226)

Well Proximity Effect Model

Deep buried layers can affect devices located near the mask edge. Some of the ions scattered out of the edge of the photoresist are implanted in the silicon surface near the mask edge, altering the threshold voltage of those devices. BSIM4 considers the influence of well proximity effect on threshold voltage, mobility, and body effect as following:

(-227)

(-228)

(-229)

TMIBSIM4 Model (tmibsim4)

The TSMC Model Interface (TMI) implements a modified version of the BSIM4 model, known as TMIBSIM4. You can activate the tmibsim4 model by specifying the tmiflag and tmipath parameters as follows:

.options tmiflag = 1

.option tmipath = TMI_shared-library_path

Related Topics

BSIM4 Level-14 Model (bsim4)

Effective Oxide Thickness, Channel Length and Channel Width

Threshold Voltage Model

Channel Charge and Subthreshold Swing Models

Gate Direct Tunneling Current Model

High Speed/RF Models

Noise Models

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