Poly-Si TFT Model (PSITFT)

Equivalent Circuit

Model Features

Unified DC Model includes all four regimes for channel lengths down to 4 um
- Leakage (thermionic emission)
- Sub-threshold (diffusion like model)
- Above threshold (c-Si like with m FET)
- Kink (impact ionization with feedback)
AC model accurately reproduces C_gs frequency dispersion
Automatic scaling of model parameters to accurately model a wide range of device geometries.
Above threshold
- Based on the crystalline MOSFET Model
- Field effect mobility becomes a funcion of gate bias
- Field effect mobility accounts for trap states
Sub-threshold
- Diffusion like model
Leakage Current
- Reverse bias drain current function of
  - Electric field near drain
  - Temperature
- Independent of channel length

Channel Width and Length

(-1)

(-2)

Drain and Source Parasitic Resistance

If ACM is not given,

(-3)

(-4)

ACM=0:

(-5)

(-6)

If ACM=1,

(-7)

(-8)

If ACM=2, 3,

(-9)

(-10)

Threshold Voltage

(-11)

Effective Mobility

(-12)

(-13)

where

(-14)

(-15)

(-16)

Unified Electron Sheet Charge Density Per Unit Area

(-17)

where

(-18)

(-19)

(-20)

(-21)

(-22)

where

(-23)

(-24)

(-25)

Channel Conductance

(-26)

(-27)

Saturation Voltage

(-28)

(-29)

(-30)

Channel Current

(-31)

(-32)

where

(-33)

If Isubmod=1

lambda=0

(-34)

(-35)

(-36)

(-37)

else

(-38)

Kink Effect Current

(-39)

Kink effect current is added to the drain current

Subthreshold Leakage Current

(-40)

(-41)

(-42)

(-43)

(-44)

(-45)

where FMIN=0.0001

(-46)

where

(-47)

(-48)

(-49)

(-50)

(-51)

(-52)

Parasitic Resistance Dependence

If intdsnod=0 , extrinsic characteristics are used.

(-53)

(-54)

(-55)

(-56)

Else, intrinsic characteristics are used.

(-57)

Gate-Drain/Source Resistance

(-58)

If rsx is not specified,

(-59)

If rdx is not specified

(-60)

Temperature Dependence

(-61)

(-62)

(-63)

Capacitance

When capmod=0,

(-64)

(-65)

(-66)

(-67)

(-68)

(-69)

(-70)

(-71)

When capmod=1

If ZEROC=1,

(-72)

(-73)

If `ZEROC=0,`

(-74)

if where

(-75)

if

(-76)

if

(-77)

When capmod=2

Charge conservation capacitance model

(-78)

(-79)

for Qs evaluation

(-80)

for Qd evaluation

(-81)

(-82)

(-83)

where

(-84)

(-85)

(-86)

(-87)

(-88)

(-89)

(-90)

(-91)

(-92)

(-93)

(-94)

(-95)

(-96)

(-97)

Overlap Capacitances

When `capmod=2`

(-98)

(-99)

For other values of `capmod`

If Acm parameter is given,

(-100)

(-101)

Else,

(-102)

(-103)

ACM Option

When ACM=0

(-104)

When ACM=1

(-105)

When ACM=2

(-106)

Scaling Effects

For scaling effects, see Scaling Factors (scale and scalem).

Component Statements

This device is supported within altergroups.

Sample Instance Statement

m4 (0 2 1 1) nch w=2u l=0.8u

Sample Model Statement

model nch psitft type=p

Instance Syntax

Name  d  g  s  [b]  [t] ModelName parameter=value ...

Instance Parameters

`w (m)`	Channel width.
`l (m)`	Channel length.
`nrd (m/m)`	Drain squares.
`nrs (m/m)`	Source squares.
`m=1`	Multiplicity factor (number of MOSFETs in parallel).
`region=triode`	Estimated operating region. Possible values are `off`, `triode`, `sat`, or `subth`.
`isnoisy=yes`	Should resistor generate noise. Possible values are `no` or `yes`.
`rth0 (`Ω`)`	Thermal resistance.
`cth0 (F)`	Thermal capacitance.
`nseg=1 m/m`	Number of segments for channel width partitioning.

Model Syntax

model modelName psitft parameter=value ...

Model Parameters

Device type parameters

type=n

Transistor type. Possible values are n or p.

Drain current model parameters

`vto=0 V`	Threshold voltage at zero body bias (BIN).
`lambda=0.048 1/V`	Channel length modulation parameter (BIN).
`tox=1e-7 m`	Gate oxide thickness.
`eta=7`	Subthreshold ideality factor (BIN).
`etai`	Alias to eta (BIN).
`asat=1`	Proportionality constant of Vsat (BIN).
`alphasat`	Alias to asat (BIN).
`delta=4`	Transition width parameter (BIN).
`mus=1 cm`²`/V s`	Subthreshold mobility (BIN).
`mu0=100 cm`²`/V s`	High field mobility (BIN).
`muo (cm`²`/V s)`	Alias to mu0 (BIN).
`mu1=0.004 cm`²`/V s`
	Low field mobility parameter (BIN).
`mmu=1.7`	Low field mobility exponent (BIN).
`m`	Alias to mmu (BIN).
`vfb=-0.1 V`	Flat band voltage (BIN).
`dd=1400e-10 m`	Vds field constant (BIN).
`dg=2000e-10 m`	Vds field constant (BIN).
`blk=0.001`	Leakage barrier lowering constant (BIN).
`clk=6 A/m`	Leakage scaling constant (BIN).
`i0=6.0 A/m`	Alias of clk (BIN).
`lkink=19e-6 m`	Kink effect constant (BIN).
`mkink=1.3`	Kink effect exponent (BIN).
`mk=1.3`	Alias of mkink (BIN).
`vkink=9.1 V`	Kink effect voltage (BIN).
`rs=0` Ω	Source resistance.
`rd=0` Ω	Drain resistance.
`rsx=0` Ω	Resistance in series with Cgs.
`rdx=0` Ω	Resistance in series with Cgd.
`at=3e-8 m/V`	DIBL parameter 1 (BIN).
`bt=1.9e-6 m/V`	DIBL parameter 2 (BIN).
`eb=0.68 eV`	Barrier height of diode (BIN).
`i00=150 A/m`	Reverse diode saturation current (BIN).
`ioo (A/m)`	Alias to i00 (BIN).
`etac0`	Capacitance subthreshold ideality factor at zero drain bias (BIN).
`etac00=0 1/V`	Capacitance subthreshold coefficient of drain bias (BIN).
`mc=3`	Capacitance knee shape parameter (BIN).
`dvto=0 V/C`	Temperature coefficient of VTO (BIN).
`dmu1=0 cm`²`/V s C`	Temperature coefficient of MU1 (BIN).
`dasat=0 1/C`	Temperature coefficient of ASAT (BIN).
`lasat=0 m`	Coefficient of length dependence of ASAT (BIN).
`von=0 V`	On-Voltage (BIN).
`cgso=0 F/m`	Gate-source overlap capacitance.
`cgdo=0 F/m`	Gate-drain overlap capacitance.
`vsigma=0.2 V`	Above threshold DIBL parameter (BIN).
`vsigmat=1.7 V`	Above threshold DIBL parameter (BIN).
`me=2.5`	Long channel saturation transition parameter (BIN).
`ms`	Alias to me (BIN).
`minme=2.0`	Minimum value of me parameter..
`meta=1`	ETA floating-body parameter (BIN).
`ls=35e-9 m`	Channel-length modulation coefficient 1 (BIN).
`vp=0.2 V`	Channel-length modulation coefficient 2 (BIN).
`isubmod=0`	Channel-length modulation model version.
`vmax=4e4 m/s`	Carrier saturation velocity (BIN).
`theta=0 1/V`	Mobility modulation coefficient (BIN).
`mss=1.5`	Vdse transition parameter (BIN).
`kss=0`	Fractions of the channel resistance coefficient.
`rsh=0` Ω`/sqr`	Source/drain diffusion sheet resistance.
`capmod=0`	Intrinsic charge model.
`zeroc=0`	Zero gate-source (gate-drain) capacitance flag (Cgs=Cgd=0 if zeroc=1 and capmod=1).
`intdsnod=0`	Intrinsic source and drain nodes usage flag.
`minr=0.1` Ω	Minimum source/drain resistance.
`version=2`	Version control parameter. The available versions are 1, 2.
`compatible=spectre`	Spice compatible flag. Possible values are `spectre`, `spice2`, `spice3`, `cdsspice`, `spiceplus`, `eldo`, or `sspice`.
`cdnver=1`	Cadence version flag, 0 without improvement, 1 with improvement.

Temperature effects parameters

`tnom (C)`	Parameter measurement temperature.
`trise=0 C`	Temperature rise from ambient.
`shmod=0`	Self-heating selector.
`cth0=0.0 F`	Self-heating thermal capacitance.
`rth0=0` Ω	Self-heating thermal resistance.
`wth0=0.0` μ`m`	Minimum width for thermal resistance calculation..
`tmax=500 C`	Maximum device temperature above ambient.

Operating region warning control parameters

alarm=none

Forbidden operating region. Possible values are none, off, triode, sat, subth, or rev.

Default device parameters

`w=3e-6 m`	Default channel width.
`l=3e-6 m`	Default channel length.
`nrd=1 m/m`	Default drain squares.
`nrs=1 m/m`	Default source squares.

Auto Model Selector parameters

`wmax=1 m`	Maximum channel width for which the model is valid.
`wmin=0 m`	Minimum channel width for which the model is valid.
`lmax=1 m`	Maximum channel length for which the model is valid.
`lmin=0 m`	Minimum channel length for which the model is valid.

Acm related parameters

`acm=0`	Area calculation method.
`xl=0.0 m`	Accounts for masking and etching effects.
`xw=0.0 m`	Accounts for masking and etching effects.
`ld (m)`	Lateral diffusion into channel from source and drain diffusion.
`wd=0.0 m`	Lateral diffusion into channel from bulk along width.
`lmlt=1.0`	Length diffusion layer shrink reduction factor.
`wmlt=1.0`	Width diffusion layer shrink reduction factor.
`ldif=0.0 m`	Length of heavily doped diffusion adjacent to gate (BIN).
`hdif=0.0 m`	Length of heavily doped diffusion from contact to lightly doped region.
`xj=1.5E-7 m`	Metallurgical junction depth.
`meto=0.0 m`	Fringing field factor for gate to source and gate to drain overlap capacitance.
`rdc=0.0` Ω	Additional drain resistance due to contact resistance.
`rsc=0.0` Ω	Additional source resistance due to contact resistance.

Capmod=2 related parameters

Special parameters of version 1

`dvt=0 V`	The difference between von and the threshold (BIN).
`vsi=2.0 V`	Above threshold DIBL parameter (BIN).
`vst=2.0 V`	Above threshold DIBL parameter (BIN).

Binning parameters

`binunit=1`	Bin parameter unit selector. 1 for microns and 2 for meters.
`binflag=0`	Binflag=2 is to open xl/xw binning.

Output Parameters

`rtheff (`Ω`)`	Effective thermal resistance.
`Ctheff (F)`	Effective thermal capacitance.
`weff (m)`	Effective channel width.
`leff (m)`	Effective channel length.
`rseff (m)`	Effective source resistance.
`rdeff (m)`	Effective drain resistance.

Operating-Point Parameters

`type=n`	Transistor type. Possible values are `n` or `p`.
`region=triode`	Estimated operating region. Possible values are `off`, `triode`, `sat`, or `subth`.
`reversed`	Reverse mode indicator. Possible values are `no` or `yes`.
`ids (A)`	Resistive drain-to-source current (alias = lx4).
`vgs (V)`	Gate-source voltage (alias = lx2).
`vds (V)`	Drain-source voltage (alias = lx3).
`vth (V)`	Threshold voltage (alias = lv9).
`vdsat (V)`	Drain-source saturation voltage (alias = lv10).
`gm (S)`	Common-source transconductance (alias = lx7).
`gds (S)`	Common-source output conductance (alias = lx8).
`tdev (C)`	Temperature rise from ambient.
`cgd (F)`	Gate-drain capacitance (alias = lx19).
`cgs (F)`	Gate-source capacitance (alias = lx20).
`cgg (F)`	Cgg (only for capmod=2).
`css (F)`	Intrinsic capacitance dQs_dVs (only for capmod=2).
`csd (F)`	Intrinsic capacitance dQs_dVd (only for capmod=2).
`cssx (F)`	Intrinsic capacitance dQs_dVsx (only for capmod=2).
`csdx (F)`	Intrinsic capacitance dQs_dVdx (only for capmod=2).
`cds (F)`	Intrinsic capacitance dQd_dVs (only for capmod=2).
`cdd (F)`	Intrinsic capacitance dQd_dVd (only for capmod=2).
`cdsx (F)`	Intrinsic capacitance dQd_dVsx (only for capmod=2).
`cddx (F)`	Intrinsic capacitance dQd_dVdx (only for capmod=2).
`csxs (F)`	Intrinsic capacitance dQsx_dVs (only for capmod=2).
`csxd (F)`	Intrinsic capacitance dQsx_dVd (only for capmod=2).
`csxsx (F)`	Intrinsic capacitance dQsx_dVsx (only for capmod=2).
`csxdx (F)`	Intrinsic capacitance dQsx_dVdx (only for capmod=2).
`cdxs (F)`	Intrinsic capacitance dQdx_dVs (only for capmod=2).
`cdxd (F)`	Intrinsic capacitance dQdx_dVd (only for capmod=2).
`cdxsx (F)`	Intrinsic capacitance dQdx_dVsx (only for capmod=2).
`cdxdx (F)`	Intrinsic capacitance dQdx_dVdx (only for capmod=2).
`cgso (F)`	Gate-Source overlap capacitance.
`cgdo (F)`	Gate-Drain overlap capacitance.
`qs (Coul)`	Qs (only for capmod=2).
`qd (Coul)`	Qd (only for capmod=2).
`qg (Coul)`	Qg (only for capmod=2).
`qsx (Coul)`	Charge of sx internal node (only for capmod=2).
`qdx (Coul)`	Charge of dx internal node (only for capmod=2).
`ron (`Ω`)`	On-resistance.
`id (A)`	Resistive drain current.
`is (A)`	Resistive source current.
`pwr (W)`	Power at op point.
`igs (A)`	Gate-to-source current.
`igd (A)`	Gate-to-drain current.
`i1 (A)`	Resistive drain current.

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Spectre Circuit Simulator Components and Device Models ReferenceProduct Version 23.1, June 2023