A

Configuration Flags

This appendix lists the flags, or SKILL variables, associated with the configurable fields in SystemVerilog Integration Environment forms. In addition to setting these flags through the forms, you can set the flags in a configuration file, such as si.env, or from Virtuoso CIW. The appendix also lists additional useful flags that you can set in a configuration file or from Virtuoso CIW.

This appendix includes the following topics:

Important Notes

SystemVerilog Integration Environment is based on NC Verilog Environment. Therefore, they share some common configuration flags. Both the environments also share some features and capabilities.
You can use various SKILL functions for formatting netlist output. These functions are specified as values for the verilogFormatProc property and are common for NC Verilog Environment and SystemVerilog Integration Environment.
For details on the SKILL functions for formatting netlist output and common configuration flags, see the Virtuoso NC Verilog Environment User Guide. Also see the Digital Design Netlisting and Simulation SKILL Reference.

Configuration Flags for Design Details

The following table lists the fields in the main SystemVerilog Integration Environment form and their flags. For details, see “Initializing the Run Directory”.

Flag	Field
	Top Level Design
`simLibName`	Library
`simCellName`	Cell
`simViewName`	View

Configuring Flags for Netlist Generation

The following table lists the fields in the Netlist Setup form and their flags. For details, see “Configuring Options for Generating a Netlist”.

Flag	Field
`simReNetlistAll`	Netlisting Mode
`verilogSimViewList`	Netlist These Views
`simVerilogLaiLmsiNetlisting`	Netlist For LAI/LMSI Models
`simVerilogTestFixtureFlag`	Generate SystemVerilog Test Fixture Template
	Netlist Control Options:
`vtoolsUseUpperCaseFlag`	Netlist Uppercase
`hnlVerilogCreatePM`	Generate Pin Map
`simVerilogFlattenBuses`	Preserve Buses
`simVerilogHandleSwitchRCData`	Netlist SwitchRC
`simVerilogProcessNullPorts`	Skip Null Port
`simVerilogHandleUseLib`	Netlist Uselib
`simVerilogDropPortRange`	Drop Port Range
`simVerilogIncrementalNetlistConfigList`	Incremental Config List
`hnlVerilogNetlistStopCellImplicit`	Symbol Implicit
`vlogifUseAssignsForAlias`	Assign For Alias
`vlogifSkipTimingInfo`	Skip Timing Information
`vlogifDeclareGlobalNetLocal`	Declare Global Locally
`simVerilogNetlistExplicit`	Netlist Explicitly If this field is enabled or its flag is set to `t`, explicit netlisting is performed. If you run the netlister in standalone mode, you need to define this flag in the file `si.env`. Even when you use this option, instances of behavioral modules will still be connected implicitly. To get explicit connections for behavioral modules use the hnlVerilogNetlistBehavioralExplicit variable.
`simVerilogEnableEscapeNameMapping`	Support Escape Names
`simVerilogGenerateSingleNetlistFile`	Single Netlist File
`hnlVerilogTermSyncUp`	Terminal SyncUp
`verilogSimStopList`	Stop Netlisting at Views
`simVerilogPwrNetList`	Global Power Nets
`simVerilogGndNetList`	Global Ground Nets
`simVerilogOverWriteSchTimeScale`	Global TimeScale Overwrite Schematic TimeScale
`simVerilogSimTimeValue`	Global Sim Time
`simVerilogSimTimeUnit`	Global Sim Time Unit
`simVerilogSimPrecisionValue`	Global Sim Precision
`simVerilogSimPrecisionUnit`	Global Sim Precision Unit
`vlogifPreModuleIncludeFile`	Pre-Module Include File
`vlogifInModuleIncludeFile`	In-module Include File

Configuring Flags for Simulation

The following table lists the fields in the Simulation Setup form and their flags. For details, see “Configuring Options for Simulating a Design”.

Flag	Field
`simVerilogInvocationOptionsFile`	Options File
`simVerilogLibraryFile`	Files
`simVerilogLibraryDirectory`	Directories
`simVerilogInvocationOptions`	Other Options
`simNCVerilogPackButton`	Pack Reference Libraries to Reduce Start-up Time
`simNCVerilogPackLib`	Directory
	Object Access
`simNCVerilogReadAccess`	Read
`simNCVerilogWriteAccess`	Write
`simNCVerilogConnectAccess`	Connectivity
`simNCVerilogLineDebug`	Enable Line Debugging
`simNCVerilogDelayMode`	Mode
`simNCVerilogDelayType`	Type
`simNCVerilogSDFDFile`	SDF Command File
`simNCVerilogPulseCtlError`	Error
`simNCVerilogPulseCtlReject`	Reject
`simNCVerilogPulseCtlSpecparam`	Use Pulse Control Parameters
`simNCVerilogEnableTimingCheck`	Enable Timing Check
`simNCVerilogTimingNeg`	Allow Negative Values
`simNCVerilogTimingNot`	Ignore Notifiers
`simNCVerilogSupWarn`	Suppress Warnings
`verilogLogFile`	Simulation Log File
`simNCVerilogSVSuppressUnique`	Unique Statement
`simNCVerilogSVSuppressPriority`	Priority Statements
`simNCVerilogSVRNGSeed="random"`	Random
`simNCVerilogSVRNGSeed="`value`"` Example: `simNCVerilogSVRNGSeed="10"`	Value

Configuring Flags for Test Fixture Files

The following table lists the fields in the Edit Test Fixture form and their flags. For details, see “Specifying the Testbench File and Stimulus File”.

Flag	Field
`vlogifCurrentTestFixture`	TestBench File Name
`vlogifCurrentStimulus`	Stimulus File Name

Other Flags for Netlist Configuration

The following table describes some other flags for netlist configuration.

Flag	Field
`vlogIfSVEnableDataTypeOverRiding`
	Sets the data type propagation. By default, this flag is set to `t` to enable data type propagation. For details, see “Overriding Hierarchical Data Type Propagation”. For an example of data type propagation, see “Overriding Hierarchical Data Type Propagation in a Design”.
`simSVPortPropertyList`	When enabled, allows specifying only the `dataType` property and leaving the `portKind` property blank. Example: simSVPortPropertyList = '( ("analogLib" "res" "symbol" "vob_ana wreal1driver nil unPackedExplicit" ) ) This will print: input wreal1driver vob_ana [1023:0];
`hnlPrintNonAnsiSV`	Enables the Verilog 95 non-ANSI SystemVerilog format support. By default, SystemVerilog Integration Environment uses the Verilog-2001 SystemVerilog ANSI format. To enable the Verilog 95 non-ANSI SystemVerilog format support, set `hnlPrintNonAnsiSV` to `t` in the simulation run control file`.simrc`. For details on the `.simrc` file, see Customization of the Simulation Environment Using the .simrc File.
`vlogPrintAssignForUnpacked`
	Enables the capability of printing the assign statements for the unpacked arrays of a design in the netlist. By default, this flag is set to `nil`. To print assign statements, set this flag to `t` in your netlist configuration file. For an example of a netlist with an assign statement, see Netlisting a Design Containing Packed and Unpacked Arrays.
`vlogPrintConcatenationForUnpacked`
	Enables the printing of concatenation statements instead of assignment statements for unpacked arrays. For example, `{net1 net2}` instead of `'{net1 net2}`. By default, this flag is set to `nil`. To print the concatenation statements, set this flag to `t` in your netlist configuration file.
vlogPrintAliases	Enables the printing of alias statements for signals connected to the patch element. For example, if signals connected to the patch element are `a`, `b` then, alias `a` `=` `b` will be printed.
`hnlProcessAliasSignalWithSourceDirection`
	A flag that specifies that the netlister uses aliasing between more than two signals. By default, it is set to `nil`. It requires adding the `direction` property of the net, where the property value must be set to the source. The following example shows aliasing between the signals `a`, `z<0>`, and `z<1>`. Here, if the source net is `a`, then the `direction` property must be set on net a, where the property value is set to source.
`hnlUseSchematicForSystemVerilogView`
	A flag that supports printing inherited connections from the schematic when the instances are bound to a SystemVerilog view. Consider an instance `i0` that is bound to a SystemVerilog view and has two ports `a`, `b` in the module definition.
	In the top cell, the instantiation of `i0` has only one port, `a`. However, an inherited connection is also created in the schematic view of `i0`. When the instance is bound to a SystemVerilog view and you enable the `hnlUseSchematicForSystemVerilogView` flag, the netlist shows the inherited connections from the schematic view as shown below.

Return to top

Virtuoso Verilog Environment for SystemVerilog Integration User GuideProduct Version IC23.1, June 2023

A