Contents
1
Introducing SystemVerilog Integration Environment
Netlist Generation and Design Simulation Flow
About Creating SystemVerilog-Based Designs
2
Generating Netlist and Simulating Designs
Initializing the Run Directory
A
Configuration Flags
Configuration Flags for Design Details
Configuring Flags for Netlist Generation
Configuring Flags for Simulation
Configuring Flags for Test Fixture Files
Other Flags for Netlist Configuration
B
Examples
Overriding Hierarchical Data Type Propagation in a Design
Netlisting a Design Containing Packed and Unpacked Arrays
C
Running Simulations with Xcelium
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