2 Generating Netlist and Simulating Designs

This chapter includes the following topics.

Overview

The following figure shows how to use SystemVerilog Integration Environment for netlisting and simulating a design. For details on the functionality, features, generic flow, tool requirements, and the graphical user interface of this environment, see Chapter 1, “Introducing SystemVerilog Integration Environment.”

This chapter uses the following design example to illustrate the netlist generation and design simulation tasks.

Design Example

This guide uses a SystemVerilog-based drink machine design as an example to illustrate tasks performed using SystemVerilog Integration Environment. This design has the following SystemVerilog modules:

drink_machine counts the amount of change that a user enters, dispenses a drink, and returns any due change.
coin_counter loads the machine with coins and determines when the machine is out of coins.
can_counter loads the machine with drinks and determines when the machine is empty.
The section “About Creating SystemVerilog-Based Designs” illustrates the creation of the can_counter cellview and symbol.

The drink machine design kit includes the ifc.v file that contains the definition of some of the interfaces used in the design. This file must be included before the module declaration in the netlist. The drink machine design kit also includes test_drink.v that you can use as a testbench for initializing the machine and buying drinks.

This chapter assumes that you have launched the SystemVerilog Integration Environment for this drink machine design. For details, see “Launching the Graphical User Interface”.

Initializing the Run Directory

When a simulation is run on the Cadence system, all inputs and outputs of the simulation process are contained in a single directory. This directory is referred to as the run directory.

Initializing a run directory for a design means setting the environment for netlist generation and design simulation. When you initialize the run directory, the SystemVerilog Integration Environment adds some files and a directory to the run directory. It adds the si.env file to store netlist generation and design simulation settings. It also adds .vlogifrc to store Verilog and SystemVerilog format-specific configuration.

Note the following before initializing a run directory:

If the run directory exists and contains the .simrc configuration file, the SystemVerilog Integration Environment loads settings from this file.
If the run directory exists and contains the .vlogifrc configuration file containing Verilog and SystemVerilog format-specific configuration flags, the environment loads settings from this configuration file.
If the specified run directory does not exist, the environment loads the $HOME/ .vlogifrc file. If the home directory does not contain .vlogifrc, the environment loads the default settings.
If you are using a run directory and attempt to change it, the environment prompts you for confirmation whether you want to use the previous run directory settings for the new run directory.
For details on si.env and .simrc, see the Open Simulation System Reference.

To initialize the run directory for a design:

Ensure that the top-level design is correctly specified in the Library, Cell, and View fields of the main form.

By default, the SystemVerilog Integration Environment displays the library, cell, and view of the design opened in Virtuoso Schematic Editor, from where you launched the environment. To change the design, do one of the following:
- Click Browse and select the library, cell, and view using Library Browser.
- Enter the library, cell, and view in their respective fields.
If you choose the top-level configuration view of the design, you can click Hierarchy Editor and use Virtuoso^® Hierarchy Editor to browse the design hierarchy and edit design configurations.
Specify the run directory.
By default, the SystemVerilog Integration Environment displays the directory workingDirectory/topCellName_svrun1 in the Run Directory field. To change the run directory, do one of the following:
- Click the browse button and select the directory.
- Enter the path of the run directory.
You can specify a directory relative to the current working directory. The environment automatically expands the relative directory to its full path.
To initialize the run directory, do one of the following:
- Click Initialize Design on the toolbar.
- Choose Commands — Initialize Design.
The SystemVerilog Integration Environment does the following:
- Adds initial files and directory to the run directory
- Changes the Status on the main form from Uninitialized to Ready
- Enables the options to configure netlist generation and design simulation
- Enables the option to generate a netlist

Netlisting a Design

You can generate a netlist, which contains connectivity information of a design, after you have initialized a run directory for that design. Configure the netlist generation options before you generate the netlist. When you generate the netlist, the SystemVerilog Integration Environment creates a map file containing the netlist configuration options, and the map of the names used in the netlist and their corresponding names in the design. The environment lets you view the netlist and the map file.

This section provides information on the following topics.

Configuring Options for Generating a Netlist

You can configure various options, based on which the SystemVerilog Integration Environment generates a netlist. The environment stores these configurations in the si.env and .vlogifrc files located in the run directory.

To configure netlist generation options after you have initialized the run directory:

Choose Setup — Netlist. The Netlist Setup form appears.
Set options as required.
For example, to configure netlist generation for the sample drink machine design, you specify the path to ifc.v in the Pre-Module Include File field and retain other default settings. This include file contains the definition of interfaces. The SystemVerilog Integration Environment includes this file before the module declaration in the netlist.
Click OK.

You can create a .simrc file in the run directory and store your default netlist generation and simulation configurations in this file. Configurations in .simrc overwrite configurations in si.env.

By default, the environment uses the Verilog-2001 SystemVerilog ANSI format. To enable the Verilog 95 non-ANSI SystemVerilog format support, set hnlPrintNonAnsiSV to t in the .simrc file.

The following figure illustrates the Netlist Setup form and the table describes the configuration options. For information on the configuration flag associated with the fields in this form, see “Configuring Flags for Netlist Generation”.

Field	Description and Flag
Netlisting Mode	Select the netlisting mode from: Entire Design: Netlists the entire design, regardless of which cells have been modified since the last netlist was generated. Incremental: Netlist only those parts of the design that have changed since the last netlist was generated. Off: Does not generate netlist of the design if another netlist exists. Flag: `simReNetlistAll`
Netlist These Views	Enter the views that you want to netlist for each cell or module. You use this option with the Stop Netlisting at Views. The environment starts at the top-level cell in the design being simulated and works down the hierarchy, selecting the appropriate view for each cell netlisted. For each cell, the netlister searches for a view from the list, in left-to-right order, and netlists the first view it finds that is on the list. The default list is: systemVerilog behavioral_sv functional_sv verilog_sv behavioral functional verilog schematic symbol Flag: `verilogSimViewList`
Netlist For LAI/LMSI Models	Select if you want to use one of these simulation models: LOGIC Automation Incorporated (LAI) models: The `lai_verilog` property values indicate the use of these models Logic Modeling Systems Incorporated (LMSI) hardware simulation models: The `lmsi_verilog` property values indicate the use of these models. Cells that do not have the `lai_verilog` or `lmsi_verilog` view type are netlisted according to the priorities established with the Netlist These Views and Stop Netlisting at Views options. To attach the `lai_verilog` or `lmsi_verilog` view property to an instance on a Virtuoso Schematic Editor schematic, use the Edit – Properties command available on the schematic window. For details, see the Virtuoso Schematic Editor L User Guide. Flag: `simVerilogLaiLmsiNetlisting`
Generate SystemVerilog Test Fixture Template	Select if you want the SystemVerilog Integration Environment to generate sample SystemVerilog testbench and stimulus files. You can edit these files and use them for simulating the design. For details, see “Specifying the Testbench File and Stimulus File”. Flag: `simVerilogTestFixtureFlag`
Netlist Control Options	Select the following options to control netlist generation. Netlist Uppercase: Generates a netlist in uppercase letters. Flag: `vtoolsUseUpperCaseFlag` Generate Pin Map: Creates the pin mapping files necessary to convert Standard Delay Files (SDF) pin names to SystemVerilog pin names. These files are stored in the RunDirectory`/pinMap` directory. Select this option only when you want to back annotate. Use this option when the pin names for a symbol in your schematic differ from those in the SystemVerilog library model description. After the pin map is created, the entire design is netlisted automatically to ensure that the netlister creates pin maps for the entire design. The Generate Pin Map option must remain selected on subsequent runs. Otherwise, the netlister deletes your pin map directory. Flag: `hnlVerilogCreatePM` Preserve Buses: Preserves buses (vectors) in the netlist. If this option is not selected, the netlister expands vector nets to single-bit equivalents (scalars) in the netlist. Flag: `simVerilogFlattenBuses` Netlist SwitchRC: Includes user-defined RC switch properties in the netlist. Flag: `simVerilogHandleSwitchRCData` Skip Null Port: Ignores floating instance ports. Flag: `simVerilogProcessNullPorts`
	Netlist Uselib: Automatically adds the `'uselib` directive to the netlist when a design includes two similarly named cells from two different libraries. Flag: `simVerilogHandleUseLib` Drop Port Range: Prints the module port without the port range. Flag: `simVerilogDropPortRange` Incremental Config List: Writes the renetlisted cellviews to the configuration list of the design. Flag: `simVerilogIncrementalNetlistConfigList` Symbol Implicit: Suppresses printing the net name during instance port formatting. Flag: `hnlVerilogNetlistStopCellImplicit` Assign For Alias: Uses an assignment statement for patches between nets. If you disable this option, the netlister applies the default `cds.alias` to patches between nets. Flag: `vlogifUseAssignsForAlias` Skip Timing Information: Ignore timing information assigned to instances in the design. Flag: `vlogifSkipTimingInfo` Declare Global Locally: Lets you declare global signals locally. When you disable this option, the netlister uses the default signals (Global Power Nets and Global Ground Nets). Flag: `vlogifDeclareGlobalNetLocal`
	Netlist Explicitly: Generates name-based port lists using the connection-by-name syntax for modules in views. If you disable this option, the netlister generates order-based port lists. This option does not apply to instances whose master module is generated by the netlister. For example, the netlister converts all schematics into modules and order-based port lists are created for the instances of these modules. Flag: `simVerilogNetlistExplicit` Even when you enable this option, instances of behavioral modules will still be connected implicitly. To get explicit connections for behavioral modules use the hnlVerilogNetlistBehavioralExplicit variable. Support Escape Names: Include escaped names in the netlist. It also allows you to escape names that are reserved keywords in SystemVerilog. Flag: `simVerilogEnableEscapeNameMapping` Single Netlist File: When selected, generates a single netlist instead of multiple netlists, one for each module. The netlist file is generated in the current simulation run directory. Flag: `simVerilogGenerateSingleNetlistFile`
Terminal SyncUp	Specifies how to synchronize terminals between an instance and its switched master. You can choose from the following options: Expand on Mismatch: Retains the design terminals as is, unless there is a mismatch. In case of a mismatch, the netlister expands the mismatched terminals. Use this default option to generate a pure explicit netlist with flattened buses. Honor Switch Master: Always honors the switch master terminals. Merge All: Merges all terminals to create simple scalar and pure bus terminals. The resulting netlist does not have any bundles or split buses. You can also set the `hnlVerilogTermSyncUp` variable in the `.vlogifrc` file. The possible values are `mergeAll`, `honorSM`, and `nil` (default). Flag: `hnlVerilogTermSyncUp`
Stop Netlisting at Views	Enter the list of views that controls the level of hierarchy at which netlisting stops. After netlisting a cell, the netlister checks whether the view netlisted is on this stop list. If it is in this list, the netlister stops expansion of the design for this cell. The order of views in the stop list is irrelevant. The default list is: systemVerilog verilog_sv verilog symbol Flag: `verilogSimStopList`
Global Power Nets	Enter the global net names you want netlisted with the supply1 wire type. Supply1 wire types are driven to logic state 1. The net names you specify must conform to global naming conventions as described in the Virtuoso Schematic Editor L. Flag: `simVerilogPwrNetList`
Global Ground Nets	Enter the global net names you want netlisted with the supply0 wire type. Supply0 wire types are driven to logic state0. The net names you specify must conform to global net naming conventions. Flag: `simVerilogGndNetList`
Global TimeScale Overwrite Schematic TimeScale	Select to overwrite any time values or units defined within a schematic with the following global variables: Global Sim Time and Unit Flags: simVerilogSimTimeValue and simVerilogSimTimeUnit Global Sim Precision and Unit Flags: simVerilogSimPrecisionValue and simVerilogSimPrecisionUnit The unit can be s`,` ms`,` us`,` ns, or ps.
Pre-Module Include File	Enter or select the file that the netlister must use as the include file before the module declaration in the netlist file generated for each hierarchical cellview. If hnlVerilogDumpIncludeFilesInNetlist is set to `t`, the content of the include file is copied to the netlist, instead of an `‘include` statement`.` Flag: `vlogifPreModuleIncludeFile`
In-module Include File	Enter or select the file that the netlister must use as an include file immediately after the module declaration in the netlist file generated for each hierarchical cellview. If hnlVerilogDumpIncludeFilesInNetlist is set to `t`, the content of the include file is copied to the netlist, instead of an `‘include` statement`.` Flag: `vlogifInModuleIncludeFile`

By default, the text files of Stop Netlisting at Views are included in the generated netlist. You can use vlogifVicSVTextCellViewList to include text files, in addition to the mandatory SystemVerilog text file. Use the following syntax in Virtuoso CIW or si.env:

vlogifVicSVTextCellViewList = (list "view_type_1" "view_type_2" "view_type_n")

For example:

vlogifVicSVTextCellViewList = (list "systemVerilogText" "text.v")

In this example, systemVerilogText represents the SystemVerilog view type and text.v represents the Verilog view type.

Printing CDF Parameters in Inline Explicit Format

If an instance has CDF parameters as well as Verilog parameters, both the parameters can be read during netlisting. For the CDF parameters to be printed in the inline explicit format, the following flags need to be set to true in the .simrc file or at CIW:

hnlVerilogPrintCDFParamExplicit = t

hnlVerilogPrintOverriddenCDFParamOnly = t**Does not print the default value of parameter

hnlVerilogPrintParamExplicitNonStopping = t** Prints Verilog/CDF parameters for non stopping cells.

The hnlVerilogPrintCDFParamExplicit flag, in turn, requires the following flags to be set to true:

hnlVerilogDonotPrintDefparam = t simVerilogPrint2001Format = t

To print CDF parameters like Verilog parameters on the instance line, define the CDF parameter hnlVerilogCDFdefparamList with the following setting:

paramType: string

parseAsCEL: yes

name: hnlVerilogCDFdefparamList

prompt: hnlVerilogCDFdefparamList

defValue: <names of all/subset of already-defined CDF parameters separated by space. These will be netlisted in inline explicit format at instance>

display: nil

Verilog parameters and CDF parameters can have the same name.

When an instance with both CDF as well as Verilog parameters is encountered, the following rules are followed for netlisting:

Verilog parameters are given precedence over CDF parameters. Additionally, the values of Verilog parameters override the values of CDF parameters.
Verilog parameters follow the order of precedence defined in the paramOrder property.
If the value of a CDF parameter is changed for an instance, then the parameter with the new value is netlisted.

Managing Data Type Conflicts

The SystemVerilog Integration Environment supports data type propagation from leaf-level SystemVerilog cellviews to the top-level schematic design hierarchy. During data type propagation, conflicts can occur in the following cases.

Conflict: An instance with a SystemVerilog data type and another instance with no data type are connected to a pin.
Resolution: The SystemVerilog data type is propagated.
Conflict: Two instances connected to a pin have different SystemVerilog data types.
Resolution: To determine which data type must be propagated, set a custom conflict resolution mechanism. For this, define the function hnlSVResolveDataTypeConflict as required. The return value of this function must be list(isRefPort portKind dataType isUnpacked).
For further details and an example of resolving such a conflict, see “Resolving Data Type Conflict”.

Overriding Hierarchical Data Type Propagation

In a design hierarchy, SystemVerilog Integration Environment propagates data type from the leaf-level SystemVerilog cellviews to the top-level schematic. You can override the data type propagation from a port of a leaf-level SystemVerilog cellview to the top module in the hierarchy.

To override the data type propagation from a port, change the value of the dataType property of that port in the place master of the cellview to the data type you want to propagate. In this method, you do not need to change the data type of the port in the cellview.

The following figure illustrates the override. In this figure, SV1 and SV2 are SystemVerilog cellviews, each containing a port of data type A. In the place master of SV1, the data type of the port is overridden by data type B, which is further propagated in the design hierarchy.

For further details and an example of overriding data type propagation, see “Overriding Hierarchical Data Type Propagation in a Design”.

If you do not want to override the data type propagation, set vlogIfSVEnableDataTypeOverRiding to nil.

Ignoring Port Type Propagation

If you have systemVerilog ports declared as real var <port_name> and generate a virtuoso schematic symbol, the real port will have dataType = real and portKind = var.

If you connect this port to another symbol port, which has dataType = logic and portKind = wire, you can successfully generate an NCVerilog /SystemVerilog netlist. However, if you try to use this netlist in an irun simulation, the elaboration fails due to incompatible port connection. To avoid this issue, you can ignore the data type and port information propagation by setting the vlogIfSVDisableDataPropagation flag to t in your .simrc file.

Adding Port Properties to an Instance

The Verilog Environment for SystemVerilog Integration allows you to modify the port properties dataType and portKind, which are specific to an instance. When ignoreDataType is set to t, the properties dataType and portKind are ignored. Instead, the dataType information that is propagated from the bottom-level cell to the top-level cell is considered.

You can add the ignoreDataType property on a specific instance terminal in the schematic. If this property is selected, the SystemVerilog Integration environment will not print the Master Value and the Local Value.

Additionally, you can modify the local values of the port properties dataType and portKind that are associated with a specific instance of a cell.

The following table clearly describes the impact of enabling and disabling the ignoreDataType property on the port of an instance in different scenarios:

Condition	Additional Condition	Result
`ignoreDataType` `= t`		The master values and local values of `dataType` and `portKind` are ignored. Instead, `dataType` information propagated from the bottom cell to the top cell is used.
`ignoreDataType` `= nil`	The local value of `dataType` is set to custom_value.	The local value of the specific instance is used instead of the value set on the symbol cell.
`ignoreDataType` `= nil`	The local values are not set for `dataType` and `portKind`.	The master value of the symbol cell property is used.

Example

Consider the input port I2 in the following schematic and the related condition scenarios that follow.

When ignoreDataType is set to t is set on the port of an instance
When you set ignoreDataType to t on I2, the master and local values of dataType and portKind are ignored. In such a case, dataType information that is propagated from the bottom-level cell to the top-level cell is used.

The following example shows how the netlist displays the port information in this scenario:

module tb_w_voltage ( 
output wire logic   VOUT0, 
output wire logic   VOUT1, 
output wire logic   VOUT2, 
input wire logic   GNDA_ADC, 
input  voltage     VIN0,
input  voltage     VIN1 );

Here, the wire logic value is derived from the dataType property of the bottom-level cell.

When ignoreDataType is set to nil and the local value of dataType is set to custom_value
When you set ignoreDataType to nil on I2 and the local value dataType to myvoltage, the local value myvoltage of the specific instance is used, instead of the master value voltage that is set on the symbol cell.

The following example shows how the netlist displays the port information in this scenario:
```
module tb_w_voltage ( 
output wire logic   VOUT0, 
output wire logic   VOUT1, 
output wire logic   VOUT2, 
input  myvoltage   GNDA_ADC,
input  voltage  VIN0, 
input  voltage  VIN1 );
```
Here, the local value overrides the master value.
When ignoreDataType is set to nil and the local value of dataType is not set
When you set ignoreDataType to nil on I2 and the local values of dataType and portKind are not set, the master value voltage of the symbol cell property is used.

The following example shows how the netlist displays the port information in this scenario:
```
module tb_w_voltage ( 
output wire logic   VOUT0, 
output wire logic   VOUT1, 
output wire logic   VOUT2, 
input  voltage GNDA_ADC,
input  voltage  VIN0, 
input  voltage  VIN1 );
```
Here, the property of the symbol cell (master value) is used.

Generating a Netlist

You typically generate the hierarchical netlist of a design in the following cases:

Before simulating a new design
After modifying a cell in your design
After modifying a cell instantiated from a source library

Before you generate the netlist of a design, ensure that the run directory is initialized and the netlist generation options are configured as required. SystemVerilog Integration Environment generates the netlist based on how you have configured these options. It also generates a map file that includes key netlist configurations and the map of the names used in the netlist and their corresponding names in the design.

Notes:

SystemVerilog Integration Environment initializes all the OSS tabular name mapping variables to ensure that the generated netlist contains all the names in SystemVerilog namespace. It maps the OSS names for the design to SystemVerilog constructs, which is listed in the map.
SystemVerilog Integration Environment supports the netlisting of designs with ports of type packed and unpacked arrays. For details, see “Netlisting a Design Containing Packed and Unpacked Arrays”.

SystemVerilog Integration Environment stores the netlist and map files in the runDirectory/inhl/cds0 directory. It also creates various files and folders in the run directory.

To generate a netlist and a map file of a design based on netlist configuration, do one of the following:

Click Generate Netlist on the toolbar.
Choose Commands — Generate Netlist.
SystemVerilog Integration Environment does the following:
- Generates the netlist and map files and stores them in the run directory.
- Changes the Status on the main form from Ready to Netlisting Succeeded.
- Enables the options to view the netlist and map file.
- Enables the option to simulate the design.

Viewing a Netlist and a Map File

After generating a netlist, you can view the hierarchical netlist containing the connectivity information of the design. You can also view the map file containing the netlist configuration options and the map of the names used in the netlist and their corresponding name in the design.

To view the netlist or the map file of a top-level design:

Choose Results — Netlist. The View Netlist Run Files form appears.
Select Netlist if you want to view the netlist content.
Select Map if you want to view the map file content.
Select the library from the Library Name list.
Select the cell from the Cell Name list. The File Path field displays the location of the netlist or map file.
If you want to refresh the list of libraries and cells, click Load.
Click View. A text window appears with the file contents.

The following figure illustrates how SystemVerilog Integration Environment displays the netlist and the map file.

Simulating a Design

Configure the design simulation options before you simulate a design for which you have generated a netlist. You can also specify the testbench and the stimulus you want to use for the simulation. You can then simulate the design in interactive or batch mode.

This section provides information on the following topics.

For information on using SystemVerilog Integration Environment in standalone mode, see “Using Standalone Mode”.

Configuring Options for Simulating a Design

You can configure various options, based on which SystemVerilog Integration Environment simulates a design. The environment lets you configure the simulation after you have initialized the run directory. It saves the Verilog and SystemVerilog format-specific settings in the .vlogifrc file. Settings in .vlogifrc overwrites the configurations in si.env and .simrc.

To configure simulation options:

Choose Setup — Simulation. The Simulation Setup form appears.
Set options as required.
For example, to configure the simulation of the sample drink machine design, you configure the following fields as indicated and retain other default settings.

Field Value

Unique Statements

Select

Priority Statements

Select

RNG Seed > Value checkbox

Select

RNG Seed > Value text field

3
Click OK.

Field	Value
Unique Statements	Select
Priority Statements	Select
RNG Seed > Value checkbox	Select
RNG Seed > Value text field	3

The following figure illustrates the Simulation Setup form and the table describes the configuration options. For information on the configuration flag associated with the fields in this form, see “Configuring Flags for Simulation”.

Field	Description and Flag
Options File	Specify the path to the options file relative to the directory from which you started the Virtuoso session. The simulation is based on the SystemVerilog command options defined in the file. The file can also contain source text filenames or NC Verilog predefined + or - options that are not available through the interface. Flag: `simVerilogInvocationOptionsFile`
Reference Libraries
Files	Specify the path to the library files containing third-party SystemVerilog libraries used with this design. You can specify multiple paths. Flag: `simVerilogLibraryFile`
Directories	Specify the path to the dedicated library directory containing third-party SystemVerilog library used with this design. You can specify multiple paths. Flag: `simVerilogLibraryDirectory`
Other Options	Specify the file extensions that SystemVerilog Integration Environment must read in the specified directories. Flag: `simVerilogInvocationOptions`
Pack Reference Libraries to Reduce Start-up Time	Select to specify a path where the compiler compiles the reference library files and directories. Flag: `simNCVerilogPackButton`
Directory	Specify the path to the directory where the compiler must store the reference library files and directories. Flag: `simNCVerilogPackLib`
Debug
Optimize for Best Performance	Select to set the visibility access for all objects in the design. Use this option to increase the simulation performance by not giving read, write or connectivity access to the simulation objects.
Object Access	Select if you want to apply a specific type of access to the simulation object. The access can be: Read: Select to probe objects in the design and generate a Simulation History Manager (SHM) database or a Value Change Dump (VCD) database. This option lets you use SimVision to view waveforms, or SimCompare to compare the databases. Flag: `simNCVerilogReadAccess` Write: Select to specify values using the interactive simulation interface. For example, select this option when you use the force or deposit commands from the interactive simulation interface. Flag: `simNCVerilogWriteAccess` Connectivity: Select to display the load or driver information. For example, select this option if the driver command requires the load or driver information. Flag: `simNCVerilogConnectAccess` The default value is Read access.
Enable Line Debugging	Select to use line break points and single stepping. It lets you break on a sequence execution and step in for debugging the design object. Flag: `simNCVerilogLineDebug`
Delay
Mode	Select the delay mode. You can choose from: Zero: Select to ignore all module path delays, timing checks, and structural and continuous assignment delays. Path: Select to use path delay information from specified blocks that contain module path delays; ignore structural and continuous assignment delays, with the exception of `trireg` charge decay times. Unit: Select to ignore module path delays and timing checks and convert all structural and continuous assignment delays that are nonzero to a single time unit. Distributed: Select to use the delay on nets, primitives, and continuous assignments and ignore module path delays. None: Select to use all of the delays in your netlist. Flag: `simNCVerilogDelayMode`
Type	Specify the delay type to apply during simulation. You can choose from: Minimum: Select to use all minimum delays. Typical: Select to use all typical delays. Maximum: Select to use all maximum delays. Flag: `simNCVerilogDelayType`
SDF Command File	Specify the name and path to the Standard Delay File (SDF) containing commands that the elaborator should annotate. If an SDF delay file already exists, the elaborator automatically generates an SDF command file and displays the filename in this field. Flag: `simNCVerilogSDFDFile`
Pulse Control
Error	Specify the error limit percent. You typically set it to 0, 50, or 100 percent. A pulse that is less than or equal to the specified percentage but greater than the reject limit, sets the module path output pulse to the e logic value. Flag: `simNCVerilogPulseCtlError`
Reject	Specify the rejection percentage. You typically set it to 0, 50, or 100 percent. Flag: `simNCVerilogPulseCtlReject`
Use Pulse Control Parameters	Select to read in the `PATHPULSE$` special parameter from the SystemVerilog model in the SystemVerilog library, which overrides the global pulse control. Flag: `simNCVerilogPulseCtlSpecparam`
Timing
Enable Timing Check	Select to specify the following types of timing checks. Allow Negative Values: Select to allow negative values in `$setuphold` and `$recrem` timing checks in the SystemVerilog or Verilog description and in `SETUPHOLD` and `RECREM` timing checks in the Standard Delay Files (SDF) annotation. If this option is not set, negative values in the description or in the SDF annotation are set to 0 and a warning is generated. Flag: `simNCVerilogTimingNeg` Ignore Notifiers: Select to ignore notifiers in timing checks. Flag: `simNCVerilogTimingNot` Flag: `simNCVerilogEnableTimingCheck` for Enable Timing Check
Suppress Warnings	Select to suppress all warnings during simulation. Flag: `simNCVerilogSupWarn`
Simulation Log File	Specify the file to store simulation logs in the run directory. The default file is `simout.tmp`. Flag: `verilogLogFile`
irun Options
Include Extensions	Select the `SystemVerilog` or `Verilog` language whose file extensions you want to specify. In the text box, specify the comma-separated or space-separated list of file extensions. The default list for SystemVerilog is: .template,.sv,.SV,.svp,.SVP,.svi,.svh,.vlib,.VLIB The default list for Verilog is: .v,.V,.vp,.VP,.vs,.VS The irun utility lets you simulate a mixed language design containing Verilog and SystemVerilog modules. During simulation, the irun utility processes files with the SystemVerilog and Verilog extensions specified in this field.
Suppress Semantic Checks
Unique Statement	Select to suppress the semantic checking of unique constructs to shorten the simulation time. Flag: `simNCVerilogSVSuppressUnique`
Priority Statements	Select to suppress the semantic checking of priority constructs to shorten the simulation time. Flag: `simNCVerilogSVSuppressPriority`
RNG Seed
Random	Select to randomly generate a seed value to initialize the random number generator (RNG) of the simulator. Flag: `simNCVerilogSVRNGSeed="random"`
Value	Select to specify a seed value for the simulator and enter the value in the corresponding input field. Flag: `simNCVerilogSVRNGSeed="`value`"`

Specifying the Testbench File and Stimulus File

SystemVerilog Integration Environment lets you use the following files to initiate the simulation of a design:

Testbench file containing instantiation of the complete design
Stimulus file containing the preinitialized signal settings that drive a simulation

The testbench and stimulus files are referred to as the test fixture files.

You can set SystemVerilog Integration Environment to create the following sample test fixture files in the run directory during netlist generation. For this, select Generate SystemVerilog Test Fixture Template on the Netlist Setup form. The environment stores references to the test fixture files in the .vlogifrc configuration file.

testfixture.template: The default testbench file
testfixture.sv: The default stimulus file
The test fixture files should have the valid file extensions listed in the Include Extensions field on the Simulation Setup form. You must edit and check the contents of the sample test fixture files before you use them for simulation.

For information on the configuration flag associated with the fields in this form, see “Configuring Flags for Test Fixture Files”.

To work with the sample test fixture files:

Choose Commands — Edit Test Fixture. The Edit Test Fixture form appears.

If you have generated a netlist for the first time in a new run directory, the names of the default files appear on the Edit Test Fixture form. Otherwise, the form displays the names of the files used during the previous simulation.
Edit and save the sample test fixture files as required.
SystemVerilog Integration Environment generates the sample test fixture files with commented statements for reference, considering that a SystemVerilog module can have different types of ports at top-level. You must edit these files appropriately. Using the sample test fixture files without proper modification can causes the simulation to fail.
For the sample drink machine design, you can copy the contents of the test_drink.v file to the testbench file. The test_drink.v file is provided with the sample drink machine design kit. Also check the stimulus file contents.
Click OK to save the test fixture setting and close the form.

If you do not want to use the test fixture files for simulation, clear the Generate SystemVerilog Test Fixture Template checkbox on the Netlist Setup form and clear the Set Selected File As TestBench/Stimulus checkboxes on the Edit Test Fixture form. In this case, when you run the simulation in interactive mode, SystemVerilog Integration Environment launches SimVision without applying any stimulus. The batch mode does not require test fixture files.

The flag for the testbench file name is vlogifCurrentTestFixture. The flag for the stimulus file name is vlogifCurrentStimulus.

Simulating a Design in Interactive Mode

Interactive mode of simulation lets you choose the compilation, elaboration, and simulation steps to perform. In this mode, SystemVerilog Integration Environment uses the NC tools and launches SimVision to let you interactively simulate the design. Using SimVision, you can directly interact with the ncsim simulator to open a database, trace signals, set breakpoints, observe signals, and perform other functions to verify your design.

If you want to view simulation results in the SimVision window, set the SKILL variable simNCVerilogNostdout to nil in the Virtuoso CIW or in the simulation run control file .simrc before simulating the design. The default value of this variable is t.

To simulate a design in interactive mode:

Click Interactive in the Simulation Mode area of SystemVerilog Integration Environment main form.
Choose one of the following options.
- Compile
- Compile and Elaborate
- Elaborate and Simulate
- Simulate
  Before you can simulate a design, you must first compile the design and then elaborate it.
Do one of the following:
- Click Simulate on the toolbar.
- Choose Commands — Simulate.
SystemVerilog Integration Environment performs the selected steps and informs you about the status.
If you chose the Simulate option, the environment launches SimVision. If you specified the test fixture files, the environment uses them to initiate the simulation. Otherwise, you must initiate the simulation.
The following figure illustrates SimVision, which has been launched to simulate the sample drink machine design. For details on using SimVision, see the SimVision User Guide.

Simulating a Design in Batch Mode

Batch mode of simulation compiles, elaborates, and simulates the design in that order. It uses the NC tools for performing these steps. SystemVerilog Integration Environment provides a window to monitor the status of the batch simulation job.

To simulate a design in batch mode:

Click Batch in the Simulation Mode area of SystemVerilog Integration Environment main form.
Choose Results — Job Monitor to open the window for monitoring the batch simulation job. The Analysis Job Monitor window appears.
Do one of the following on SystemVerilog Integration Environment main form:
- Click Simulate on the toolbar.
- Choose Commands — Simulate.
SystemVerilog Integration Environment uses the NC tools to compile, elaborate, and simulate the design, without launching SimVision.
If the Analysis Job Monitor window is open, the environment displays the simulation status. This window also displays the status of the previous batch jobs. It includes an entry for each job and lets you prioritize, suspend, continue, or kill active jobs. For details on using this window, choose Help and see the Simulation Environment Help.

After completing the simulation, SystemVerilog Integration Environment displays a message, informing you about the simulation result.

Using Standalone Mode

You can run Open Simulation System-based SystemVerilog Integration Environment in standalone mode to generate a netlist of a top-level SystemVerilog-based design and simulate that design.

Cadence recommends that you initialize the run directory and configure the netlist and simulation options using the graphical user interface of SystemVerilog Integration Environment. If required, you can modify settings in the simulation environment configuration file .simrc or si.env. Note that settings in .simrc have presidence over settings in si.env.

To use standalone mode of SystemVerilog Integration Environment, ensure that the run directory includes si.env with the necessary configurations. If this file is absent, you cannot netlist and simulate a design in standalone mode.

The si.env file is primarily used to instruct the simulation environment which design to simulate and which simulator to use. It is recommended not to include additional flags in this file because they can be lost after the simulation is run. Instead, use the .simrc file to customize simulation runs. Settings in this file overrides settings in si.env. For details, see How SE Works in Open Simulation System Reference.

You use the si command in the following syntax to generate a netlist and simulate a design.

si [run_directory] [-batch [-command commandName]] [-cdslib path]

In this syntax:

si represents the Open Simulation System (OSS) binary file.
-batch refers to the batch simulation mode.
-command specifies the command to generate a netlist or simulate a design
You typically use the following -command options for your SystemVerilog-based designs:
- netlist instructs the simulation system to netlist the design.
- vlogifNCSVSetupBatch instructs the simulation system to simulate the design.
-cdslib specifies the full path of cds.lib, which defines the design libraries and the path to these libraries.

For more information on the si command line interface, see the Open Simulation System Reference.

The following examples illustrate how you use SystemVerilog Integration Environment in standalone mode.

Run si from the run directory to netlist the design referred in si.env. The cds.lib file is located in the home directory.
si -batch -command netlist -cdslib ~/cds.lib
Run si from the run directory to simulate a SystemVerilog-based design referred in the si.env file.
si -batch -command vlogifNCSVSetupBatch

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Virtuoso Verilog Environment for SystemVerilog Integration User GuideProduct Version IC23.1, June 2023

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Generating Netlist and Simulating Designs