Product Documentation
Virtuoso Design Planning and Analysis User Guide
Product Version IC23.1, November 2023

Make Cell Form

Use the Make Cell form to create real cellviews for the selected virtual hierarchies. You can also use the form to create a bottom-up layout view for each level of virtual hierarchy inside the selected virtual hierarchy.

If the design is opened in Virtuoso Layout Suite EXL and no virtual hierarchy is preselected, the design must contain a virtual hierarchy for the Make Cell form to display the options related to virtual hierarchies. If the design is opened in Virtuoso Layout Suite EXL and the Make Cell command is invoked post selection, the selected figGroup must be a virtual hierarchy figGroup. Otherwise, the Make Cell form opens displaying the regular Layout XL options.

Field Description

Library

Specifies the name of the library to be used for creating a new cellview for the selected virtual hierarchy blocks. When the All levels option is selected, the same library is used to create the layout views at all levels as the library of the selected virtual hierarchy.

Cell

Specifies the name of the cell to be used for creating a new cellview for the selected virtual hierarchy blocks. When the All levels option is selected, the cell name used at each level is the same as the name of the corresponding schematic cell.

View

Specifies the name of the view to be created for the virtual hierarchy blocks. If a view name is not specified, the default view name, layout_variant_1, is used. The subsequent view names are then automatically incremented to layout_variant_2, layout_variant_3, and so on.

The layout view name for the new cell should not be a name defined in CPH Global Bindings such as layout, which is a default physical binding in CPH. This helps avoid overriding the physical binding in CPH.

Type

Specifies the type of the cell to be created.

  • softMacro: Creates a soft block type cellview from the virtual hierarchy.
  • none: Creates a custom cell type.
  • digital softMacro: Creates a soft block with hierarchy for a block of type digital.
  • block: Creates hard macros that can be supported by macro placers, Virtuoso Layout Suite XL commands such as Load Physical View, and other applications that support only macros and blocks.

The default is softMacro.

Environment variable: makeCellType

Overwrite layout cellview

Replaces the existing layout with the layout cellview created using selected virtual hierarchies.

Environment variable: makeCellOverwriteLayout

Hierarchy

Specifies if the made cellview replaces the virtual hierarchy clones and all the virtual hierarchies across the design hierarchy.

All clones

Replaces all instances of the selected virtual hierarchy clone with the instances of the new cellview. The option is available only when the selected virtual hierarchy is a clone. Else, the option is grayed out.

If the All clones option is deselected or non-clone virtual hierarchies are selected, the Push options are enabled. In this case, the value of the Push – Into block option is set based on the value of the makeCellPushInBlock environment variable.

Environment variable: makeCellVirtualClones

All levels

Uses the bottom-up approach to create cellviews for all virtual hierarchy levels inside the selected virtual hierarchy and then creates a cellview for the selected virtual hierarchy. For virtual hierarchies at lower levels, which do not already have an area boundary, the Make Cell command automatically creates area boundaries using the default enclosure value. See areaBoundaryEnclosure.

When the Create Pins – On boundary or Create Pins – Congestion aware option is selected, the Make Cell command overrides the current display depth value and sets it to 32 for the selected virtual hierarchy. This ensures that pins for all virtual hierarchies under the selected virtual hierarchy are created on the boundary.

Create Pins

Specifies the options for creating interface pins for the selected virtual hierarchy.

Environment variable: makeCellPinsChoice

Congestion aware

Runs the congestion-aware global router to automatically create pins on the boundary of the virtual hierarchy. Congestion-aware pin creation is recommended for scenarios where an initial placement has already been attempted. Having access to the congestion analysis data before the actual make cell creation can help avoid ANY routing bottlenecks before the actual make cell creation, improving design performance.

By default, pin creation for the new made cell in the Design Planning and Analysis tool is congestion aware. For more information on congestion-aware pin placement, Congestion Analysis Assistant.

Environment variable: makeCellOptPins

On boundary

Creates pins on the boundary of the virtual hierarchy, ensuring the shortest possible net length in the direction of routing. Power and ground pins and any pins that could not be routed are also placed on the boundary.

The creation of pins on or below the virtual hierarchy boundary with the All levels option selected depends on the current Display Depth Options value.

  • If the current display depth is set to 0, only top-level virtual hierarchies have their pins created based on the options selected on the form. Lower-level virtual hierarchies have their pins created below the virtual hierarchy boundary.
  • If the display depth is increased to 1, virtual hierarchies at the top level and at one level below have their pins created using the options selected on the form. Virtual hierarchies further down have their pins created below the boundary.

Pin creation follows the selected pin creation options on the form only for visible virtual hierarchies. Any virtual hierarchies at lower levels that are not set to be displayed have their pins created below the boundary.

Environment variable: makeCellPinsBelow (when set to nil)

Below boundary

Creates pins just below the boundary of the virtual hierarchy.

Environment variable: makeCellPinsBelow (when set to t)

When Below boundary pin creation option is selected, the associated layer-purpose pair drop-down and the Width and Height fields gets enabled and you can specify the appropriate value in each field to use for below boundary pin creation.

Promote pins

Extends pins from lower levels of a virtual hierarchy to a higher level. If no pins are found at the level below, the command goes down to the next level to promote pins to the top.

Width

Specifies the width of the pins to be created.

Height

Specifies the height of the pins to be created.

Label

Specifies if a label needs to be created for the new pin based on the pin creation options specified on the Generate Layout form.

  • None: Creates no label for the new pin.
  • Label: Creates a label for the new pin.
  • Text Display: Creates a label for the new pin in the form of a text display.

Pin labels are supported for all pin creation modes.

Text style

Opens the Virtuoso Layout Suite XL Set Pin Label Text Style form. You can use the options on the form to specify the style to be used for the new pin label or text display.

Delete virtual pins

Deletes any existing virtual pins in the design to allow new pins to be generated.

Environment variable: makeCellDeleteVirtualPins

Push

Controls the Push options during make cell creation.

The Push options are supported only for the selected virtual hierarchy and not for the virtual hierarchies inside the selected virtual hierarchy.

Into block

Pushes the top-level implementation of power structures and signal net routing to the block level. Pushes both metal and poly layers to the block level.

Environment variable: makeCellPushInBlock

Routes as blockages

Pushes the overlapping routes into the made cell as routes or as blockages. Push also pushes overlapping blockages into the cell and Width Spacing Patterns/row regions.

Environment variable: makeCellPushRoutesAsBlockages

For more information, see Push Into Blocks.

Internal routes only

Pushes the internal routes into the made cell, no top-level routes are pushed.

Environment variable: makeCellPushInternalRoutesOnly

Related Topics

Layout Component Generation in Design Planning and Analysis

Congestion Analysis Assistant


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