D

Generating an EAD Technology File

An EAD technology file, named eadTechFile, is a binary encrypted file that contains electrical process parameters for RC extraction, halo distances, capacitance models, and the electromigration rules. While preparing the Layout EAD setup before running parasitic extraction and electromigration checks, you need to specify an EAD technology file in the Process Settings section on the Layout EAD Options form.

Virtuoso provides the eadModelGen executable utility under $CDSHOME/tools/catena/bin in the Virtuoso installation area. You can use this utility to generate an EAD technology file.

You would require a separate EAD technology file for every combination of process technology, layer stack, and process corner.

The following sections provide the details on how to use the eadModelGen utility to create or update an EAD technology file:

Prerequisites

Before running the eadModelGen utility, ensure that the following are available:

A process description file in Cadence-standard text format: You can either provide qrcTechFile or an ICT file that describes all the process parameters required for RC extraction.
If using qrcTechFile, ensure that the file contains the RCGEN models.
If using an ICT file, you can also add rules for electromigration checking to the ICT file using the em_model statements. It is mandatory that the file is provided in the Cadence-standard text format that has been defined in conjunction with various foundries. For details on how to create an ICT file, refer to the EXT Techgen Reference Manual in QRC installation.
A multi-core machine with large RAM: The eadModelGen is a resource-intensive utility, so it is recommended to use a multi-core machine, preferably with more than 16 cores and 64GB of RAM.

Generating an EAD Technology File

To run the eadModelGen utility, run the following command:

$ eadModelGen <ictfilename> | qrcTechFile

The utility reads the specified input ICT file or qrcTechFile to create a technology file and saves it at the current location. The input file is usually an ASCII file in the ICT format that contains the process description, but a binary qrcTechFile may also be used if an ICT file is not available.

For the <ictfilename> argument, you can provide the name of a technology file (ictfile, eadTechfile, or any other custom name) or a symbolic link to a technology file.

If the input file is an ICT file, EAD first looks for eadTechFile in the same directory. If found, loads it to update the content. Otherwise, loads the ICT file.

Depending on your requirements, you can also use one or more of the following optional command-line arguments:

Command-Line Argument	Purpose
-h \| -help	Prints help for the utility
-v \| -version	Prints the tool and library version information
-output_file	Saves the output in a file specified using this argument. If not specified, an output file with the default name, `eadTechFile`, is created.
-log_file	Saves output to the given log file
-dry_run	Displays the run information and options without actually running the command
-threads \| -multi_cpu	Runs the model generation jobs using the given number of threads
-update	Updates the complete ICT file contained in `eadTechFile` with the given ICT file. You cannot update the `eadTechFile` using an ICT-EM file or `emDataFile` that is read only using the EAD Browser.
-update_em `<EM-iRCX-file>`-ircx_file `<RC-iRCX-file>`	Updates an existing `eadTechFile` with EM rules from an `EM iRCX` file. While updating the EM rules, the command looks for matching layer names in the `eadTechFile` and the given `EM iRCX` file. However, when the layer names in these files do not match, you must provide an `RC iRCX` file along with the `EM iRCX` file by using the optional -ircx_file argument. The `RC iRCX` file provides the missing layer mapping information. You cannot update the `eadTechFile` using an ICT-EM file or `emDataFile` that is read only using the EAD Browser. This command-line option updates only an existing EAD technology file. It cannot be used to update a QRC technology file.
-lsf_command	Runs the model generation jobs using LSF. Use this argument to provide a command string that defines how to submit jobs to an LSF queue in your specific LSF environment. For example: -lsf_command "bsub -q lnx64 -m pto_opt -err err -o out " -lsf_number 100 Note that the LSF command must be enclosed in double quotes. You also need to specify the -lsf_number argument. It is also recommended that you use a unique project name (`-P`) when submitting your jobs so that you can easily query the job status later. Depending on the process and the number of conductor layers, the LSF jobs might take a long time to generate models. Therefore, after submitting jobs to the LSF server, the `eadModelGen` command exits. When you find that LSF jobs have completed the run, you must execute the `eadModelGen` command again, with the same options except `-lsf_command` and `-lsf_number`, to compile all the models into a binary technology file. The following example steps show how to generate a technology file: `1. eadModelGen -lsf_command "bsub -q lnx64" -lsf_number 8 ictfile 2. Confirm that all the LSF jobs have completed their runs 3. eadModelGen ictfile` If you want the command to wait for the completion of jobs before exiting, use the -lsf_wait and -lsf_wait_interval options. The eadModelGen command internally uses the `bjobs` command to check the status of the submitted LSF jobs. If `bjobs` fails to return the status of the jobs, the command exits and shows an error message.
-lsf_number	Specifies how many LSF jobs to run in parallel. This argument is used with the -lsf_command argument. For example: -lsf_command "bsub -q lnx64 -m pto_opt -err err -o out " -lsf_number 100 You can use the `-threads` with this argument for multi-threaded execution in LSF.
-lsf_wait	Forces the `eadModelGen` utility to wait until all the LSF jobs have completed and `eadTechFile` has been created. This option prevents the command to exit immediately after running the LSF commands. Note: This argument is useful only when used with -lsf_command and -lsf_wait_interval. If you use this command, you do not need to rerun the `eadmodelGen` utility after completion of LSF jobs.
-lsf_wait_interval `<no-of-seconds>`	Specifies the duration (in seconds) after which the `eadModelGen` utility needs to repetitively check the completion status of LSF jobs. After all the jobs are complete, the `eadModelGen` utility exits. This argument is useful only when specified with -lsf_command and -lsf_wait.
-mail `<email_address>`	Sends an email to the given address after all model generation jobs have completed and the EAD technology file has been created. After receiving the completion mail, you must execute the `eadModelGen` command again, with the same options except `-lsf_command` and `-lsf_number`, to compile all the models into a binary technology file.
-overwrite	Forces overwrite of the existing eadTechFile if one already exists in the output directory.
-split	Splits the components of an existing `eadTechFile` into the given directory
-info	Prints the summary information about the specified ICT file, EAD technology file, or `qrcTechFile`. Provide the complete directory path to the file for which you want to print information.
-comments	Prints the comments embedded in the ICT file in addition to the summary information printed by -info. Use this argument along with `-info`.
-no_cap_models	Creates an `eadTechFile` without capacitance models. The resulting `eadTechFile` can be used only for the R extraction mode, EM checking, and high precision C extraction, but cannot be used for fast C extraction. The time required to generate this partial `eadTechFile` is much less than the time required to create the default file that contains the capacitance models. An efficient way can be to get started using EAD very quickly using this option, that is with the R-only extraction, EM checking, and HPC. In parallel, you can generate the full `eadTechFile` that includes capacitance models too.
-no_load_models	When using an existing eadTechFile, instead of an ICT file, as the input to eadModelGen for model generation, you can specify this option. This will avoid loading the existing capacitance models in the eadTechFile, which will not be used anyway.
-use_ead2dc	Use the native EAD 2D solver instead of the default FEM 2D solver to generate the capacitance models for all the layers. This option may be necessary if model generation fails to complete with the default FEM 2D solver.
-use_ead2dc_for_device_layers	Use the native EAD 2D solver instead of the default FEM 2D solver to generate the capacitance models for the local interconnect and device-level layers. The default FEM 2D solver will be used for all other layers. This option may be necessary if model generation with the FEM 2D solver fails to complete for these layers.
-no_cap_3d_models	Creates an eadTechFile without any 3D correction capacitance models. As a result, EAD will not consider any 3D corner or crossover effects for normal capacitance extraction. However, this does not affect extraction using the High Precision C Solver.
-skip_layer_type	Skips generating capacitance models involving layers of the given type. For example, `diffusion`, `poly`, `lil`, or `metal`.
-lithobias_file	Specifies the lithoBias rules file to be considered for the generation of `eadTechFile`. This file should be in the standard OpenDFM format provided by Si2. The lithoBias rules are added to `eadTechFile`. If the input file for the eadModelGen command is a QRC technology file that contains lithoBias rules, these rules are automatically included in the output `eadTechFile`. You can use the `eadModelGen -info` command to view the names of layers that include lithoBias rules.
-combination_layers	Limits the number of capacitance models to be generated to the set of layer combinations specified by the `combination_layers` section in the ICT file.
-protected_process	Protects the process information in the resulting eadTechFile so that the ICT process description cannot be extracted from the file using the `-split` option.
-max_spacing_factor	Overrides the default halo spacing distance per layer, which is the distance that EAD uses to search for neighboring shapes. Specify a factor to be multiplied by the `min_spacing` value in the ICT file. This option may be necessary in order to generate capacitance models for processes that define a very thick substrate, or thick oxide layers below the first conductor layer.
-max_simulation_widths	Specifies that if the ICT file contains `manual_simulation_points`, use the `simulation_widths` table to define the maximum width per conductor layer. This limits the width ranges used while generating models.
-max_width_file <file-name>	Specifies an optional file that defines the maximum width for each conductor layer in the ICT file. Other than the comments marked with #, each line in the given file should consist of a layer name followed by a maximum width value (in microns). It is required that the maximum width value should be at least 9 times the minimum width value for the given layer.
-status	Returns the status of model generation jobs for the given ICT file.

Important Points to Note

If the eadModelGen utility does not generate an eadTechFile due to some network or disk space issues, you can execute the command again. It will continue to run from the point where it stopped in the previous run.
The time required to generate an eadTechFile with capacitance model depends on the hardware configuration of the computer on which it is running, the number of threads, and the number of layers for which model information is to be generated.
The eadModelGen utility also works with OpenLava, the open-source equivalent of LSF.
An eadTechFile generated using a newer version of Virtuoso is not compatible with an earlier version of Virtuoso.
It is recommended to use -lsf_wait with -lsf_interval in LSF mode to ensure that the eadModelGen command does not exit after submitting the LSF jobs and compiles all the models generated by different jobs into a common eadTechFile.

Example Scenarios of EAD Technology File Generation

This section provides some of the possible example scenarios in which an eadTechFile can be generated with different requirements.

Scenario 1: You need to update an existing eadTechFile with a new ICT file

You can update an existing eadTechFile with a new ICT file only if there is no change in the ICT file that would affect the capacitance models. For example, in cases where the existing eadTechFile does not contain the EM rules, but now you need to include the EM rules added to the ICT file. In this case, do the following:

Change the name of the new ICT file to a name other than ictfile.
Run the eadModelGen utility with this following command:
```
$ eadModelGen -update <new_ict_file_name> eadTechFile
```

Scenario 2: You need to extract all the components contained in the given eadTechFile.

You can do this by executing the following command:

$ eadModelGen -split <tmp_dir> eadTechFile

If you run this command on a protected eadTechFile, the specified directory will contain all the contents of eadTechFile except the ICT File.

The following examples describe how the eadTechFile is split in different cases:

If the eadTechFile was generated for R-only extraction, <tmp_dir> will contain the VHALOS file.
If the eadTechFile was generated for RC extraction, <tmp_dir> will contain VHALOS and all the model files, but not the ICT File.

Scenario 3: You need to protect the process information in the eadTechFile.

You can use the -protected_process command-line argument, as shown below.

$ eadModelGen -protected_process -threads 16 ictfile

If the eadTechFile is protected, it is not possible to extract the ICT file using the -split command-line argument.

Scenario 4: The generation of the complete eadTechFile with capacitance models takes a very long time (a few hours), so you need to generate a partial eadTechFile without capacitance models.

You can do this by executing the following command:

$ eadModelGen -no_cap_models -threads 16 ictfile

Scenario 5: Your ICT file contains an explicit specification of the layer combinations required for model generation in the manual_simulation_combinations section. You need to include only those layer combinations in the eadTechFile instead of automatically generating all the possible layer combinations.

To do this, run the following command to limit the model generation to only the specified layer combinations:

$ eadModelGen -combination_layers -threads 16 ictfile

Scenario 6: You need to verify some details for an existing eadTechFile.

You can do this using the -info command-line argument, as shown below:

$ eadModelGen -info -log_file info.log eadTechFile 
eadModelGen version 7.2.6r910, built 2014/03/31 23:01:34, platform opteron (64bit)
Current time is Tue Apr 01 11:19:49 2014
Loading technology file : eadTechFile
Technology File : ./eadTechFile
Process Name    : cln28hp_1p10m_7x2r_typical
Model version   : 6
Created on      : 2013/08/11 14:39:47
Created by      : eadModelGen version 7.2.6r543 (built 2013/08/05 23:41:52)
Layers          : 23
Diffusion            : 1 (active)
Poly            : 1 (poly)
Conductors      : 10 (M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, C1, C2, B1, B2)
lithoBias       : 0
Vias            : 11 (odCont, polyCont, VIA1, VIA2, VIA3, VIA4, VIA5, VIA6, VIA7, VIA8, VIA9)
EM Models     : 0
Cap models      : 2944

Scenario 7: You have a QRC technology file, which contains a copy of the ICT file (including the EM rules). You need to use this for eadTechFile generation.

In this case, you can run the following command to generate eadTechFile from qrcTechFile:

$ eadModelGen -threads 16 qrcTechFile

Scenario 8: You have an EAD technology file, but the EM rules are missing. You need to update the eadTechFile to include EM rules from an iRCX file.

You can do this by performing the following steps:

Update the EAD technology file using the eadModelGen utility, as shown below.
```
$ eadModelGen -update_em <iRCX file> <eadTechFile>
```
(Optional) Confirm that the EAD technology file has EM models by using the eadModelGen utility, as shown below.
```
$ eadModelGen -info eadTechFile
```

The EM rules get added to the existing eadTechFile in lines beginning with EM models.

Scenario 9: Run eadModelGen with LSF using 200 jobs, wait for the LSF jobs to complete (checking every 10 minutes), and then receive an email when eadTechFile has been created.

You can do this by submitting an LSF command and using the supporting options, as shown below.

eadModelGen -lsf_command "/grid/sfi/farm/bin/bsub -P EAD:6.1.8:RD:gpdk090 -R
2015_lnx86_test -W 48:00 -q lnx64" -lsf_number 200 -lsf_wait -lsf_wait_interval
600 -mail abc@mailaddress.com ictfile

The LSF command string will depend on your specific LSF installation. It is recommended to use a unique project name (-P) when submitting your jobs so that you can query the job status later using that name. In the above example command, a project name has been provided using -P. You can query its status as shown below.

$ bjobs -P EAD:6.1.8:RD:gpdk090

Updating an EAD Technology File

As the foundries update the ICT and processes on a regular basis, you might also need to update the EAD models in the eadTechFile. For this, you can use the -update command-line argument to update the eadTechFile without regenerating the capacitance models.

Some examples of changes in ICT that do require generation of new EAD models are given below.

When there is a change in parameters that affect the capacitance, including layer heights, thickness, widths, spacings, bias (top/bottom enlargement), WEE tables, dielectrics, layout scaling.
When a new eadTechFile will need to be generated.

You might also need to update the eadTechFile if some modeling improvements have been done.

Some examples of changes in ICT that do not require generation of new EAD models are given below.

Changes to the sub_conductor device layers. This is because currently, EAD does not use these layers.
Changes to resistance parameters, for example, rho tables, and wire_edge_enlargement_r.
Addition or changes in the EM rules

After upgrading Virtuoso, you need not update or regenerate the eadTechFile because it is backward compatible.

EM Rule Support in EAD

This section lists the differences between EM rules supported in EAD and Voltus-Fi:

The EM parameter em_recover is supported by the parser but it is not used during EM analysis.
The following operators are supported in lowercase in EAD:
- sqrt
- log
- exp
- abs
- min
- max
- normsinv
- * / + -
- ()
- e
- ^
- expr1?expr2: expr3

Voltus-Fi-XL supports parameters for only limit-based EM analysis. The following parameters can be used to specify EM rules in the ICT EM file. The EM rules might also be embedded in the ICT file or the qrcTechFile.

Parameter Name	Description
`em_vcwidth <`value`>`	Optional parameter for `via` layers that defines the minimum size via that is used by the software to identify single square via. This parameter is similar to the `viaWidthList` parameter in `emDataFile`.
`em_W_n`	Optional parameter that specifies the wire width in microns below which a line is considered narrow. All lines are considered wide unless you specify otherwise using this parameter It helps to select the rule between `em_jmax__w` and `em_jmax__n`. If `w < em_W_n` , then `em_jmax__n` is selected, otherwise `em_jmax__w` selected.
`em_jmax_dc_rms_metal_line_factor`	Defines the relationship between the value of power on metal lines and the `Irms` rating values for DC RMS analysis.
`em_jmax_ac_rms_metal_line_factor`	Defines the relationship between the value of power on metal lines and the `Irms` rating values for AC RMS analysis.
`em_ac_rms_context_aware_pitch_num`	Context-aware relaxation keyword. Specifies the pitch count values for RMS relaxation for AC RMS analysis in the context-aware RMS Relaxation flow. For example, `em_ac_rms_context_aware_pitch_num 5` The context-aware RMS Relaxation flow is foundry-specific. For more information, contact your Cadence representative.
`em_dc_rms_context_aware_pitch_num`	Context-aware relaxation keyword. Specifies the pitch count values for RMS relaxation for DC RMS analysis in the context-aware RMS Relaxation flow. For example, `em_dc_rms_context_aware_pitch_num 5` The context-aware RMS Relaxation flow is foundry-specific. For more information, contact your Cadence representative.
`em_jmax_ac_rms_context_aware_factor`	Additional factor to be multiplied for EM limits to take into consideration the context-aware RMS relaxation flow. For example, `em_jmax_ac_rms_context_aware_factor 1.5 srms_0>= 0.008 srms_1> 0.0004` Where, `srms_0` is the worst `srms` value in the neighboring area within the context-aware region of the parasitic. `srms_1` is the second worst `srms` value in the neighboring area within the context-aware region of the parasitic. The context-aware RMS Relaxation flow is foundry-specific. For more information, contact your Cadence representative.
`em_jmax_dc_rms_context_aware_factor`	Specifies the benefit factor for RMS relaxation for DC RMS analysis in the context-aware RMS Relaxation flow. Additional factor to be multiplied for EM limits to take into consideration the context-aware RMS relaxation flow. For example, `em_jmax_dc_rms_context_aware_factor 1.5 srms_0>= 0.008 srms_1> 0.0004` Where, `srms_0` is the worst `srms` value in the neighboring area within the context-aware region of the parasitic. `srms_1` is the second worst `srms` value in the neighboring area within the context-aware region of the parasitic. The context-aware RMS Relaxation flow is foundry-specific. For more information, contact your Cadence representative.
`em_segment_length`	A process definition parameter that determines how to calculate the length of a wire segment. This parameter determines whether the segment length is of the type perimeter, centerline, or total. The difference between the different length types is as follows: `perimeter`: specifies that the length calculation is along the wire’s outer edge boundary. This value is used for 28nm process nodes. `centerline`: specifies that the length is extended to the edge of the segment along the centerline path. This value is used for 20nm process nodes. `total`: specifies that the segment length is calculated by adding the path lengths of all the resistors in the segment.
em_recover	This parameter is supported in the parser and in the EM process, but it is not used during EM analysis. Optional parameter that specifies the recovery factor used for calculating the average current density with recovery. You can set the recovery factor to -1.0 when you want to account for the average of the absolute current (avg(abs(current))) so that the negative current does not cancel the positive current values in arriving at the average current result. Default: 1 Range: A positive integer or floating point number

Current Density (JMAX) Keywords

The table below lists the Current Density (JMAX) keywords that can be specified in the ICT EM file.

Keyword	Description
`em_jmax_dc_avg*`	Optional keyword that specifies the DC AVG analysis.
`em_jmax_ac_avg*`	Optional keyword that specifies the AC AVG analysis.
`em_jmax_dc_peak*`	Optional keyword that specifies DC PEAK analysis.
`em_jmax_ac_peak*`	Optional keyword that specifies AC_PEAK analysis.
`em_jmax_dc_rms*`	Optional keyword that specifies DC RMS analysis.
`em_jmax_ac_rms*`	Optional keyword that specifies AC RMS analysis.
`em_jmax_ac_rec`	Optional keyword that specifies the maximum recovery AC current analysis.

Where star ‘*’ implies that ‘_w’ and ‘_n’ rules are also supported.

For example,

em_jmax_ac_peak_w is an optional parameter that is essentially the same as em_jmax_ac_peak, with the exception that it is specified for wide wires (as defined by em_W_n).
em_jmax_ac_peak_n is an optional parameter that is essentially the same as em_jmax_ac_peak, with the exception that it is specified for narrow wires (as defined by em_W_n).

Rules for Defining EM Parameters

An example of the EM rule for defining the em_jmax_dc_avg parameter is provided below:

[em_jmax_dc_avg <value> | <value_1> <area_1/width_1> [...] | EQU <fn(E)>]

[jmax_factor <temp1> <scale1> [<temp2> <scale2> ...]]

[jmax_life <life1> <scale1> [<life2> <scale2>.......]]

[current_direction up | down | both]

[conditions]

[single]

[power_rail/power_grid    ]

[priority==<priority no.>]

[device==”<device model names>”]

[sub_conductor=="<subconductor names>"]

[color=="<list of color no.>"]

[mask==<mask no.>]

[via_range <value>]

All other EM parameters are defined with the same structure but apply to different characteristics of the em_model (peak current versus average for instance). The following rules apply to all the limit-based em_model parameters:

Single Value Current Density
Specifying a single value or an equation is an enhancement for width or area dependent parameters (such as em_jmax_ac_avg).
For narrow/wide wire parameters (such as em_jmax_ac_avg_n or em_jmax_ac_avg_w) you can only specify a single value. It will not accept either a PWL table or an equation.
Piece-wise Linear (PWL) Interpolation
In a width-dependent model for a conductor layer, or for an area-dependent model for a via layer, PWL interpolation uses a series of data points that are points on a graph of X versus Y, where X can be either a value or an expression and Y is a value. For example, current density value and area <value1> <area1>, current density value and width <value1> <width1>, current density expression and area <expression1> <area1>, or current density expression and width <expression1> <width1>.
The following syntax are supported:
```
em_jmax_dc_avg PWL <value1> <area1/width1> <value2> <area1/width1>
```
```
em_jmax_dc_avg PWL (<value1> <area1/width1> <value2> <area1/width1>)
```
```
em_jmax_dc_avg PWL (<expression1> <area1/width1> <expression2> < area1/width1>)
```
For example:
```
em_jmax_dc_avg PWL 0.3582 0.001444 0.5694 0.003364 0.7164 0.0038
```
```
em_jmax_dc_avg PWL (0.3582 0.001444 0.5694 0.003364 0.7164 0.0038)
```
```
em_jmax_dc_avg PWL (0.05*0.5 0.002 0.1*0.5 0.004 0.2*0.5 0.008)
```
Equations in EM Model
The EQU keyword denotes the definition of an equation for current density.
An EOL or one of the qualifiers (jmax_factor, current_direction,or single) marks the end of an equation specifying the Current Density limit. If the equation resolves into two separate equations, then this will result in an error.
For EQU, the following operators (case-sensitive) are supported:
- sqrt
- log
- exp
- abs
- min
- max
- normsinv
- * / + -
- ()
- e
- ^
- expr1? expr2: expr3
Where, expr1 is a conditional expression. If expr1 evaluates to true, then expr2 is evaluated, else expr3 is evaluated.
For example:
Life_factor= ((A < 5 and B > 2)? 3:4)
em_jmax_dc_avg EQU 3.0*w * Life_factor jmax_factor 50 1.1 110 1.0 125 0.92 L > 5
Square brackets ‘[]’ are not supported. A comma ‘,’ implies multiple equations, and results in an error. The period ‘.’ is ambiguous and should not be used to indicate multiplication (use * instead).
Spaces are permitted to make an equation more readable.
Variables within equations, such as deltaT, w, and l, are populated by the analysis tool at runtime. Use the em_variables parameter in the process definition to globally declare variables that are used within the various em_models.
The equation definition ends when reaching the end of line (EOL) or another keyword like:
The equation definition ends when reaching the end of line (EOL) or another keyword like:
- /* Limit-based EM equations (EQU), terminated by any of the following:
- // EOL
- // jmax_factor
- // jcdf_factor
- // rating_factor
- // current_direction
- // single
- // power_rail
- // power_grid
- // priority
- // mask
- // color
- // VO_
- // Itolerance
- // via_range
- // jmax_life
- // conditions [L/W/Lu/Wu/Lb/Wb/Lv2v/Wv/Lv/Vg/N/a == | < | <= | > | >= <value>
- // device
- // sub_conductor
- // sub_via
- // bridge_via
- // MD_AND_OD_OVERLAPPING_REGION
- // Sh
- // hi_em
- // em_ (the next em_ rule)
- // } (the end of the model)
List of supported variables are provided below:
- a: area of the resistor
- w: width
- l: length
- La: length of pseudo via
- La_x: length of pseudo via along the x-axis
- La_y: length of pseudo via along the y-axis
- N: number of vias
- deltaT: rise in temperature in degree Celsius
- r: duty ratio
- Tref: refers to em_tref, the nominal temperature for EM analysis defined in the process section of the ICT file. If em_tref is not defined, then default value(110C) is set.
- cdf_percentage: This variable lets you use the value specified using the keyword cdf_percentage in the emir config file or command file, in the EM rules.
Order Dependency
The actual Current Density limit (value, piece-wise linear or PWL pairs, or equation) should follow immediately after the Current Density keyword (em_jmax_dc_avg). Any of the qualifiers (jmax_factor, current_direction, or single) will come after that. The order of the qualifiers is not important.
Units of Values
The unit should be specified in accordance with the setting defined by the em_conductor_unit, em_via_unit, and em_via_area_unit parameters defined in the process definition. Units are specified as:
- For a single value or an equation:
  - A/cm² or mA for metal layers (width based)
  - A/via or mA for via layers (per via)
- For a PWL table:
  - A/cm² or mA, with width specified in microns for metal layers
  - A/cm² or mA, with area specified in square microns for via layers
JMAX Factor
jmax_factor <temp1> <scale1> [<temp2> <scale2> ...]
jmax_factor is the optional scaling factor to use at different temperatures compared to the reference temperature (defined by em_tref in the process definition). The temperature for jmax_factor should be specified in degrees Celsius.
Scaling factor is a positive integer: >1 to scale up, <1 to scale down, or 1 for no scale effect.
If the specified temperature, T, falls between the defined minimum and maximum temperatures, the software will calculate a new scale factor (RT) using the formula, TTF=A*J^(-n)*exp(Ea/kT).
For example:
```
RT = RT1*exp((Ea/kT)*(1/T-1/T1))
```
where
```
Ea/kT=(T1*T2/(T1-T2))*ln(RT2/RT1)
```
Format of the Conditions
Condition = [L/W/Lu/Wu/Lb/Wb/Lv2v/Sv/Td/r/a/N < | <= | > | >= | == | != <value in microns/micro seconds> | ground_net | supply_net | Vu_current_direction {up | down}] | [Itolerance < | <= | > | >= | == | != <value in percentage> ]
Conditions = [condition]*
The L parameter specifies the length-based jmax values in microns.
The W parameter specifies the width-based jmax values in microns.
L and W are applicable for both metals and vias.
Lu, Lb, Wu, and Wb are applicable for vias only.
Lv2v and Itolerance are applicable only for the power_rail rule. Itolerance is not supported in EAD and will be ignored.
Where,
L = length W = Width Lu = Upper metal length Lb = Bottom metal length Wu = Upper metal width Wb = Lower metal width Lv2v = Distance between terminal vias Itolerance = Difference in the current values of terminal vias. For example, if a difference of up to 5 percent is acceptable, then specify 'Itolerance <= 0.05'. Td= Time duration in micro second or total ‘On Time” period r = Duty ratio a = Area of the single cut in the via or in the via array N = Number of vias in the via array
Voltus-Fi-XL supports metal length/width rules above and below vias, where, the dimensions to be checked for the rules are different for the metal above and the metal below. In this case, Lu/Wu refers to dimensions of the metal above the via and Lb/Wb refers to dimensions of the metal below the via.

Single
The keyword, single can be specified to differentiate between a single square cut via and square viaarray. The following example shows how to use the single keyword:

em_jmax_dc_avg PWL 0.022  0.01  jmax_factor 105 1.1  110 1.0 115

0.9 120 0.8 125 0.7 130 0.6 140 0.5 150 0.4  current_direction up

Lb > 4 Wb >= 0.05  current_direction up single

JMAX Life
The keyword, jmax_life provides the ability to set the scaling factor that applies to the Current Density limits for different lifetimes. The syntax is as follows:
```
jmax_life <life1> <scale1> [<life2> <scale2>.......]
```
The software will take the unit of lifetime from the em_lifetime_units parameter specified in the process section of the ICT file. In case the specified life value does not match any of the life values provided using jmax_life, the software performs linear interpolation to calculate the Tlife factor.
Current Direction
current_direction [up | down | both] can be specified for via current direction. The syntax of current_direction is:
- up - means the direction of the current is from bottom to top and specifies to use the length and width of the metal below Lb/Wb for the VIA Jmax factor
- down - means the direction of the current is from top to bottom and specifies to use the length and width of the metal above Lu/Wu for VIA Jmax factor
- both - This rule is applicable only when the direction of the current is uncertain. This rule is unlikely to be applied since the software calculates the current direction
Power Rail/Power Grid
The keyword power_rail or power_grid can be specified to enable the particular EM rule for power-rail analysis. These rules are not supported in EAD and will be ignored during parsing.
ApplyR
The keyword is not supported in EAD EM.
Priority
These rules are not supported in EAD and will be ignored during parsing.
Device
This keyword is used to specify different EM rules for device resistors, which are subsets of other layers. The syntax is as follows:
```
device=="device model names"
```
For example, the following keyword specifies that the particular EM rule is applicable only to device with the model names, “devRA devRB”.
```
device=="devRA devRB"
```
Subconductor
This keyword is used to specify different EM rules for subconductors, which are subsets of poly or other layers. The syntax is as follows:
sub_conductor=="subconductor names"
For example, the following keyword specifies that the particular EM rule is applicable only to subconductor layers, pploy and gpoly.
sub_conductor=="ppoly gpoly"
bridge_via
This keyword is used to specify that the particular EM rule will apply only to bridge vias.
Color
This keyword is used to specify that the particular EM rule is applicable only to the resistor with the specified color number.
For example,
color==”2 4 5” specifies that the particular EM rule is applicable only to the resistor with property, $M=2 OR $M=4 OR $M=5.
Masks
This keyword is used to specify that the particular EM rule is applicable only to the resistor with the specified mask number.
For example,
mask==2 specifies that the particular EM rule is applicable only to the resistor with property, $M=2.

Rules for Specifying Via Area

You can specify PWL in either one of the following ways:

Provide PWL for a specific area:

em_jmax_* PWL Value_1 area_1 … Value_N areaN

For example,

em_jmax_* PWL 1.3 2.0 1.7 3.0

Provide PWL for a specified area range:

em_jmax_* EQU <equation with 'a'> conditions

For example,

em_jmax_* EQU (1.3 * a)/2.0  a>=0.0 a<2.5

em_jmax_* EQU (1.7 * a)/3.0  a>=2.5 N>=3

em_jmax_* EQU (1.9 * a)/3.0  a>=2.5 N<3

EM Rule Selection Priority

This section details the order of priority in which the EM rules are applied by Voltus-Fi-XL based on the specified keywords. The order of priority of keywords in descending order is provided below:

device --> highest priority
sub_conductor
bridge_via
priority
power_grid/power_rail
color
mask
current_direction
Conditions
Area matching in case of PWL
Base rule
Optimistic/pessimistic rules --> lowest priority

These are detailed below.

device
When a device is specified in the EM rule file, the software first looks for the device keyword and applies the EM rules to the specified device.
For example, for a device with model name, devRA, if the following rules are specified in the ICT file:
```
1. em_jmax* …   device==“devRA”
```
```
2. em_jmax* …   device==“devRB”
```
```
3. em_jmax* …
```
Then the software follows the order of priority provided below:
- Match rule 1 because it has a matching device keyword
- Match rule 3 if rule 1 does not match
- Skip rule 2 because it is for device, devRB
- KPNS: CCMPR02674181
sub_conductor
When a sub conductor is specified in the EM rule file, the software first looks for the sub_conductor keyword and applies the EM rules to the specified sub conductor.
For example, for a resistor on layer, ppoly, if the following rules are specified in the ICT file:
```
1. em_jmax* …   sub_conductor==“ppoly”
```
```
2. em_jmax* …   sub_conductor==“gpoly”
```
```
3. em_jmax* …
```
Then the software follows the order of priority provided below:
- Match rule 1 because it has a matching sub_conductor keyword
- Match rule 3 if rule 1 does not match
- Skip rule 2 because it is for sub conductor, gpoly
- KPNS: CCMPR02674181
bridge_via
When a bridge_via is specified in the EM rule file, the software first looks for the bridge_via keyword and applies the EM rules having bridge_via keyword for the bridge via. In case, the via is not bridge via, rules having bridge_via keyword will be ignored.
For example, for a bridge via, if the following rules are specified in the ICT file:
```
1. em_jmax* … bridge_via
```
```
2. em_jmax* … 
```
Then the software follows the order of priority provided below:
- Match rule 1 because it is a bridge via
- Match rule 2 if rule 1 does not match
In case, the via is not bridge via, then the software will match rule 2.
priority
This keyword is not supported in EAD.
power_rail/power_grid
This keyword is not supported in EAD.
color
When the color keyword is specified in the EM rule file, in the following manner:
```
1. em_jmax* …   color==”1 3 5” 
```
```
2. em_jmax* …
```
For example, if a resistor has color number 5, specified using $M=5, then the software follows the order of priority provided below:
- Match rule 1 for the specified color number
- Match rule 2 if rule 1 does not match
mask
When the mask keyword is specified in the EM rule file, in the following manner:
```
1. em_jmax* …   mask==2 
```
```
2. em_jmax* …
```
For example, if a resistor has mask number 2, specified using $M=2, then the software follows the order of priority provided below:
- Match rule 1 for the specified mask number
- Match rule 2 if rule 1 does not match
current_direction
When the current_direction keyword is specified in the EM rule file, in the following manner:
```
1. em_jmax* …   current_direction up
```
```
2. em_jmax* …   current_direction down
```
```
3. em_jmax* …
```
Then, for a resistor with current_direction up, the software follows the order of priority provided below:
- Match rule 1 because it has a matching current_direction keyword
- Match rule 3 if rule 1 does not match
- Skip rule 2 because the current direction is not matching
Conditions
When conditions are specified in the EM rule file, in the following manner:
```
1. em_jmax* …   L <=5
```
```
2. em_jmax  …   L > 5
```
```
3. em_jmax* …
```
Then the software follows the order of priority provided below:
- Match rules 1 and 2 because conditions are specified
- Match rule 3 if rules 1 and 2 are not matching
Area Matching from the PWL
When the PWL for specific via areas are specified in the EM rule file, in the following manner:
```
1. em_jmax* …   PWL VAL_1   AREA_1   VAL_2   AREA_2    L <=5 
```
```
2. em_jmax  …   PWL VAL_3   AREA_3   VAL_4   AREA_4   L <=5
```
Then the software follows the order of priority provided below:
- Match the exact areas provided in the rule file
- The software does not interpolate for unmatched areas (other than AREA_1, AREA_2, AREA_3, and AREA_4 in above example)
Base Rule Selection
When the PWL for specific via area is specified in the EM rule file, without any conditions in the following manner:
```
em_jmax* …   PWL VAL_1   AREA_1   VAL_2   AREA_2 
```
Then the software follows the order of priority provided below:
- Match the exact areas from the base rule
- The software does not interpolate for unmatched areas (other than AREA_1 and AREA_2 in above example)
When multiple rules match for a conductor/via, then maximum/minimum amongst them is returned depending upon the environment variable layoutEAD.em useMaxRule.

For more information about EM rules, see Voltus-Fi Custom Power Integrity Solution L User Guide and Voltus-Fi Custom Power Integrity Solution XL User Guide.

Solvers for Generation of Capacitance Models

eadModelGen can use different solvers for capacitance model generation. Each solver has its own advantages and limitations. Depending on your accuracy requirements, choose a solver by using appropriate command options.

The solvers available for capacitance model generation are listed below:

FEM 2D solver: Finite Element Method (FEM) 2D solver it is the default solver. It runs model generation on regular interconnect Back End of the Line (BEOL) layers. The BEOL is the second part of IC fabrication where the individual devices get interconnected with the wiring on the wafer. Both contribute towards the maximum rise in temperature that causes the self-heating effect.
The FEM 2D solver provides the best performance on the BEOL layers in the layer stack with high accuracy. It works best on those BEOL layers that are within some range of typical conductor dimensions for the given process. In general, for these types of BEOL layers, FEM 2D is much faster than EAD 2D with virtually the same accuracy, but in some cases, the performance might not be so good. Some of those cases are listed below:
- For the top layers in the stack, also referred to as RDL layers, which are very thick or wide relative to the other layers in the stack, and are typically used for global power or ground distribution. In FEM 2D, the entire process layer stack is meshed for solving, so these very thick and wide layers can result in a very large mesh, which may consume a large amount of memory and increase the time to solve. In extreme cases, FEM 2D can actually be slower than EAD 2D on these layers.
- For the very thin layers. For example, the highly resistive RH_TN layers in the MEOL. These layers require using a very small mesh unit size. The presence of these very thin layers can result in a finer, and therefore, larger mesh for the layer stack, which increases the amount of memory required and decreases the performance.
EAD 2D solver: Runs model generation for most layers, including the regular interconnect (BEOL) layers down to the device and local interconnect Front End of Line (FEOL) and Middle End of Line (MEOL) layers. FEOL is the first part of IC fabrication where the individual devices such as transistors, capacitors, and resistors are patterned in the semiconductor. FEOL covers everything up to, but not including, the deposition of metal interconnect layers. MEOL, which is also called as MOL, comprises contacts that connect the separate transistor and interconnect pieces.
EAD 2D provides a good balance of speed and accuracy. Unlike FEM 2D, the EAD 2D solver does not mesh the interior of the conductors. It only meshes the boundaries of the conductors and the dielectrics in between them. Therefore, it is not susceptible to the same issues that FEM 2D has when there are large variations in the conductor widths or thicknesses. In general, it is slower than FEM 2D.

On some processes, particularly for the FEOL and MEOL layers, the default FEM 2D solver may not provide the best option for accuracy. In such cases, you can run the EAD 2D solver by using the -use_ead2dc command-line option. You can also run a hybrid mix of these solvers by using the -use_ead2dc_for_device_layers command-line option. With this option, EAD automatically runs the EAD 2D solver for any models involving FEOL or MEOL layers, and invokes the default solver for the BEOL layers.

Guidelines for Using a Solver

It is recommended to use FEM 2D in general.
Use EAD 2D only on those layers that either require higher accuracy (at the expense of speed), or for which FEM 2D shows performance issues.
Use EAD 2D only for specific layers, not for all layers. For example, the very thin or thick layers for which FEM 2D shows performance issues. Specify the layer names using the -use_ead2dc_for_device_layers option. eadModelGen always picks up where it left, so you can run EAD 2D for selected layers, and then run it using FEM 2D to complete the remaining models.

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Virtuoso Electrically Aware Design Flow GuideProduct Version IC23.1, November 2023

D

Generating an EAD Technology File

Prerequisites

Generating an EAD Technology File

Important Points to Note

Example Scenarios of EAD Technology File Generation

Updating an EAD Technology File

EM Rule Support in EAD

Current Density (JMAX) Keywords

Rules for Defining EM Parameters

Rules for Specifying Via Area

EM Rule Selection Priority

Solvers for Generation of Capacitance Models

Guidelines for Using a Solver

Virtuoso Electrically Aware Design Flow Guide
Product Version IC23.1, November 2023