A
Nodal Analysis
This appendix briefly introduces Kirchhoff’s Laws and describes how the simulator uses them to simulate an analog system. For information, see
Kirchhoff’s Laws
Simulation of the analog content of Verilog®-AMS language modules is based on two sets of relationships. The first set, called the constitutive relationships, consists of formulas that describe the behavior of each component. Some formulas are supplied as built-in primitives. You provide other formulas in the form of module definitions.
The second set of relationships, the interconnection relationships, describes the structure of the network. This set, which contains information on how the nodes of the components are connected, is independent of the behavior of the constituent components. Kirchhoff’s laws provide the following properties relating the quantities present on the nodes and on the branches that connect the nodes.
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Kirchhoff’s Flow Law
The algebraic sum of all the flows out of a node at any instant is zero. -
Kirchhoff’s Potential Law
The algebraic sum of all the branch potentials around a loop at any instant is zero.
These laws assume that a node is infinitely small so that there is negligible difference in potential between any two points on the node and a negligible accumulation of flow.
Simulating an Analog System
To describe an analog network, simulators combine constitutive relationships with Kirchhoff’s laws in nodal analysis to form a system of differential-algebraic equations of the form
These equations are a restatement of Kirchhoff’s Flow Law.
v is a vector containing all node potentials.
q and i are the dynamic and static portions of the flow.
f is a vector containing the total flow out of each node.
v0 is the vector of initial conditions.
Transient Analysis
The equation describing the network is differential and nonlinear, which makes it impossible to solve directly. There are a number of different approaches to solving this problem numerically. However, all approaches break time into increments and solve the nonlinear equations iteratively.
The simulator replaces the time derivative operator (dq/dt) with a discrete-time finite difference approximation. The simulation time interval is discretized and solved at individual time points along the interval. The simulator controls the interval between the time points to ensure the accuracy of the finite difference approximation. At each time point, the simulator solves iteratively a system of nonlinear algebraic equations. Like most circuit simulators, the AMS Designer simulator uses the Newton-Raphson method to solve this system.
Convergence
In Verilog-AMS, the analog behavioral description is evaluated iteratively until the Newton-Raphson method converges. (For a graphical representation of this process, see “Simulator Flow for Analog Systems”.) On the first iteration, the signal values used in Verilog-AMS expressions are approximate and do not satisfy Kirchhoff’s laws.
In fact, the initial values might not be reasonable; so you must write models that do something reasonable even when given unreasonable signal values.
For example, if you compute the log or square root of a signal value, some signal values cause the arguments to these functions to become negative, even though a real-world system never exhibits negative values.
As the iteration progresses, the signal values approach the solution. Iteration continues until two convergence criteria are satisfied. The first criterion is that the proposed solution on this iteration,
where reltol is the relative tolerance and abstol is the absolute tolerance.
reltol is set as a simulator option and typically has a value of 0.001. There can be many absolute tolerances, and which one is used depends on the resolved discipline of the net. You set absolute tolerances by specifying the abstol attribute for the natures you use. The absolute tolerance is important when vn is converging to zero. Without abstol, the iteration never converges.
The second criterion ensures that Kirchhoff’s Flow Law is satisfied:
where fni(v(j)) is the flow exiting node n from branch i.
Both of these criteria specify the absolute tolerance to ensure that convergence is not precluded when vn or fn(v).scs) to work effectively on any node in the circuit, you must scale the absolute tolerance appropriately for the associated branches. Set the absolute tolerance to be the largest value that is negligible on all the branches with which it is associated.
The simulator uses absolute tolerance to get an idea of the scale of signals. Absolute tolerances are typically 1,000 to 1,000,000 times smaller than the largest typical value for signals of a particular quantity. For example, in a typical integrated circuit, the largest potential is about 5 volts; so the default absolute tolerance for voltage is 1 μV. The largest current is about 1 mA; so the default absolute tolerance for current is 1 pA.
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