Customization of Verilog In Defaults Using the .cdsenv File
In addition to these parameters, Verilog In provides some other parameters that you can use while importing Verilog designs. These parameters can be used to customize the default behavior of Verilog In using the corresponding environment variables. These variables are specified in the .cdsenv file, which can be accessed from the following path:
inst_dir/tools/dfII/etc/tools/ihdl/.cdsenv
The following table shows some of the entries in the .cdsenv file:
|
Tool Name
|
Environment Variable Name
|
Type
|
value
|
Range
|
|
ihdl
|
pin_master_basic_lib
|
boolean
|
|
nil
|
|
ihdl
|
pin_master_cells
|
string
|
ipin opin iopin
|
|
|
ihdl
|
searchInReflib
|
boolean
|
t
|
nil
|
|
ihdl
|
maxNetNameLength
|
int
|
8000
|
nil
|
|
ihdl
|
createFileLink
|
boolean
|
t
|
nil
|
|
ihdl
|
prefix_internal_net_name
|
string
|
" "
|
nil
|
|
ihdl
|
refSchList
|
string
|
" "
|
nil
|
|
ihdl
|
pnrMaxInst
|
int
|
20000
|
nil
|
|
ihdl
|
pnrMaxPort
|
int
|
5000
|
nil
|
The following table describes the parameters that correspond to the environment variables available in the.cdsenv file:
|
Parameter
|
Description
|
|
search_in_reflib
|
Determines whether to search the cells in the target and reference libraries before the cells are created. The search_in_reflib parameter can have either of the following values:
-
1: Indicates that before creating the cells, these are searched in the target and reference libraries. -
0: Indicates that the cells are not searched in the target and reference libraries before the cells are created.
The default value of the search_in_reflib parameter is 1. For more information, see Target Library Name and Reference Libraries.
If both the search_in_reflib and import_if_exits parameters are set to 0, the cells are searched only in the target library and are created if these do not exist.
|
|
max_net_name_length
|
Specifies the maximum number of characters a net name can contain. The net name can contain the 8000 characters by default. A warning is generated if the number of characters in a net name exceeds 8000.
If the net name exceeds the number of characters you specify, the string is divided into multiple chunks. A shorter alias name is associated with each chunk. The maximum number of characters a chunk can contain is equal to the value of the maxNetNameLength variable. To obtain the complete net name, combine the different alias names.
|
|
create_file_link
|
If the value of this variable is nonzero, sets a soft link to the Verilog source file from which the Verilog design was imported into a functional view.
The create_file_link parameter can have either of the following values:
-
0: Indicates that no pointer is set to the Verilog source file. -
1: Indicates that a pointer is set to the Verilog source file.
The default value of the create_file_link parameter is 0.
|
|
prefix_internal_net_name
|
Specifies the prefix string for internal net names.
In the schematic view, the default internal net name is NeTt_<index>and in the netlist view, the net names are _LoNgNeTnAmE<index> and _NeTt_<index>. However, when you generate a netlist from a design for which net names have leading underscores, the net names are escaped and require explicit name mapping. To avoid escaping net names and creating name maps, you can set the prefix_internal_net_name variable as follows:
In CIW:
envSetVal("ihdl" "prefix_internal_net_name" 'string "myprefix")
In the .cdsenv file:
"ihdl" "prefix_internal_net_name" 'string "myprefix" nil
Setting this environment variable in the schematic view displays the net name as follows:
myprefix_n_e_t_<index>
Setting this environment variable in the netlist view displays the net name as follows:
myprefix_l_o_n_g_n_e_t_n_a_m_e_<index> and
myprefix_n_e_t_<index>
If you want to use the default net names, set the prefix argument (myprefix) in the envSetVal function to " ".
|
Related Topics
Target Library Name
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