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Verilog In with Verilog 2001 Support

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This topic explains the Verilog 2001 constructs for which Verilog In can create schematics. Verilog In supports Verilog IEEE 1364-2001 constructs. For other constructs, it does not create a schematic.

The ncvlog parser used by Verilog In supports the Verilog IEEE 1364-2001 constructs. The ncvlog parser version 08.20 is built into the DFII hierarchy. If you want to use a higher version of this parser from the IUS hierarchy, you can set the path as follows:

set path =($path <IUS_BASE>/tools/bin )

setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH}: 'cds_root ncvlog'/tools/inca/lib

Verilog In supports the following Verilog 2001 constructs:

• Signed Arithmetic
• Sized and Typed Parameters and Local Parameters
• Attributes in HDL Source
• Inherited Connections
• Named Parameter Assignment
• ANSI-C Style Port Declarations
• Combined Port and Type Declaration
• Indexed Part Selects
• Power Operator and Arithmetic Shift Operator

Signed Arithmetic

As per the Verilog IEEE 1364-1995 standard, the integer data type was signed while the reg and net data types were unsigned. The Verilog IEEE 1364-2001 standard has been enhanced to provide greater signed arithmetic capability, such as declaring signed reg and net data types.

The Verilog IEEE 1364-2001 standard uses the signed keyword to declare the reg and net data types, ports, and functions as signed data types as follows:

wire signed [7:0] vector;

input signed [7:0] a;

To support signed net and port data types, a new boolean property, verilogSignedDataType, has been added by Verilog In. You can specify whether the net or port is signed or unsigned in the schematic or symbol view created by Verilog In. For example, consider that you have the following statement in the netlist:

wire signed [7:0] vector;

In such a case, Verilog In attaches the verilogSignedDataType = t property to the wire object.

Sized and Typed Parameters and Local Parameters

As per the Verilog IEEE 1364-2001 standard, you can explicitly declare the data type and size of parameters instead of determining these properties from the parameter value as shown below.

parameter verilog mux_selector = 0;

Traditionally, Verilog parameters are stored as simple name-value pairs under the hierarchical instance property, verilog. If the size and type are specified explicitly for a parameter then the name-value pair is modified to a name-list pair as follows:

paramName1 = (”vin2001” ”param” signed type range value)

The following list describes various components of a name-list pair:

• vin2001 indicates that the property was imported by Verilog In under support of the Verilog 2001 constructs
• param indicates that this is a parameter
• signed specifies the value 1 for signed or 0 for unsigned
• type specifies any Verilog supported data type
• range indicates the range in the lsb or msb format
• value specifies the value of the parameter

The Verilog IEEE 1364-2001 standard also introduces a new type of module parameter called local parameter. A local parameter is similar to a parameter, except that it cannot be modified using a defparam statement or by ordered or named parameter value assignments in a module instance statement. Local parameters are declared using the localparam keyword as follows:

localparam signed [3:0] mux_selector = 0;

The format for specifying local parameters is similar to the parameter format except that the second value is localparam as follows:

paramName1 = (”vin2001” ”localparam” signed type range value)

Attributes in HDL Source

The Verilog IEEE 1364-2001 standard allows you to specify properties for objects, statements, and groups of statements in the HDL source. These properties are used to control the operation or behavior of the tools. These properties are called attributes.  

(* attributeName1=”attributeValue1”, attributeName2=”attributeValue2”,attributeName3=”attributeValue3”) module attribute_test(out,in,clk);

(* attrbuteName4="attributeValue4", attrbuteName5="attributeValue5" *) output out; //module port  attributes

(* attrbuteName6="attributeValue6", attrbuteName7="attributeValue7" *) input in, clk; //module port  attributes

(* attrbuteName8="attributeValue8", attrbuteName9="attributeValue9" *) wire m,n; // net attributes

// instance attributes

(* attributeName12=” attributeValue12” *) and a2 ( m, n);

endmodule

For module, instance, port, and net, attributes are stored as hierarchical database properties on the cellview, instance, port, and net objects respectively and can be specified using the verilogAttributes option in the Edit Cellview Properties form.

Inherited Connections

Verilog In is enhanced to support supply sensitivity specification, netExpressions including port netExpression and wire netExpression statements, and netSet properties. During import, Verilog In reads and creates netExpression and netSet properties on instances, ports and nets as applicable. The following topics explain the support for inherited connections in Verilog In.

Supply sensitivity specification

You can specify the supply port sensitivity information for power and ground supply as attributes of input, output, and inout ports. The attributes indicate the relationship between the port on which they are attached to the specified power port. Supply sensitivity information indicates the effective power and ground signals to use when an application needs to establish a logical connection to 1'b1 (power) or 1'b0 (ground), in a Verilog netlist.

The attributes supplySensitivity and groundSensitivity are used for specifying the sensitivity to the power supply port and ground supply port respectively.  

module inv( a, y, powr, grnd) ;

(* supplySensitivity = "powr", groundSensitivity = "grnd" *)
input a ;
(* supplySensitivity = "powr", groundSensitivity = "grnd" *)
output y ;

As there is no direct way to verify that the specified port is in fact a supply port, therefore, a basic check is made to ensure that the port exists in the module port list.

The following two statements can be considered equivalent to the single statement as shown below.

(* powerSensitivity = "powr", groundSensitivity = "grnd" *)
   input a ;

(* powerSensitivity = "powr", groundSensitivity = "grnd" *)
   input b;

Equivalent single statement:

(* powerSensitivity = "powr", groundSensitivity = "grnd" *)
   input a, b;

Inherited connection specification (netExpression)

Net expression can be added either as attributes on a port declaration or to wires not associated with named ports. If the net expressions are added to wires, the connectivity is established through the hierarchy without explicit ports on the module declaration.

Port netExpression

A net expression added to a port indicates the name of the property for doing the connection look- up in the hierarchy, as well as a default value for the connection, if no explicit overwrite is found.

(* netExpr = "vdd(vdd_)" *) inout powr ;

The above declaration means that the input-output verilog port called powr has a net expression attached to it. The name of the property to search for in the hierarchy is “vdd_” and the default net name to connect to is the global net (in this case specified through an out of module reference) called vdd(vdd_). In the case where the port is explicitly connected when the module is instantiated, the net expression is ignored, irrespective of the netSet properties defined at a higher level in the hierarchy.

Wire netExpression

A similar net expression declaration is also available for wires. Since there are no ports associated directly with a wire, the only way to overwrite the default value of an inherited connection, defined on a module wire, is by using a netSet property in a higher level of hierarchy.

(* netExpr = "clock(clck_)" *) wire CK ;

In the above example, to build the effective connectivity for the wire, clck_, the elaborator searches the hierarchy for a netSet named clock. In no netSet is found, then it defaults to the clock(clck_) net name.

Inherited Connections Setup(netSet)

NetSet statements are used to determine the value of the property that was specified in a net expression in the lower elements of a hierarchy to establish connectivity.

(* netSet = "vdd,vss" *)

(* vdd = "DVDD" , vss = "DVSS" *) moduleName

instanceName( portConnectivity));

In the above example, the values for the vdd and vss connections are assigned to the local net names DVDD and DVSS. This means that the net expressions located within the module that is instantiated by this statement, or lower within the hierarchy of this module, are resolved to the DVDD and DVSS connections unless the expression is for a port that has an explicit connection.

For more information on inherited connections, see Customizing the Hierarchical Netlister (HNL) ,and Netlisting.

Named Parameter Assignment

As per the Verilog IEEE 1364-1995 standard, you can modify the values of parameters declared within an instantiated module in only the following ways:

• Using the defparam statement, which allows assignment to parameters using their hierarchical names.
• Using module instance parameter value assignment, which allows values to be assigned inline during module instantiation. There are two forms of module instance parameter value assignment:
  • assignment by ordered list
  • assignment by name

The Verilog IEEE 1364-1995 standard supports only one form of module instance parameter value assignment - assignment by ordered list. The Verilog IEEE 1364-2001 standard includes module instance parameter value assignment by name. Parameter assignment by name consists of explicitly linking the parameter name with its new value. The parameter name is the name specified in the instantiated module. Verilog In has been enhanced to support named parameter assignment as shown below.  

module ram (...);

parameter WIDTH = 8;

parameter SIZE = 256;

endmodule

module my_chip (...);

...

ram #(8, 1023) ram1 (...);    // Parameter redefinition by position

ram #(.SIZE(1023), .WIDTH(1000)) ram2 (...); // Parameter redefinition by name (named param assign)

...

 endmodule

ANSI-C Style Port Declarations

As per the Verilog IEEE 1364-1995 standard, the order of ports is defined within parentheses and the port declarations are listed after the parentheses. For tasks and functions, the parentheses list is omitted and the order in which the declarations have been specified is used to define the input/output order. The Verilog IEEE1364-2001 standard uses an updated syntax that is similar to the ANSI C language. When specifying the input and output declarations for modules, tasks, and functions, the declarations can be specified within parentheses to indicate the order of input and output.

For example, when declaring the input and output of a module, the following syntax is supported:

module mux8 (output wire [7:0] x,

input wire [7:0] a,

input wire [7:0] b,

input wire enable);

...

...

endmodule

Verilog In parses both ANSI-C and non-ANSI-C style port declarations.

Combined Port and Type Declaration

For signals connected to the inputs or outputs of a module, you must declare the direction of the port and the type of the signal, such as net, reg, etc. As per the Verilog IEEE 1364-1995 standard you are required to specify these two declarations in two separate statements. The Verilog IEEE 1364-2001 standard provides a simpler syntax allowing you to combine the two declaration into one statement as follows.

module mux8 (x, a, b, enable);

output wire [7:0] x;

input wire [7:0] a, b;

input wire enable;

...

...

endmodule

Indexed Part Selects

In the Verilog IEEE1364-1995 standard, variable bit selects of a vector are permitted, but part-selects must be constant. You could not, for example, use a variable to select a specific byte out of a word.

The Verilog IEEE 1364-2001 standard adds a second type of part-select, called indexed part select. According to the standard, an indexed part select of a vector net, vector reg, integer variable, or time variable can be specified by providing a base expression, a width expression, and an offset direction, using the following syntax:

 [base_expression +: width_expression]     //positive offset

 [base_expression -: width_expression]     //negative offset

The base expression can be a constant or it can vary during simulation run time. The width_expression must be a constant. The offset direction indicates if the width expression is added or subtracted from the base expression.

module top;

wire [5:0] in;
wire [0:5] in2;
wire [1:0] out2;
BUF u2 (out2, in[4 -: 2]);
BUF u1 (out2, in2[1 +: 2]);

endmodule

module BUF (out, in);

input [1:0] in;
output [1:0] out;
buf (out[0], in[0]);
buf (out[1], in[1]);

endmodule

Power Operator and Arithmetic Shift Operator

The Verilog IEEE 1364-2001 standard adds a power operator, represented by **. This operator performs exponential arithmetic.

module expr_delay (o, i);

output o;
input i;

buf #(2 ** 3, 9 >>> 2) (p, i);

endmodule

Also, Verilog IEEE 1364-2001 supports two types of shift operators, the logical shift operators, << and >> and the arithmetic shift operators, <<< and >>>. Verilog IEEE 1376-1995 standard provides only the logical shift operator.

Constant expressions are allowed only in delays. Therefore, Verilog In supports these new operators for delays and creates functional view for all other cases.