Contents
Licensing
License Requirement for Spectre FMC
Legato Reliability Solution License
License Checkout Order
Using License Queuing
Suspending and Resuming Licenses
Related Documents for Spectre
Third Party Tools
Typographic and Syntax Conventions
References
Spectre Usability Features and Customer Service
Variation Analysis
Supported Features
Analog HDL
AHDL Linter
RF Capabilities
Using the Example and Displaying Results
Sample Schematic
Sample Netlist
Elements of a Spectre Netlist
Instructions for a Spectre Simulation Run
Following Simulation Progress
Screen Printout
Viewing Your Output
Starting Virtuoso Visualization and Analysis XL
Plotting Signals
Changing the Trace Color
Learning More about Virtuoso Visualization and Analysis XL
Starting Spectre APS Simulations
Getting More Performance from Spectre APS Simulation
Specifying Multithreading Options
Simulation Diagnostics
Spectre Mixed-Signal Design Simulation
Starting an Spectre MS Simulation Run
Adjusting MS Speed and Accuracy
Digital Partitioning and Virtual Power Nodes
Spectre MS DC Operating Point Calculation
Spectre MS Current Accuracy
Handling Macro Device Models
Spectre MS Postlayout Simulation
Spectre MS Partitioning Report
Starting Spectre XPS Simulation Run
Reviewing the Log File
Spectre XPS cktpreset Mode Information
File Reading and Parsing Related Information
Output and IC/Nodeset Related Information
Options to Control Warning/Error Messages in Spectre XPS
Transient Simulation Information
Output Files
Using the Command-Line Option -outdir
Using the Command-Line Option -outname
Multithreading Support
Spectre XPS Options
Options Related to Circuit Partitioning
Options Related to RC
Options Related to Models
Option Related to SRAM Bitcell
Options to Control Error Tolerance
Option to Report DC Non-Convergence
Options to Control Waveform and Output
Post-layout simulation
Spectre XPS SRAM Simulation
XPS SRAM Timing Simulation
XPS SRAM Power Simulation
XPS SRAM Postlayout Simulation
XPS SRAM Leakage Current Simulation
Handling SRAM Designs at Advanced Technology Nodes
Spectre XPS DRAM Simulation
Spectre XPS DRAM Postlayout Simulation
Starting an XPS DRAM Simulation Run
Overall Accuracy/Performance Tuning Strategy in Spectre XPS
High Accuracy Mode
Function Verification Mode
Accuracy for Analog Block in DRAM Simulation
Spectre XPS Flash Simulation
Adjusting Speed and Accuracy of Spectre XPS Flash Memory Simulation
Starting a Spectre XPS Flash Memory Simulation
Flash Memory Postlayout Simulation
License Requirements for Spectre X
Using the Spectre X +preset Option
Dynamically Changing Parameters in Spectre X
Migrating from Spectre APS
Using the Spectre X +xdp Option
Using GPU with Spectre X
License Requirements for GPU
Use Model
Technology and Overview
Use Model and Applications
Setup to Enhance the Performance of a Fast Monte Carlo Simulation
Post-Process Fast Monte Carlo Data
Support for SPICE Netlists
Simulation Flow Compatible Options
Options to Specify the Output Format
Options to Specify the Hierarchy Delimiter
Options to Control Duplicated Subcircuits, Measures, Instances, and Parameters
Option to not Save the Waveform
Option to Enable or Disable the Safe Operation Area (SOA) Check
PSpice Netlist and Device Model Support
Netlist Statements
Netlist Conventions
Basic Syntax Rules
Spectre Language Modes
Creating Component and Node Names
Escaping Special Characters in Names
Duplicate Specification of Parameters
Instance Statements
Formatting the Instance Statement
Examples of Instance Statements
Basic Instance Statement Rules
Identical Components or Subcircuits in Parallel
Analysis Statements
Basic Formatting of Analysis Statements
Examples of Analysis Statements
Basic Analysis Rules
Control Statements
Formatting the Control Statement
Examples of Control Statements
Model Statements
Formatting the model Statement
Creating a Model Alias
Creating an alias for a Subcircuit
Examples of model Statements
Using analogmodel for Model Passing (analogmodel)
Basic model Statement Rules
Input Data from Multiple Files
Syntax for Including Files
Formatting the include Statement
Rules for Using the include Statement
Example of include Statement Use
Reading Piecewise Linear (PWL) Vector Values from a File
Using Library Statements
Structural Verilog
Multidisciplinary Modeling
Setting Tolerances with the quantity Statement
Inherited Connections
Instance (Component or Analysis) Parameters
Types of Parameter Values
Parameter Dimension
Parameter Ranges
Help on Parameters
Scaling Numerical Literals
Parameters Statement
Circuit and Subcircuit Parameters
Parameter Declaration
Parameter Inheritance
Parameter Referencing
Altering/Sweeping Parameters
Expressions
Behavioral Expressions
Built-in Constants
User-Defined Functions
Predefined Netlist Parameters
Subcircuits
Formatting Subcircuit Definitions
A Subcircuit Definition Example
Subcircuit Example
Rules to Remember
Calling Subcircuits
Modifying Subcircuit Parameter Values
Checking for Invalid Parameter Values
Enabling/Disabling Noise in Subcircuits
Conditional Subcircuits
Inline Subcircuits
Modeling Parasitics
Parameterized Models
Inline Subcircuits Containing Only Inline model Statements
Process Modeling Using Inline Subcircuits
Component Model
Binning
Auto Model Selection
Conditional Instances
Scaling Physical Dimensions of Components and Device Model Technology
Multi-Technology Simulation
Specifying cmin
N-Port Modeling
N-Port Example
Creating an S-Parameter File Automatically
Creating an S, Y, or Z-Parameter File Manually
Reading the S, Y or Z-Parameter File
Improving the Modeling Capability of the N-Port
S-Parameter File Format Translator
Standard Scattering Parameter Modeling and Mixed-Mode Scattering Parameter Modeling
Transmission Line Modeling
Constant RLGC Matrices
Frequency-Dependent RLGC Data
2-D Field Solver Geometry and Material Information
S-Parameter Data
TLINE Parameters
Input/Output Buffer Modeling Using IBIS
IBIS Translator Model
Example of an IBIS Component Subcircuit
Types of Analyses
Analysis Parameters
Specifying Parameter Defaults in a File
Probes in Analyses
Multiple Analyses
Multiple Analyses in a Subcircuit
Example
DC Analysis
Selecting a Continuation Method
Enabling Fast DC Simulation
AC Analysis
S-Parameter Analysis
Transient Analysis
Sweeping Parameters During Transient Analysis
Balancing Accuracy and Speed
The errpreset Parameter
Setting the Integration Method
Improving Transient Analysis Convergence
Controlling the Amount of Output Data
Calculating Transient Noise
Performing Small-Signal Analyses during a Transient Analysis
Performing DCMatch Analysis during a Transient Analysis
Generating EMIR Output During Transient Analysis
Performing Event-Triggered Analysis During Transient Analysis
Fault Analysis
Analog Test Overview
Application of Fault Analysis
Fault Analysis Technology
Fault List
Creating a Fault List
Layout-Based Fault Generation
Use Model of faultlayer
Use Model Examples of a Layout-Based Fault Simulation
Fault Universe Details Saved from Fault Generation
Fault Generation Based on Circuit Activity Analysis
Fault Generation for Design Hierarchy Extraction
Fault Selection and Sampling
Weighted Random Sampling
Uniform Random Sampling
Weighted Sorted Sampling
Confidence Interval Sampling
Benchmark Test of Fault Sampling, Simulation, and Confidence Interval Estimation
Defect Detection Using Weighted Likelihood
Fault Sampling Output and Confidence Interval Calculation
Applying Fault Weighting and Sampling in Fault Simulation
Assert Checking
Enabling Asserts for Fault Simulation
Verilog-A Asserts
Defining Fault Times
Specifying Event-Triggered Fault Times
Stopping Fault Simulation Automatically
Files Generated for Fault Simulation
Fault Table File
Assert Violation Database
Spectre Direct Fault Analysis
Spectre Transient Fault Analysis
spectre_ddmrpt Command-Line Options
spectre_fsrpt Command-Line Options
Pole Zero Analysis
Syntax
Example 1
Example 2
Example 3
Example 4
Output Log File
Loopfinder Analysis
Syntax
Output of the Loopfinder Analysis
Other Analyses (sens, fourier, dcmatch, and stb)
Sensitivity Analysis
Fourier Analysis
DC Match Analysis
ACMatch Analysis
Stability Analysis
Sweep Analysis
Monte Carlo Analysis
Spectre Reliability Analysis
Reliability Simulation Block
Reliability Analysis with Spectre X Distributed Simulation
Reliability Control Statements Reference
accuracy ( *relxpert: .accuracy )
age ( *relxpert: .age )
agelevel_only ( *relxpert: .agelevel_only )
aging_analysis_name
check_neg_aging (*relxpert: .check_neg_aging)
degradation_check (*relxpert: .degradation_check)
degradation_check_exception (*relxpert: .degradation_check_exception)
degradation_check_output (*relxpert: .degradation_check_output)
degsort (*relxpert: .degsort)
deg_ratio (*relxpert: .deg_ratio)
deltad ( *relxpert: .deltad )
dumpagemodel (*relxpert: .dumpagemodel)
enable_bias_runaway (*relxpert .enable_bias_runaway)
enable_negative_age (*relxpert .enable_negative_age)
enable_tmi_uri
gradual_aging_agepoint (*relxpert: .agepoint)
gradual_aging_agestep (*relxpert: .agestep)
idmethod ( *relxpert: .idmethod )
igatemethod (*relxpert: .igatemethod)
isubmethod (*relxpert: .isubmethod)
macrodevice (*relxpert: .macrodevice)
maskdev ( *relxpert: .maskdev )
minage ( *relxpert: .minage )
opmethod (*relxpert: .opmethod )
output_inst_param (*relxpert: .output_inst_param)
output_she_power (*relxpert: .output_she_power)
reset_analysis_param
output_device_degrad ( *relxpert: .output_device_degrad )
output_subckt_degrad
preset (*relxpert: .preset)
rel_mode (*relxpert: .rel_mode)
relx_tran ( *relxpert: .relx_tran )
report_model_param (*relxpert: .report_model_param )
simmode
tmi_aging_mode (*relxpert: .tmi_aging_mode)
tmi_she_mindtemp (*relxpert: .tmi_she_mindtemp)
uri_lib ( *relxpert: .uri_lib )
vdsmethod
Aging Monte Carlo Analysis
User-Defined Reliability Models
Measuring the Reliability Analysis
Thermal Nodes
External Thermal Node
Internal Thermal Node
SpectreThermal Analysis
Spectre Thermal Analysis Technology, Product, and Flow Overview
Thermal Control Files
Trench Structure Support
Cauer and Foster Model Support in Package File
Getting Started with Spectre Thermal Analysis
Generating the Thermal Analysis Database and Plotting the Results
The alter and altergroup Statements
Changing Parameter Values for Components
Changing Parameter Values for Models
Further Examples of Changing Component Parameter Values
Changing Parameter Values for Circuits
The ic and nodeset Statements
Setting Initial Conditions for All Transient Analyses
Supplying Solution Estimates to Increase Speed
Specifying State Information for Individual Analyses
The info Statement
Specifying the Parameters You Want to Save
Specifying the Output Destination
Examples of the info Statement
Printing the Node Capacitance Table
Printing the Capacitance Values of Nets
Printing the Terminal Capacitance Values of MOSFETs
The options Statement
options Statement Format
options Statement Example
Performing Parasitic Reduction
Setting Tolerances
Specifying Hierarchical Delimiters
Additional options Statement Settings You Might Need to Adjust
Simulation Config file Support
Computing the Constant Current
Computing the Drain Saturation Voltage Based on Output Conductance
The paramset Statement
The save Statement
Saving Signals for Individual Nodes and Components
Saving Groups of Signals
Using Wildcards in the Save Statement
The print Statement
Examples
The set Statement
The shell Statement
The statistics Statement
Signals as Output
Saving all AHDL Variables
Listing Parameter Values as Output
Specifying the Parameters You Want to Save
Specifying the Output Destination
Examples of the info Statement
Preparing Output for Viewing
Output Formats Supported by the Spectre Simulator
Defining Output File Formats
Accessing Output Files
How the Spectre Simulator Creates Names for Output Directories and Files
Filenames for SPICE Input Files
Specifying Your Own Names for Directories
Running Spectre in 64-Bit
Starting Simulations
Specifying Simulation Options
Using License Queuing
Suspending a Simulation Automatically When Disk Space is Low
Suspending and Resuming Licenses
Determining Whether a Simulation Was Successful
Checking Simulation Status
Interrupting a Simulation
Recovering from Transient Analysis Terminations
Creating Saved State Files
Creating checkpoint Files
Creating Recovery Files from the Command Line
Setting Recovery File Specifications for a Single Analysis
Restarting a Transient Analysis
Output Directory after Recovery
Controlling Command Line Defaults
Examining the Spectre Simulator Defaults
Setting Your Own Defaults
References for Additional Information about Specific Defaults
Overriding Defaults
About the AHDL Linter Feature
Using the AHDL Linter Feature
Identifying AHDL Linter Messages
Static AHDL Linter Message
Dynamic AHDL Linter Message
Filtering AHDL Linter Messages
Using the ahdlhelp Utility
Device Checks
The assert Statement
The check Statement
The checklimit Statement
Global Options
Circuit Checks
Circuit Check Scoping
Specifying the Output Format for the Checker Violation Report
Circuit Check SpiceVision PRO Integration
MonteCarlo Sweep and Alter Support in Dynamic Checks
Changing Default Value of Parameters
Circuit Check Syntax
Dynamic Checks
Static Checks
Static Stack Count
Workshop
Performance Improvement
EMIR Analysis
Spectre EMIR Technology, Product, and Flow Overview
Getting Started with Spectre EMIR Analysis
Establishing an Accuracy Reference and Correlating EMIR Accuracy
Optimizing EMIR Analysis for Accuracy and Performance
Power Gate Support
Handling the Complexity of DSPF/SPEF files
Advanced Analyses
Advanced EMIR Features
Event Triggered EMIR Analysis
Other Features
Spectre EMIR Analysis Using Voltus-XFi
Simplified Use Model for the Iteration Method
Enhanced Distribution of EMIR Analysis
Parasitic Backannotation of DSPF/SPEF/DPF Files
Postlayout Simulation Methodologies
Parasitic Backannotation - Concept
Control Options for Parasitic Backannotation Flow
Parasitic Backannotation Report
Some Common Error and Warning Messages Related to Parasitic Backannotation
New key for Encryption
Encrypting a Netlist
What You can Encrypt
Encrypted Information During Simulation
Protected Device
Protected Node
Protected Global and Netlist Parameters
Protected Subcircuit Parameters
Protected Model Parameters
Multiple Name Spaces
Displaying Messages Generated From an Encrypted Block
Specifying Efficient Starting Points
Reducing the Number of Simulation Runs
Adjusting Speed and Accuracy
Saving Time by Starting Analyses from Previous Solutions
Saving Time by Specifying State Information
Setting Initial Conditions for All Transient Analyses
Supplying Solution Estimates to Increase Speed
Specifying State Information for Individual Analyses
Saving Time by Modifying Parameters during a Simulation
Changing Circuit or Component Parameter Values
Modifying Initial Settings of the State of the Simulator
Saving Time by Selecting a Continuation Method
About Spectre Filename Specification
Creating Filenames That Help You Manage Data
Creating Filenames by Modifying Input Filenames
Description of Spectre Predefined Percent Codes
Customizing Percent Codes
Creating Filenames from Parts of Input Filenames
Error Conditions
Invalid Parameter Values That Terminate the Program
Singular Matrices
Internal Error Messages
Time Is Not Strictly Increasing
Spectre Warning Messages
P-N Junction Warning Messages
Tolerances Might Be Set Too Tight
Parameter Is Unusually Large or Small
gmin Is Large Enough to Noticeably Affect the DC Solution
Minimum Timestep Used
Syntax Errors
Topology Messages
Model Parameter Values Clamped
Invalid Parameter Warnings
Redefine Primitives Messages
Initial Condition Messages
Output Messages
Log File Messages
Customizing Error and Warning Messages
Selecting Limits for Parameter Value Warning Messages
Selecting Limits for Operating Region Warnings
Range Checking on Subcircuit Parameters
Formatting the paramtest Component
Controlling Program-Generated Messages
Specifying Log File Options
Correcting Convergence Problems
Correcting DC Convergence Problems
Correcting Transient Analysis Convergence Problems
Correcting Accuracy Problems
Suggestions for Improving DC Analysis Accuracy
Suggestions for Improving Transient Analysis Accuracy
Packaging a Test Case for Shipment to Cadence
Example
Notes on the BSIM3v3 Model
Spectre Syntax
SPICE BSIM 3v3 Model
Spectre BSIM 3v3 Model
Ring Oscillator Spectre Deck for Inverter Ring with No Fanouts (inverter_ring.sp)
Ring Oscillator Spectre Deck for Two-Input NAND Ring with No Fanouts (nand2_ring.sp)
Ring Oscillator Spectre Deck for Three-Input NAND Ring with No Fanouts (nand3_ring.sp)
Ring Oscillator Spectre Deck for Two-Input NOR Ring with No Fanouts (nor2_ring.sp)
Ring Oscillator Spectre Deck for Three-Input NOR Ring with No Fanouts (nor3_ring.sp)
Opamp Circuit (opamp.cir)
Opamp Circuit 2 (opamp1.cir)
Original Open-Loop Opamp (openloop.sp)
Modified Open-Loop Opamp (openloop1.sp)
Example Model Directory (q35d4h5.modsp)
Installing Compiled-Model Interface (CMI)
Configuration File
Configuration File Format
Precedence for the CMI Configuration File
Configuration File Example
CMI Versioning
Checking the CMI Shared Library
Loading a Plug-in
Using a NCF in a Spectre Netlist
Creating a Plug-in
Installing a NCF
Modifying the Default Behavior of a NCF
ncfSetNumArgs( ncfHandle_t, int, int )
ncfSetDLLFunctionV1( ncfHandle_t, ncfFunctionV1Ptr_t )
Attaching Arbitrary Data to a NCF
General Definition
Options for Digital Vector
vector_chk_zstate
vector_chk_xstate
Vector Patterns
radix
sig_type
io
vname
hier
tunit
chk_ignore
chk_window
enable
period
mask
Signal Characteristics
Timing
idelay
odelay
tdelay
slope
tfall
trise
Voltage Threshold
vih
vil
voh
vol
avoh
avol
vref
vth
Driving Ability
hlz
outz
triz
Tabular Data
Absolute Time Mode
Period Time Mode
Valid Values
Vector Signal States
Input
Output
Example of a Digital Vector File
Frequently Asked Questions
Can I replace the bidirectional signal with an input and output vector?
How do I verify the input stimuli?
How do I verify the vector check?
Processing the Value Change Dump File
VCD Commands
VCD File Format
Definition Commands
$date
$enddefinitions
$scope
$timescale
$upscope
$var
$version
Data Commands
data
time_value
Signal Information File
Signal Information File Format
Signal Matches
.alias
.scope
.in
.out
.bi
.chk_ignore
.chkwindow
Signal Timing
.idelay
.odelay
.tdelay
.tfall
.trise
Voltage Threshold
.vih
.vil
.voh
.vol
Driving Ability
.outz
.triz
Hierarchical Signal Name Mapping
Enhanced VCD Commands
Signal Strength Levels
Value Change Data Syntax
Port Direction and Value Mapping
Enhanced VCD Format Example
Frequently Asked Questions
Is it necessary to modify the VCD/EVCD file to match the signals?
How can I verify the input stimuli?
How do I verify the output vector check?
Why should I use hierarchical signal name mapping?
What is the difference between CPU and user time?
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