1 Importing a Simple VHDL Design

This chapter discusses the following:

Introduction to the Example Design

In this chapter, you import a simple example VHDL design. This example is included in the Cadence software hierarchy, at <dfII_install_dir>/tools/dfII/samples/vhdlin/Test3, where <dfII_install_dir> is your installation directory.

The design is a full adder that includes a VHDL design of a half adder and an OR gate. The half adder contains the behavioral information, while the full adder is only structural. The entities (e) and architectures (a) are split into separate files. The VHDL design directory includes

full_adder.a.vhd
full_adder.e.vhd
half_adder.a.vhd
half_adder.e.vhd
or_gate.a.vhd
or_gate.e.vhd

You can import the design into each of the three types of outputs:

VHDL text view
Netlist view
Schematic view

Checklist Before Importing a Design

Before you use VHDL In to import a design, use the following checklist to review what you need:

What do you want to convert the VHDL design into?
- Schematic view
- Netlist view
- VHDL text view
Do you have all the design units you need?
- Entity declarations
- Architecture declarations
- Package declarations
- Package body declarations
Do you have the library units referenced by the design?
Can the parser parse your design?
Have you modified the design to eliminate or change those constructs that VHDL In cannot convert? (See Chapter 1, “Conversion Issues.”)
Have you listed all the Cadence libraries required by VHDL In in a cds.lib file either in the current working directory or in the standard installation path?
For standalone mode line commands
- Have you created a VHDL In parameter file?
- Have you created a file listing all the VHDL design files? (This file is optional.)

Setting Up the Library Environment

To set up your library environment before you import the example design, follow these steps:

Modify your cds.lib file to include the five minimum required libraries: basic, sample, US_8ths, STD (std), and IEEE (ieee).
The process for referencing these libraries is described Chapter 1, “Getting Started with VHDL In.”
Start VHDL In from the CIW menu banner or from the VHDL Tool Box.
Create the VHDL design files for the full adder in the directory of your choice.
In this example, the directory used is
```
~/vhdlin_examples/simple_design/
```

Importing to VHDL Cells

In this section, you import the full adder design as a VHDL design cell.

Setting Up the VHDL Import Form

Follow these steps to set up the VHDL Import form for the import process.

In the CIW, select File – Import – VHDL.
The VHDL Import form opens.
Locate the directory for the VHDL source files you want to import.
You can move down a directory in either of the following ways:
- Enter a path to the directory in the File Name field and press Return.
- Double-click a directory in the Files List Box.
You can move up one directory any of the following ways:
- Enter the path to the directory in the File Name field and press Return.
- Enter two dots (..) in the File Name field and press Return.
- Double-click ../ in the Files List Box.
The correct path is displayed below the Files List Box, and the source files are displayed in the Files List Box.
Display only files matching a certain pattern, from the current directory. (This is optional.)
Enter the pattern to match with wild card characters in the File Name field and press Return. The Files List Box lists only VHDL files in the directory matching the string you entered in the File Name field.
Select and add each source file you want to import from the File Name List Box to the Import Files List Box.
To locate a file name in the Files List Box, use the scroll bar to the right of the Files List Box.
You can select a single file and add the file to the Import Files List Box any of the following ways:
- Double-click the name in the Files List Box.
- Enter a file name in the File Name field and press Tab.
- Enter a file name in the File Name field and click Add>>.
You can also select multiple files (listed adjacently) and add them simultaneously to the Import Files List Box. Drag the mouse across the file names to highlight them, and click Add>>.
Press Tab to go to the Target Library Name field.
When you finish an entry in a field in the VHDL Import form, press Tab to go to the next field.
Do not press Return. Pressing Return is the same as clicking OK, which indicates you are ready to import. The form closes when you press Return after you specified an existing target library. A dialog box with an error message appears when you press Return without specifying a target library.
In the Target Library Name field, enter the target library name that you want to import the source files into (vhdl_designs). Press Tab to finish.
To accommodate the name mapping scheme used by the ncvhdl parser, use only lowercase letters to name your target libraries.
Set the Import Structural Architectures As cyclic field to vhdl.
You can leave all other options at their default setting.
In the Reference Libraries field, add sample, std, and ieee to the list.
Click Apply.
Clicking Apply instead of OK keeps the form open. You can then start the next example of importing to a netlist without having to complete the list of libraries in the Reference Libraries field again or having to add the designs to the Import Files List Box again.
The system imports the design file names into the target library you specified. You can use the VHDL Tool Box form or the Library Manager form to read or edit the cell view of each file.

Creating a New Target Library

If you specify a target library name that does not exist, a dialog box opens, asking you if you want to create the new library. If you click Yes, the New Library form opens.

Enter the library name and the directory where you want the library located.
Put the Cadence versions of the VHDL design, the netlist, and the schematic in ~/vhdl_designs, ~/netlist_library, and ~/sch_lib, respectively.
Select Do not need process information, and click OK

A message appears in the CIW display area:

Created library "vhdl_design" as “/net/.../~/vhdlin_examples/simple_design/vhdl_designs”

After the new library is created, you must go back to the VHDL Import Form and click Apply again to import the file names you specified into the target library you just created.

Viewing the Results

A message in the CIW display area tells you that the VHDL Import process has started. When the process finishes, you are presented with a dialog box, which asks if you want to view a summary file. If you click Yes, the VHDL Tool Box status window appears, displaying a summary file. You can also view the log of resulting cellviews of your design in the summary file.

Viewing the Summary File

When the import process has finished successfully, you can examine the summary file to check the results of importing to VHDL. The summary file contains information about the number of files processed by VHDL In, the number of files attempted to be imported by VHDL In, the design units imported, and their view types. The summary file also mentions the files that VHDL failed to import, and the reason for the failure.

The following summary file was generated for a successful VHDL to VHDL import process. You can view the summary file through the VHDL Tool Box status window labeled VHDL Tool Box Log File. The window refers to the VHDL Tool Box even if you start from the CIW.

To close the VHDL Tool Box status window

Select File – Close.

The contents of the summary file and the error file are saved with the name you had typed in the Summary File field in the VHDL Import Form. The default value of Summary Field is ./vhdlin.summary.

For examples of error messages, see Chapter 1, “Error Messages.”

To close the VHDL Tool Box status window, select File – Close.

Viewing the Design’s Cellviews

Once the import process has finished successfully, you can examine the cellviews in the target library (such as the entity cellview) to check the results of importing to a VHDL cell.

In the CIW, select Tools – Library Manager.
The Library Manager window opens.
In the Library list box, click the vhdl_designs library name.
The Cell list box displays two cells for the vhdl_designs library: full_adder and half_adder.
In the Cell list box, click the full_adder cell name.
The View list box displays three cellview names for the full adder design: entity, structure, and symbol.
In the View list box, double-click the entity cellview file name.
A text editor window opens, displaying the contents of the entity cellview, as shown below: a text file and directory for the entity file for the full_adder design.

You can open the same file in the Language Sensitive Editor, or LSE (emacs) that highlights the language specific keywords. If you are using LSE and the text editor window is empty, use the File – Open command to open ~/vhdl_designs/full_adder/entity.
VHDL In places VHDL design text files in the vhdl.vhd file. You can open the vhdl.vhd file for viewing to verify the contents of the file.
To open the vhdl.vhd file for viewing, double-click the vhdl.vhd file name.

The top half of the LSE text editor window displays the contents of the vhdl.vhd file, and the bottom half shows the files and directories in the entity directory.

Importing to a Netlist

In this section, you import the full adder design as a OA format netlist. If the VHDL Import form is still open from the first example, Importing to VHDL Cells, you can skip steps 1 through 3.