1 Creating a Parameter File

This chapter discusses the following:

Parameter File Structure

This chapter describes the statements you must use when you create a VHDL In parameterfile. You can use this file when running VHDL In in standalone mode. A VHDL In parameter file must consist of a series of single line entries, each with the following syntax:

parameter_name := parameter_value -- <comments>

Here is a long parameter file. This file supports the conversion of a VHDL adder design into a Virtuoso schematic.

logFileName := /tmp/vhdlImLob14298
errorFileName := /tmp/vhdlinErb14298
importLibraryName := adder
inputPinSymbol := basic ipin symbol
outputPinSymbol := basic opin symbol
inoutPinSymbol := basic iopin symbol
contAssignSymbol := basic patch symbol
ignoreContassFunc := FALSE
writeInRefLibs := TRUE.
structuralViewType := schematic
referenceLibraries := basic,US_8ths
symbolViewName := symbol
overwriteExistingView := TRUE
maxError := 10
powerType := std_ulogic
powerLiterals := ‘1’
powerNetName := VDD!
groundType := std_ulogic
groundLiterals := ‘0’
groundNetName := GND!
sheetBorderSize := US_8ths Asize symbol
maxNoRows := 1024
maxNoCols := 1024
fontHeight := 0.062500
lineLineSpacing := 0.200000
lineComponentSpacing := 0.500000
componentDensity := 0
pinPlacement := left_right_boundaries_only
fullPlaceRouteSchematic := TRUE
squareSchematics := TRUE
minimizeCrossovers := TRUE
optimizeLabels := TRUE
caseSensitivity := FALSE
generateFastSchematic := TRUE
fastSchematicMaxInst := 20000
fastSchematicMaxPort := 5000

Description of Parameters

The following sections describe each parameter and give a sample parameter specification. If you leave out a parameter, the system assigns it the default.

Anything that is not an integer or real number is a string. A string does not need quotes. Trailing and preceding white spaces have no effect. Blank spaces inside strings are preserved. You can write only one parameter specification per line. You can continue a specification onto a second line by using a backslash (\) at the end of the first line.

logFileName. UNIX file where VHDL In places the log of the import process. The default is vhdlin.log.

logFileName := vhdlin.log

errorFileName. UNIX file where VHDL In places any error messages that occur during the import process. The default is vhdlin.err.

errorFileName := vhdlin.err

importLibraryName. Specifies the logical library in OA format where VHDL In places the output. If you do not provide a path to this library in your cds.lib file, and if the directory does not exist, then VHDL In creates an import library in the current working directory and appends its definition in the cds.lib file. There is no default. You must always provide a library name.

importLibraryName := test_library

inputPinSymbol. Specifies the symbol that VHDL In must instantiate for input pins. If you do not specify a symbol, or VHDL In cannot find it, VHDL In cannot generate a schematic. There is no default. You must always provide a value if you are trying to generate structural netlist or schematic.

inputPinSymbol := basic ipin symbol

outputPinSymbol. Specifies the symbol that VHDL In must instantiate for output pins. If you do not specify a symbol, or VHDL In cannot find it, VHDL In cannot generate a schematic. There is no default. You must always provide a value if you are trying to generate a structural netlist or schematic.

outputPinSymbol := basic opin symbol

inoutPinSymbol. Specifies the symbol that VHDL In must instantiate for inout pins. If you do not specify a symbol, or VHDL In cannot find it, VHDL In cannot generate a schematic. There is no default. You must always provide a value if you are trying to generate a structural netlist or schematic.

inoutPinSymbol := basic iopin symbol

contAssignSymbol. Specifies the symbol that needs to be instantiated for a continuous assign statement. If such a symbol is not present, then VHDL In cannot generate a schematic. There is no default. You must always provide a value if you are trying to generate a structural netlist or schematic.

contAssignSymbol := basic patch symbol

ignoreContassFunc. Ignore continuous assignment statement function. Some continuous assignment statements assign the function of a variable to another variable, such as a <= f(b). This is impossible to netlist and must be treated as a behavioral statement. If ignoreContassFunc is true, VHDL In ignores the function f(), treating the statement as a simple assignment. Use this parameter with caution, because setting it to TRUE can change a statement such as a <= not(b) so that a is aliased to b, which is not correct.

ignoreContassFunc := TRUE

writeInRefLibs. If this parameter is set to true, VHDL In creates symbols in reference libraries when the component instances in the architecture are bound libraries that do not have the relevant symbol view.

writeInRefLibs := TRUE

structuralViewType. Valid view types are

vhdl
schematic
netlist

The default is schematic.

structuralViewType := schematic

Corresponds to the Import Structural Architectures As Cyclic field on the VHDL Import form.

referenceLibraries. A list of libraries that VHDL In searches for the symbols of any unbound instances in an architecture. If VHDL In cannot find the symbol in any reference library, it creates a symbol in the destination library and instantiates it. The default is the import library, which VHDL In always searches first. If you provide other libraries, VHDL In searches them in order.

referenceLibraries := sample, basic

Corresponds to the Reference Libraries field on the VHDL Import form.

symbolViewName. The view name where the symbol file resides. The default view name is symbol.

symbolViewName := symbol

Corresponds to the Symbol View Name field on the VHDL Import form.

overwriteExistingView. This option has only two valid values: TRUE and FALSE (in uppercase or lowercase). When this parameter is TRUE, VHDL In overwrites the existing view in the destination library. The default is TRUE.

overwriteExistingView := TRUE

Corresponds to the Overwrite Existing Views click box on the VHDL Import form.

overwriteSymbolView. This option specifies whether to overwrite symbol of a module that already exists in the target library with the symbol being imported by VHDL In. This parameter has the following four valid values:

0 does not overwrite any symbol.
1 overwrites symbols created by VHDL In (symbols that have the createdBy property set as vhdlin).
2 overwrites symbols created by the Text-to-Symbol generator or any other tool (symbols that have the createdBy property set as any value other than vhdlin).
3 overwrites all symbols.

The default is 0.

overwriteSymbolView := 1

Corresponds to the Overwrite Symbol Views list box on the VHDL Import form.

maxError. An integer that specifies the maximum number of analysis errors per file that VHDL In reports in case the file analysis fails. The default is 10.

maxError := 10

Corresponds to the Maximum Number of Errors field on the VHDL Import form.

powerType. This option indicates the base type of the enumeration literal. The default is std_ulogic.

powerType := std_ulogic

Corresponds to the (Power) Data Type field in the Power section on the VHDL Import form.

powerLiterals. This option indicates which literal values on the LHS of a continuous assignment statement specify a power net. The default is ‘1’.

powerLiterals := ‘1’, ‘H’

Corresponds to the (Power) Value field in the Power section on the VHDL Import form.

powerNetName. Used in OA to indicate a power net. If you forget to put an exclamation point (!) at the end of the name, VHDL In automatically adds one. The default is "VDD!"

powerNetName := “VDD!”

Corresponds to the (Power) Net Name field in the Power section on the VHDL Import form.

groundType. This option indicates the base type of the enumeration literal. The default is std_ulogic.

groundType := std_ulogic

Corresponds to the (Ground) Data Type field in the Ground Section on the VHDL Import form.

groundLiterals. You can use this option a second time to indicate which literal values on the left-hand side (LHS) of a continuous assignment statement specify a ground net. The default is '0'.

groundLiterals := ‘0’, ‘L’

Corresponds to the (Ground) Value field in the Ground section on the VHDL Import form.

groundNetName. You can specify this parameter a second time to indicate a ground net in OA. If you forget to put an exclamation point (!) at the end of the name, VHDL In automatically adds one. The default is "GND!"

groundNetName := “GND!”

Corresponds to the (Ground) Net Name field in the Ground section on the VHDL Import form.

sheetBorderSize. The frame symbol used for the sheet border. There is no default. If you do not define this parameter, no order is instantiated.

sheetBorderSize := US_8ths Asize symbol

Corresponds to the Sheet Border Size cyclic field under the Schematic Generation Options tab.

maxNoRows. An integer that specifies the number of components that VHDL In can place in one row of a schematic page up to a maximum of 1024. This parameter is required only if you specify a sheet border. The default is 1024.

maxNoRows := 1024

Corresponds to the Maximum Number of Rows field under the Schematic Generation Options tab.

maxNoCols. An integer that specifies the number of components that you can place in one column of a schematic page. This parameter is required only if you specify a sheet border. The default is 1024.

maxNoCols := 1024

Corresponds to the Maximum Number of Columns field under the Schematic Generation Options tab.

fontHeight. A real number that specifies the height of wire labels in user units. You must use Virtuoso Schematic Editor L to specify which user units you are using. Pin labels are 75% of the specified height. The default is 0.0625.

fontHeight  := 0.0625

Corresponds to the Font Height field under the Schematic Generation Options tab.

lineLineSpacing. A real number, representing the space, in inches, between two adjacent nets. The range is 0.125 to 0.625 inches.

lineLineSpacing := 0.2

Corresponds to the Line to Line Spacing field under the Schematic Generation Options tab.

lineComponentSpacing. A real number, representing the space, in inches, between a component and an adjacent net. The range is 0.125 to 0.625 inches.

lineComponentSpacing := 0.125

Corresponds to the Line to Component Spacing field under the Schematic Generation Options tab.

componentDensity. An integer that controls the number of instances on one page of a schematic with a sheet border. The range is 0 to 100 instances.

componentDensity := 0

Corresponds to the Component Density sliding field under the Schematic Generation Options tab.

pinPlacement. Specifies the pin placement for the schematic view. Valid options are

left_right_boundaries_only
all_boundaries
file, pinPlacementFileName
```
pinPlacement := all_boundaries 
```

The default is left_right_boundaries_only. If you specify file, VHDL In expects a second argument that specifies the file name, following this syntax:

pinPlacement = file, <pinPlacementFileName>

The pin placement file must consist of single-line statements that use the following syntax:

componentPinPlacement ::= entityName, dir, pin_name_list

where

dir = top | bottom | left | right

and

pin_name_list = <pinName> [, <pinName>]

An example of a pin placement file is

componentPinPlacement := DFF, top, CLOCK
componentPinPlacement := DFF, left, D
componentPinPlacement := DFF, right, Q, Qn

Corresponds to the Pin Placement section underthe Schematic Generation Options tab. This section has the radio buttons Left and Right Sides, All Sides, and Pin Placement File.

fullPlaceRouteSchematic. When you set this parameter to FALSE, VHDL In generates a schematic that is connected only by name, resulting in a faster creation of the schematic view and lower memory consumption. For an exceptionally large design, this gain is significant. The default is TRUE.

fullPlaceRouteSchematic := TRUE

Corresponds to the Full Place and Route click box under the Schematic Generation Options tab.

squareSchematics. If this parameter is TRUE, VHDL In performs squaring on schematics to break disproportionately long columns of components into many columns. The default is TRUE.

squareSchematics := TRUE

Corresponds to the Generate Square Schematics click box under the Schematic Generation Options tab.

minimizeCrossovers. If you set this parameter to TRUE, VHDL tries to enhance the aesthetic quality of the schematic by minimizing net crossovers. This slows down the schematic generation. For large designs, the slowdown is noticeable, while the improvement in aesthetics might not be so evident. The default is TRUE.

minimizeCrossovers := TRUE

Corresponds to the Minimize Crossovers click box under the Schematic Generation Options tab.

optimizeLabels. If you set this parameter to FALSE, VHDL In places net labels more rapidly. This could result in overlapping label names. The default is TRUE.

optimizeLabels := TRUE

Corresponds to the Optimize Wire Label Locations click box under the Schematic Generation Options tab.

caseSensitivity. If you set this parameter to FALSE, VHDL In performs a case-insensitive search of a component symbol in a reference library. The default is TRUE.

caseSensitivity := TRUE

The use of this parameter has certain restrictions. For more detailed information on the issues related to case-sensitive search, see Chapter 1, “Conversion Issues.”

generateFastSchematic. If set to TRUE, this parameter enables fast generation of the schematic when the design being imported contains a large number of instances or ports, specified in the fastSchematicMaxInst and fastSchematicMaxPort parameters.

generateFastSchematic := TRUE

For details on the generateFastSchematic, fastSchematicMaxInst, and fastSchematicMaxPort parameters, see “Fast Schematic Generation”.

fastSchematicMaxInst. Specify the number of instances. If the number of instances in the design being imported exceeds the specified number and generateFastSchematic is set to TRUE, VHDL In generates a schematic where the nets are not routed and the connectivity is indicated by names.

fastSchematicMaxInst := 20000

fastSchematicMaxPort. Specify the number of ports. If the number of ports in the design being imported exceeds the specified number and generateFastSchematic is set to TRUE, VHDL In generates a schematic where the nets are not routed and the connectivity is indicated by names.

caseSensitivity := TRUE

work_file. If you set this parameter to a library name, VHDL In will take this as the work library where the analyzed data will be created. The default is the target library.

work_file := my_work_lib

Corresponds to the VHDL WORK Library Name field under the Schematic Generation Options tab.

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VHDL In for Virtuoso Design Environment User Guide and ReferenceProduct Version IC23.1, June 2023

1

Creating a Parameter File

Parameter File Structure

Description of Parameters

VHDL In for Virtuoso Design Environment User Guide and Reference
Product Version IC23.1, June 2023