7 Customizing Your Environment

This appendix covers the following topics:

For information on the SKILL functions associated with VHDL Toolbox, see Digital Design Netlisting and Simulation SKILL Reference.

Setting VHDL HNL Variables

The following table shows VHDL HNL variables, which VHDL netlister uses while netlisting a design. You can also set these variables in the .simrc file.

Variable Name	Type	Value	Description
hnlInhConnPrefix	string	""	Support for Inherited Connection
hnlUserSimViewName	string	""	Netlist CDF parameters for
hnlUserStopCVList	list	("sample" "basic" "ieee")	Stop Library List
hnlVHDLBusRangeNotation	string	"Ascending"/"Descending"/"Auto"	Bus Range Notation
hnlVHDLMergeSignals	boolean	t/nil	Bus Range Notation
hnlVHDLCheckSameStopCellFromMultLibs	boolean	t/nil	Ext. Sources
hnlVHDLConfigSpecForCommonMaster	string	"`OTHERS`"/"`ALL`"	Instance Bindings
hnlVHDLDefaultClauseList	list	(("IEEE" "std_logic_1164" "all") ("STD"))	VHDL Default Context Clause
hnlVHDLDefaultDataType	string	"bit"	Default Data Type
hnlVHDLDefaultInhPortDataType	string	"bit"	Support for Inherited Connections
hnlVHDLDefaultInhPortMode	string	"IN"/"OUT"/"INOUT"	Support for Inherited Connections
hnlVHDLDefFileExts	list	("vhd" "vhdl")	Ext. Sources
hnlVHDLDonotUseCdsNmp	boolean	t/nil	Netlist Identifiers as
hnlVHDLEnforceVHDLViewList	list	("symbol_inh" "symbol_xxx")	VHDL Enforce Binding for Views
hnlVHDLGenTestBench	string	t/nil	Generate Test Bench Template
hnlVHDLIEEESyntax	string	"1076-1993"	VHDL IEEE Syntax
hnlVHDLInstanceBinding	string	"Direct"/"Configuration"	VHDL Instance Binding
hnlVHDLLibraryBinding	string	"Merge"/"Preserve"	VHDL Library Binding
hnlVHDLConfigUseLibNameForStoppingCell	boolean	t/ni	VHDL Library Binding
hnlVHDLMaxErrors	int	10	Max Errors
hnlVHDLMaxExtFileErrCount	int	1	Ext. Sources
hnlVHDLParseExtDataSeverity	string	"error"	Ext. Sources
`hnlVHDLPrintPortInitialValue`	boolean	t/nil	Print Default Value of Ports
hnlVHDLPriorityType	list	(?aType? ?bType?)	Type Conversion Functions
hnlVHDLResetExternalVHDLData	boolean	t/nil	Ext. Sources
hnlVHDLSingleNetlist	boolean	t/nil	Single Netlist File
hnlVHDLSkipGenericWithNoDefaultValue	boolean	t/nil	Modeling Instance Properties as Generics
hnlVHDLSplitConfigEnabled	boolean	t/nil	Generating the Configuration of All Cellviews
hnlVHDLSplitInstsInConfig	string	""	Instance Bindings
hnlVHDLTestBenchInstName	string	"dut"	SKILL Variables for Test Bench
hnlVHDLTypeConflictSeverity	string	"error" \| "warning"	Type Conflict Resolution
hnlVHDLTypeConversionFuncs	list	("typeA" "typeB" "fn_typeA2typeB" "fn_typeB2typeA"	Type Conversion Functions
hnlVHDLTypeResolverDefs	list	"typeA" typeB" "typeC"	Type Conflict Resolution
hnlVHDLUserComment	string	""	VHDL NetList Header
hnlVHDLUserDataTypeList	list	(("std_logic" "std_logic_vector" "LOGIC" "’0’") ("std_ulogic" "std_ulogic_vector" "LOGIC" "’0’") ("bit" "bit_vector" "LOGIC" "’0’"))	Data Types
hnlVHDLVerboseMode	boolean	t/nil	Detailed Report
simPrintInhConnAttributes	boolean	t/nil	Evaluate Inherited Connections
simReNetlistAll	boolean	t/nil	Netlisting
simResolveStopCellImplicitConns	boolean	t/nil	Support for Implicit Inherited Connections for Leaf Cells
simStopList	list	("symbol" "behavioral")	Stop View List
simViewList	list	("stimulus" "schematic" "structural" "dataflow" "behavioral" "symbol")	Switch View List
vhdlSimTestBenchFile	string	"test_bench.vhd"	SKILL Variables for Test Bench
vhdlSimTestBenchLCV	list	("library-name" "cell-name" "view-name")	SKILL Variables for Test Bench

In the .simrc file, you can also specify pre and post-processing functions hnlVHDLPreNetlistFunc() and hnlVHDLPostNetlistFunc(). For details, see “Customizing Pre- and Post-Processing Functions”.

Setting VHDL CDSENV Variables

The following table shows VHDL variables, which VHDL netlister uses while netlisting a design. You can set these variables in the .cdsenv file.

Variable Name	Type	Default Value	Possible Values	Description
analyzeMode	boolean	nil		Analyze(Compile) Design Units
busRangeNotation	string	"Auto"	"Ascending" "Descending" "Auto"	Bus Range Notation
caseSensitivity	string	"Converted using CDS NMP"	"Case Preserved" "Converted using CDS NMP"	Netlist Identifiers as
configName	string	"config_vhdl"		VHDL Configuration Name
configSuffix	string	"cfg"		VHDL Configuration File Suffix
defComment	string	"Netlist: Library=<libraryName>, Cell=<cellName>,View=<viewName> Time:<dateStamp>By:<user>"		Default Text
defaultDataType	string	"bit"	"bit" "std_logic" "std_ulogic" "real"	Default Data Type (for non-VHDL Views)
detailReport	boolean	nil		Detailed Report
elaborateMode	boolean	nil		Elaborate Design
enforceVHDLBindingView	string	"symbol_inh"		Enforce VHDL Binding for View(s))
`evalInheritedConn`	boolean	t		Evaluate Inherited Connections
generateTestBench	boolean	nil		Generate Test Bench Template
instanceBinding	string	"Direct"	"Direct" "Configuration"	VHDL Instance Binding
libraryBinding	string	"Merge"	"Preserve" "Merge"	VHDL Library Binding
maxErrors	int	10		Max Errors
netMode	cyclic	"ReNetlist All"	"Incremental" "ReNetlist All"	Netlisting Mode
simViewName	string	"<None>"		Netlist CDF parameters for
singleNetlist	boolean	t		Single Netlist File
`skipLibList`	string	"analogLib"		Skip Design Units
splitConfiguration	boolean	nil		Generating the Configuration of All Cellviews
stopLibList	string	"basic sample ieee"		Stop Library List
topLibraryName	string	""		Top Level Design
topCellName	string	""		Top Level Design
topViewName	string	""		Top Level Design
runDir	string	""		Run Directory
stopViewList	string	"symbol behavior behavioral"		Stop View List
switchViewList	string	"stimulus schematic structure structural dataflow behavior behavioral symbol"		Switch View List
vhdlIEEESyntax	string	"1076-1993"	"1076-1993" "1076-1987"	VHDL IEEE Syntax
defGenericsList	string	"'((\"REAL\" \"1.0\") (\"INTEGER\" \"1\") (\"STRING\" \"\") (\"TIME\" \"1 ns\") (\"BOOLEAN\" \"true\"))"		Generic Defaults
defDataTypeMappingList	string	"'((\"std_logic\" \"std_logic_vector\" \"LOGIC\" \"'0'\") (\"std_ulogic\" \"std_ulogic_vector\" \"LOGIC\" \"'0'\") (\"bit\" \"bit_vector\" \"LOGIC\" \"'0'\"))"		Data Types
defClauseList	string	"'((\"IEEE\" \"std_logic_1164\" \"all\") (\"STD\"))"		VHDL Default Context Clause

The defClauseList, defDataTypeMappingList, defGenericsList, and skipLibList CDSENV variables also accept values without a backslash and double quote \”. For example, both the settings below are valid:

envSetVal("vhdl.oss" "skipLibList"  'string  " '(( \"analogLib\" )) ")

envSetVal("vhdl.oss" "skipLibList"  'string  "'(( analogLib))")

Setting xrun Variables

The following table shows the SKILL variables that are used for the xrun utility. You can also set these variables in the .simrc file.

If you already have these variables set in the .vhdlrc file in the run directory, you do not need to add these variables. The settings from .vhdlrc are used.

Variable Name	Type	Value	Description
vhdlSimSimulator	string	”xrun”	Specifies the simulator to be used by VHDL Toolbox. You can set it to `xrun` to use the xrun utility or to `xmsim` to use the xmsim simulator.
vhdlSimVhdlFileExt	string	”.vhd,.vhdp,.vhdl,.vhdlp,.VHD,.VHDP,.VHDL,.VHDLP”	Include Extensions
vhdlSimVerilogFileExt	string	”.v,.V,.vp,.VP,.sv,.SV”	Include Extensions
vhdlSimLogFile	string	"file-name"	Log File
vhdlSimOptions	string	"-ieee364"	Simulation Options
vhdlSimDebugObjectAccess	string	"r"/ "rw"/ "rwc"	Debug Options
vhdlSimEnableLineDebug	boolean	t/nil	Debug Options
vhdlSimSnapShot	string	nil	Specifies name of the simulator snapshot.
vhdlSimNetlistandSimulate	boolean	t/nil	Specifies that the design should be netlisted before simulation.
vhdlSimCleanCompiledData	boolean	t/nil	Cleans the compiled data.
vhdlSimMode	string	"interactive"/ "batch"	Specifies whether the simulation is run in interactive or batch mode.
vhdlSimScriptFile	string	"file-name"	Specifies name of the script file to be run by the simulator.
vhdlSimIncludeTestBench	boolean	t/nil	Specifies that the testbench specified in the simulation is to be included.

Return to top

Virtuoso VHDL Toolbox User GuideProduct Version IC23.1, June 2023

7

Customizing Your Environment

Setting VHDL HNL Variables

Setting VHDL CDSENV Variables

Setting xrun Variables

Virtuoso VHDL Toolbox User Guide
Product Version IC23.1, June 2023