Virtuoso Stacked Silicon Solution Flow
Virtuoso Stacked Silicon Solution flow provides the required interface and options to design compact, stacked ICs. The following diagram depicts the overall Virtuoso Stacked Silicon solution flow.
In this flow, you can instantiate a die footprint in the package layout from a package library. The input from the package library includes a cellview that contains a layout, schematic, and symbol view. The output is a die footprint that is represented as a cellview and includes an abstract, a TILP, a schematic, and a symbol view.
The symbols of dies obtained from die export need to be arranged in a package schematic. A package schematic contains the IC and package portions of the design, which are represented, designed, and verified within a single environment.
Once the package layout has been generated from the package schematic, you can arrange the generated instances in the layout canvas and define the stack settings. Subsequently, you can create bumps and TSVs for the flip-chip dies, define connectivity for the bumps by assigning each bump to a net, and propagate the bump information to the dies on which the original die would be vertically stacked. Propagating helps align bumps in the two stacked dies.
Routing the design automatically or interactively by using a suitable router can be done at the end.
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Virtuoso Schematic Editor Driven SiP Layout Flow
Cadence SiP Layout Option has many features for package and module implementation alongside a complete complement of constraint-driven verification and automation tools to complete the implementation. Artwork and manufacturing activities must be performed in SiP Layout Option. Teams that do day-to-day module and package design in SiP Layout Option can enjoy benefits from using a Virtuoso Schematic Editor driven flow without changing their use model. In addition, it provides the ability to mix high-accuracy extraction models with ideal models and simulate the design along with the testbench in Spectre. Unified libraries let you map the terminologies and data between Virtuoso and Allegro for a seamless flow of information.
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