Product Documentation
Virtuoso SystemVerilog Netlister User Guide
Product Version IC23.1, August 2023

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Netlist Generation

Use the SystemVerilog Netlister to specify a design, configure the netlist generation options, configure design variables, netlist the design, view the netlist, and manage the states. You can generate a netlist, which contains connectivity information of a design, after you have specified the design. Configure the netlist generation options before you generate the netlist. When you generate the netlist, SystemVerilog Netlister creates a netlist file of your design based on the settings that you specify and lets you view the netlist file.

Related Topics

Specifying a Design for Netlist Generation

Configuring Netlist Generation Options

ATPG Compatible Verilog Netlists

Importing a SystemVerilog Package File

Specifying Additional xrun Arguments in SystemVerilog Netlister

DataType Propagation

Netlist Customization Using the .simrc File


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