Real Number Modeling

You can create designs using real number models (RNM) and simulate them using the AMS Designer simulator. Using either Verilog-AMS or VHDL-AMS languages, you can define real ports that are not electrical. You can use wreal connect modules to connect real number models to Spectre or SPICE or electrical blocks. The elaborator automatically inserts appropriate connect modules between electrical ports (analog domain) and wreal ports (digital domain).

Real connect modules support analog/digital (discrete wreal) conversion with a custom variable rate, while wreal connect modules support variable rate signal conversion. The absdelta function drives the real connect module analog-to-digital conversion, while digital events drive the real connect module digital-to-analog conversion.

Basic wreal Features of the AMS Designer Simulator

Basic wreal features of the AMS Designer simulator consist of the following:

• Scalar wreal declaration

• Local wreal declaration in a behavioral construct

• Hierarchical connection of nets where you explicitly assign the wreal data type

You can use these features to create real-numbered models.

For example, the following Verilog-AMS model for a DC source has an output port type that is wreal, which is like a wire with the ability to transfer a real number:

module rdcsource ( aout );
output aout;
wreal aout;     //output wreal
\logic aout;    //discrete domain

parameter real dc=0.0;
real aoutreg;

initial begin
    aoutreg=dc;
end
assign aout = aoutreg;

endmodule

The following Verilog-AMS model for a ramp source has an external clock that defines the sampling rate:

module step (clk, y );
input clk;
output y;
wreal y;
\logic y;

parameter real offset=0.0;
parameter real step=1;

real yval;

initial
    yval=offset;

always @(posedge clk)
begin
    yval = yval + step ;
    end

assign y = yval;
endmodule

Advanced wreal Features of the AMS Designer Simulator

Advanced wreal features of the AMS Designer simulator consist of the following:

• wreal arrays
  For example:
module wreal_src_bus ( out );
   output out[1:0]; 
   wreal out[1:0];

assign out[0] = 3.2;
assign out[1] = 2.2;
endmodule


• wreal nets with more than one driver.

• wrealXState and wrealZState

• Connections between wreal and VHDL real signals
  See also Connecting VHDL and VHDL-AMS Blocks to Verilog and Verilog-AMS Blocks.

• wreal coercion for hierarchical connections between wreal and wire nets, wreal and SystemVerilog real nets, wreal and VHDL real nets
  
  wreal coercion refers to the ability to connect wreal nets hierarchically to wires and coercing the wires to become wreals. This also includes support for hierarchical connection of a wreal net to SV-real and VHDL-real signals.
  
  For example, the following discrete wreal step generator connects to an electrical resistor, so the elaborator coerces wire aout to wreal and inserts a bidirectional electrical -to-real connect
  
  module: module top ( );
electrical gnd;
ground gnd;
wire aout;
\logic aout;    //discrete domain

    clock_gen #(.period(1.0)) I0 ( .clk( clk ) );
    step #(.step(10.0e-6)) I2 ( .clk( clk ), .y( aout) );
    resistor #(.r(200.0)) RLOAD2 (aout, gnd);
endmodule
  
  where module step might look like this:
  
  module step (clk, y );
input clk;
output y;
wreal y;
\logic y;

parameter real offset=0.0;
parameter real step=1;
real yval;
initial
    yval=offset;
always @(posedge clk)
begin
    yval = yval + step ;
endassign y = yval;

  endmodule

  You can use the xrun/xmelab option -rnm_coerce with parameters to turn the wreal coercion feature ON or OFF. The default is ON for whole design.

  See also Instantiating VHDL Blocks with Real Signal Ports on a Schematic and Connecting VHDL and VHDL-AMS Blocks to Verilog and Verilog-AMS Blocks.

• wreal nets with inherited connections
  This includes:

• Connection between a wreal nettype and another wreal nettype through an inherited connection.

• Connection between a wreal nettype and an electrical nettype through an inherited connection.
  Wreal nets with inherited connections are also supported in the analog design environment ( ADE ) flow. However, for this, you need to explicitly define the target nets of the inherited connection to wreal nets.

  Connection between the wreal nettype and the real nettype is not supported.

  Example (wreal nettype with another wreal nettype):


  module top; 
  
  wreal (* integer inh_conn_prop_name="global_prop_wreal";
               integer inh_conn_def_value="cds_globals.wr"; *) local;
   
  always @(local) begin 
  $display("======= local=", local);
  end
  
  initial begin
  
  #1 $display("======= (ini) local=", local);
          #1 $display("======= (ini) local=", local);
          #1 $display("======= (ini) local=", local);
  end
  
  endmodule

  where module cds_globals might look like the following:
  

  module cds_globals;
  
  electrical el, gnd;
      wreal wr;
      real re;
      wire wi;
      reg rg;
      ground gnd;
  
      assign wr = re;
      assign wi = rg;
  
      vsource #(.dc(3.3)) v1 (el, gnd);
  
      initial begin 
  #0 re = 0.0; rg = 0;
          #1 re = 1.1; rg = 1;
          #1 re = 2.2; rg = 0;
          #1 re = 3.3; rg = 1;
          #1 re = 4.4; rg = 0;
          #1 re = 5.5; rg = 1;
  end
  
  endmodule

• -wreal_resolution command-line option for specifying a resolution function for wreal nets with more than one driver

• wreal as an independent variable in the $table_model function
  
  For more information, see Using wreal Independent Variables in a $table_model.

• Delays on wreal nets
  Single net delays and assignment delays are supported on wreal nets. Assignment delays are supported when they are used with wreal nets that are part of continuous assignment declaration or net assignment declaration. This includes:

• real to wreal assignments
real r,
wreal w;
assign #5 w = r;


• wreal to wreal assignments
  wreal x,
wreal w;
assign #5 w = x;
  

Following are not supported:

• Multiple delays in a net delay. For example:
  wreal #(10,11) w;

• Multiple delays (rise, fall or rise, fall to-z) in an assignment delay. For example:
  assign #(2,3,4) a = b;

Related Topics

• Using the wreal Data Type
• Arrays of Real Nets
• Real Nets with More than One Driver
• Selecting a wreal Resolution Function