Product Documentation
Virtuoso Unified Custom Constraints User Guide
Product Version IC23.1, November 2023

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The Circuit Prospector Assistant

An Introduction to the Circuit Prospector Assistant

The Circuit Prospector recognizes structures using place-holder names for device, parameter, terminal and net names. As each Process Design Kit (PDK) and design library can use any names, each PDK and library must register the names used by each object for the respective place-holder names. For more information see PDK Setup for the Circuit Prospector in the Virtuoso Unified Custom Constraints Configuration Guide.

The Circuit Prospector assistant can be used to detect circuit structures, devices and nets based on certain criteria, and optionally apply a default set of constraints to them. It can also be used to set properties, or to visualize various groups of objects; acting as an additional search facility. Moreover, it can also be used for debugging, and to also apply specific actions to selected results.

For more overview information see also Circuit Prospector Overview.

In general, designers will want to apply a set of constraints to common circuit structures, related devices (such as same size, area, or type), devices with particular characteristics/connectivity, or symmetrical devices/nets/pins with particular properties.

However, performing this task manually and repetitively for multiple designs can be time consuming and error prone. As an aid to this task, the Circuit Prospector Assistant provides a flexible framework for capturing the information that a designer is looking for, locating structures and devices, and applying appropriate constraints to them, and consequently greatly accelerating the constraints entry process.

The Circuit Prospector provides a set of common structure finders that can be modified by the users to suit their design needs. Users can also create their own finders or capture any structure in the design and save it as a custom finder. The finders are grouped together in 'Categories' that can be customized as well. (See Creating and Editing Categories and Creating Finders).

Iterators are SKILL functions that analyze cellview devices, nets, and pins in a variety of ways, for example, you can iterate all selected objects, instances, or symmetrical devices.

As with The Constraint Manager Assistant there can only be one Circuit Prospector assistant visible in each session window.
For information on SKILL commands that can be used for Circuit Prospector assistant customization, see the Custom Constraints Functions chapter in the Virtuoso Unified Custom Constraints SKILL Reference.

Motivation

The following are some of the reasons why the Circuit Prospector is an essential tool for facilitating quick constraint entry:

The Circuit Prospector can help accelerate the constraint entry process significantly by retrieving and automatically grouping all design objects by common criteria, visualizing them, and suggesting relevant and corresponding constraints or properties.

Storage

All user-defined or modified Finders, Structures, Iterators and Constraint Generators are stored in your local .cadence/dfII/ci directory. The Cadence File Search mechanism is used to locate all .cadence directories and all finders, structures, iterators, and generators are loaded as they are found.

The files in your local .cadence directory are, by default, the last to be loaded and can override any finders, structures, iterators and generators that have been defined in other .cadence directories.

Accessing the Circuit Prospector

You can access the dockable Circuit Prospector assistant by either:

Circuit Prospector User Interface

The Circuit Prospector Assistant has three main components:

Circuit Prospector Toolbar

The first component of the Circuit Prospector is the toolbar at the top, which contains the following options:

Capture Structure

Capture Structure based on the settings and selections made in the Circuit Prospector.

Selecting this option will display the Capture Circuit Structure Form.

For more information, see Step 4: Apply default action/ constraints to the selected objects.

Run Finder

Run finder... based on the finder selection in the Search for drop-down list box.

The Run finder... and Run Default (Constraint Generation) Action drop-down menu on the Circuit Prospector toolbar become active only after you select a finder in the Search for drop-down list box.

Finders can be run on just the current schematic (the default), or the whole schematic, starting from the current cellview. See also ciRunFinder in the Virtuoso Unified Custom Constraints SKILL Reference. Choose from the following run finder options:

Run Default (Constraint Generation) Action

The options available in this menu (default constraint generation) are dependent upon the finder selected in the Search for drop-down list box and the Groups selected in the Circuit Prospector results table.

A finder must be selected and there must be one resultant group for this option to be enabled.

The first choice available in the menu (for example Generate Cluster Constraint for the Current Cellview) runs the default action and creates constraints only in the current cellview. If the finder was run hierarchically, constraints will have hierarchical path members, for example, I16/I22/MN1 and I16/I22/MN2.

The second choice in the menu runs the default action in the cellview at the hierarchical level in which the finder found the result. In this case, constraints would be created in the cellview for I16/I22, and will have members MN1 and MN2.

The corresponding cellviews must be open in write mode.

Currently selected finder identifies the type of constraints that are created and subsequently added to the Constraint Manager or the properties that are generated after selecting Run Default Action. This is because the default action is specified as part of the finder definition (see also Creating Finders).

The last option in this menu is Replace Existing Constraints, as shown below.

Clicking this option selects it as your choice for the consecutive constraint generator runs. Subsequently, running a constraint generator for the current cellview or for each sub-cell, first removes all existing constraints and then, creates the new constraints.

Delete

Use this menu to delete result entries from the results table.

Select All

Use this menu to select all result entries in the results table.

Deselect All

Use this menu to deselect all result entries from the results table.

Options

Clicking this menu item displays the following Circuit Prospector Options form:

Use this form to set the following:

Set of Drop-Down List Boxes

The second component of the Circuit Prospector, right under the toolbar, are a set of drop-down list boxes to select categories of constraints, apply finders, and choose those objects to be constrained. The drop-down list boxes are:

Results Table

The third component is a results table that lists, in tree display format, all the constrained groups and the finder that they belong to.

The results table contains the following columns:

The Circuit Prospector Constraint Creation Flow

The Circuit Prospector is used to repeatedly search for devices, pins, and nets to constrain based on specific, customizable criteria. The search results can then be browsed and filtered, before constraints are applied.

The Circuit Prospector constraint creation flow can be broken down into 4 main stages:

Step 1: Select a circuit prospector category

The first thing a designer should do, as part of the Circuit Prospector constraint creation flow, is to select a Category from the list of available assistants (see Categories).

Each Category contains a collection of related Finders (search algorithms).

Once a Category has been selected, a list of filtered finders is displayed in the Search for drop-down list box.

A Category comprises of a collection of related Finders that are search routines to look for devices, pins, or nets that meet certain criteria, for example, common circuit structures, related devices (same size, area, type, or shared connectivity), devices with certain characteristics or shared connectivity, symmetrical devices with particular properties and so on.

You should now continue to Step 2: Select a finder to search for relevant design objects

Step 2: Select a finder to search for relevant design objects

Figure 2-3 Active Same Cell Name and Size finder selected and current results shown

After selecting a Category, you must now choose from a range of related Finders (search algorithms) from the Search for drop-down list box. If ALL is selected from the list, all the finders under the current category will be run sequentially in the order of their listing in the Search for drop-drown list box.

For information on running finders in the current cellview only, in all hierarchy cellviews, or on a flattened hierarchy, see Run Finder.

As soon as the finder is selected from the Search for drop-down list box, the results (objects or groups of objects that meet the search criteria) are displayed in the results table in the same order. It should be noted that by default the finder runs only in the current cellview. To run the finder hierarchically or in a flattened hierarchy mode, follow the steps outlined in the previous section.

The finder options listed are dependent upon the selected Category.

Clicking the Edit Finder browse button will display the Edit Finder form, from where you can amend various attributes of the currently selected finder. For more information see Edit Finder Form.

At this point you are now ready to move to Step 3: (Optionally) Filter/ select the found objects to apply constraints to.

Step 3: (Optionally) Filter/ select the found objects to apply constraints to

There are two steps to complete when determining what objects a constraint should be applied to:

1. Select Objects to Constrain

The Within drop-down list box allows you to filter the objects to which you want to apply the selected finder (search). You have the following filter options:

Filter Option

Purpose

All objects

Lists all objects that matched the specified category and finder criteria. The list is displayed irrespective of the fact that the object has any constraint applied or not.

Constrained objects

Lists only those objects that have associated constraints.

Unconstrained objects

Lists only those objects that do not have any associated constraint.

Selected objects

Lists only the selected objects.

Unfound objects

Lists only unique objects when multiple finders are run sequentially, that is, when you select ALL in the Search for list.

Consider the Rapid Analog Prototype category. The Search for list for this category lists the finders in the following order: MOS Cascode, MOS Cascoded Current Mirror, MOS Current Mirror, and so on. When you select ALL in the Search for list and the Unfound objects filter in the Within list, an object listed by the first finder will not be repeated for the subsequent finders.

However, there is a possibility that when you run the constraint generators for the current cellview, this object might not be used by the corresponding constraint generator. For example, a net object might not be used if Add Guard Ring option is not selected in the constraint generator form. Consequently, the object remains unused because no other finder listed it.

Had the Unfound objects filter not been set, this object could have been listed for some other finder and could have been used to generate a constraint of a different type. So, it is noteworthy that the result of using the Unfound objects filter might not be a desired trade-off when you might prefer to generate a constraint of some other type on that object.

Normally, the results listed in the Circuit Prospector based on the selected category, finder, and filter criteria are not synchronized with the Constraint Manager and the schematic layout canvas. However, you can enable this type of synchronization by selecting the Sync Finder Results check box on the Circuit Prospector Options form that is displayed by one of the following ways:

As a result, when the Constrained Objects or Unconstrained Objects filter is selected, the Circuit Prospector finder reruns each time a constraint is created or deleted (manually or using the constraint generator).

By default, the Sync Finder Results check box is deselected.

2. Select Groups to Constraint

The results area in the lower section of the Circuit Prospector groups together each device, net, or pin that meet the search, matched expression and selection criteria. Here, you can choose those groups that you want to apply constraints to. By default, all results in the results table are highlighted and selected.

Selecting entries in either the results section of the Circuit Prospector, canvas, or the Navigator assistant simultaneously cross-highlights those devices, nets, or pins in the design cellview (the canvas) and other (applicable) assistants such as Constraint Manager (in schematic and layout views), Navigator, or Property Editor (see blue rectangles in the figure below). In addition, the selected result will automatically pan the object(s) in the canvas. This visually helps the designers to avoid creating contradicting constrains on the same device. When you select a device to create a constraint, if the Constraint Manager shows the respective constraint which already has this device, you can re-evaluate whether you need another constraint on this device or not. This overall improves the need of constraints in the design methodology.

At this point, you may optionally want to delete (filter) those result entries that you do not want to create constraints for. You can do this by selecting the result(s) using Ctrl+click, or you can delete the results that you do not want to constrain, by either pressing the Delete key or selecting the Delete button from the Circuit Prospector toolbar.

Once you have chosen the objects to be constrained and filtered (deleted), the results you can now move proceed to Step 4: Apply default action/ constraints to the selected objects.

Step 4: Apply default action/ constraints to the selected objects

The final step is to apply the default set of constraints (or any other default action such as adding relevant properties to the groups) that is associated with the finder that was run in step 2 on the selected results. It should be noted that users can also pick any relevant constraint from the drop-down list in the Constraint Manager toolbar if they want, instead of applying the default set of constraints. Further, the default action itself associated with a finder is customizable.

To do this:

  1. Click the Run Default Action drop-down list box in the Circuit Prospector toolbar.
    From here you will be displayed with a list of possible constraints that can be created in either the current cellview or for each sub-cell, based on the current Groups selection in the Circuit Prospector results table.
    The constraints available for creation in the drop-down list box will depend on the finder selected in the Circuit Prospector. This is because the constraint generator is specified as part of the finder definition.
  2. Select to create the available constraints (or any other relevant action) for either the current cellview or for each available sub-cell.
    The new constraints will be added to the Constraint Manager table. The figure below shows how to choose to create a constraint for the current cellview or each sub-cell.
Each Generate ... for Each Sub-Cell option will only be active if Run finders in all cellviews in the hierarchy is selected from the Run finder... option, as that is the only situation that such an action would be relevant.

Expanding Constraint Membership Directly on the Canvas

When creating a new constraint, from a selected group in the Circuit Prospector, you can expand the membership of the constraint to be created by selecting additional constraint members directly from the design canvas. This therefore allows you to create a new constraint based on a combination of member objects currently selected in the Circuit Prospector and also in the design canvas.

A warning message will be issued if you attempt to include canvas member objects, as part of a new constraint, when multiple groups are selected in the Circuit Prospector. This is because the Constraint Manager does not know which group (that will form a new constraint) that you want the additional canvas object selections to be part of.

Circuit Prospector Flow Summary

The following flow chart summarizes the steps involved in locating objects with the Circuit Prospector, and then generating constraints or running any action on them:

Edit Finder Form

The Edit Finder form is displayed when you select the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.

The Edit Finder form is used to edit existing finder or to create new finders. Finders are used to collect objects (instances, nets, or pins) that share certain common characteristics and/or connectivity.

Finders therefore are used to “find” groups of related objects that are required to be constrained. Finders can however also be used for debugging purposes, for example when checking for incorrect or inconsistent property settings or connectivity issues.

Each finder requires an iterator (see Edit Iterator Form) to iterate (repeatedly examine) the current cellview in a particular way. During this iteration process if the set Matching Expression evaluates to a non-nil result, then all objects (pins, nets, or instances) are collected together into groups based on the Matching Expression evaluation result.

GUI Item

Description

Name

The name of the currently selected finder.

Description

A description of the currently selected finder.

Search Using Iterator

Specifies which iterator the selected finder should use.

Select “...” to invoke Edit Iterator Form to select an iterator to be edited or created.

Matching Expression

An expression to be applied to the iterator to find the required items in the current cellview.

This expression can contain references to iterator specific variables. For example, the Same Cell Iterator (see Pre-Defined Iterators) will make available a device variable which will represent the current device in the iteration.

Properties

Displays the current properties for one or more currently selected instances.

Default Constraint Generator or Action

Specifies the constraint generator (or action) that should be associated with the currently selected finder.

Once the finder has run you can select the results from the Circuit Prospector results window and then select Generate Constraints from the Circuit Prospector toolbar and the finder’s default constraint generator will generate the constraints.

Select “...” to invoke Edit Generator or Action Form.

Edit Iterator Form

The Edit Iterator form is displayed when you select the “...” button to the right of the Search Using Iterator drop-down list box in the Edit Finder Form.

The Edit Iterator form allows for iterator details to be edited, registered, or deleted. The purpose of this form is to register an iterator function with the Circuit Prospector, providing it with a meaningful name and providing a description of what it used for.

Once registered an iterator can be used in one or more Circuit Prospector finders.
GUI Item Description

Iterators

Displays a list of the currently available Iterators.

Name

The name of the currently selected iterator.

Description

A description of the currently selected iterator.

The iterator description should list all variables made available during expression evaluation. For example, the Same Cell Iterator will make a “device” available which represents the current device in iteration. The finder’s matching expression (see Edit Finder Form) can then reference this variable, for example ciIsDevice(device "fet").

Iterator

The function name of the SKILL iterator function (see the Custom Constraints Functions chapter in the Virtuoso Unified Custom Constraints SKILL Reference).

A SKILL iterator function must be defined to take two arguments: cellview and finderExpr.

  • cellview is the current cellview.
  • finderExpr is the finder expression to be evaluated.

The function must return a list containing sub-lists of database objects (instance, nets, and pins). The sub-lists represent groups of objects that have the same finder expression evaluation result. For example, where a finder expression of “when(ciIsDevice(device "fet") ciNetOnTerm(device \"G\"))”, the Same Cell Iterator will return groups of fets that share the same net on their gate terminal. For example, list( list(fet1 fet2 fet3) list(fet4 fet5) list(fet6) ).

Supports Flattened Hierarchy

Specifies whether the currently selected iterator should support a flattened hierarchy.

The Supports Flattened Hierarchy check box is just a read only indicator for both the predefined and user defined iterators.

Add

Adds a new iterator to the Iterators list.

Delete

Deletes the currently selected iterator.

Edit Generator or Action Form

The Edit Generator or Action form (shown below) is displayed when you select the “...” button to the right of the Default Generator or Action section in the Edit Finder Form.

Constraint generators are SKILL expressions that generate one or more constraints.

The Edit Constraint Generator or Action form allows constraint generators to be edited, registered, or deleted from the Circuit Prospector. A constraint generator has a Name, detailed Description, and an Expression for generating constraints.

GUI Item

Description

Generators or Actions

Lists all of the available actions and Constraint Generators.

Constraint generators are associated with finders as the default constraints for that finder. For example, the Active Same Cell finder has a default constraint generator of “Same Cell Name - Group + Relative Orientation”.

See also Pre-Defined Constraint Generators.

Name

Name of the currently selected constraint generator.

Description

Description of the currently selected constraint generator.

Expression

An expression used to generate constraints.

The expression can contain calls to the constraints SKILL function (see the Custom Constraints Functions chapter in the Virtuoso Unified Custom Constraints SKILL Reference) or any other functions that create constraints.

The variables “instNetsPins” and “cache” are made available for use when the expression is evaluated.

Where:

  • instNetsPins is a list containing three sub-lists for the instances, nets, and pins to be constrained.
  • cache is a reference to the constraints cache.

For example, the “Matched Parameters” constraint expression is:

ciConCreateExpanded(cache ‘matchedparameters ?members append(insts pins ?verbose nil)

The above expression should evaluate to t | nil to indicate the success of constraint generation.

See also Custom Constraint Generators in the Virtuoso Unified Custom Constraints Configuration Guide.

Add

Adds a new constraint generator to the Constraint Generators list.

Delete

Deletes the currently selected constraint generator.

Capture Circuit Structure Form

You can capture new structures using the Capture Circuit Structure form which is accessible from the Capture Structure menu item on the Circuit Prospector toolbar.

Clicking the Capture Structure menu item displays the Capture Circuit Structure form, as shown below.

For a list of existing, pre-defined structures, see Structures.

The contents of the Capture Circuit Structure form are described below:

GUI Item

Description

Name

Specify the name of the structure to be created.

Type

Specify the type of structure to be created.

Description

Enter a detailed description of the structure to be created.

Expression (insts, nets...)

Enter an optional and extra match expression that applies to all instances, nets, or pins of the found structure.

Objects/Match Expression/Repeatable table

Displays the structure content and connectivity information, including entries for instances, nets, pins and constraints that are associated with the current structure.

Expanding an instance (Insts) in the table displays the instance terminals connected to nets in the structure (terminals that are not part of the structure are not listed). Associated with each instance is also a Match Expression that captures the important properties for that instance within the captured structure.

Double-clicking the matched expression for an instance displays the Edit Match Expression Form.

The default instance match expression is libName/cellName.

Expanding any Constraints item in the table will display all the constraints that exist for the captured nets, instances and pins.

If you expand insts or nets in the Object column, check boxes will be displayed in the Repeatable column for each instance or net. Checking any check boxes here will confirm that the particular insts/nets can be repeated N times in the structure (for an example of use see Using Repeatable on a Captured Structure).

During pattern matching the basic structure will be grown repeatedly until it can no longer be matched.

Edit Expressions

Invokes the Edit Match Expression form where you can edit a match expression for a captured structure. From this form, you can choose relevant properties to add to the expression.

Update From Selected

Choose to add further instances, nets, or pins to the structure, by selecting them on the canvas, before selecting the Update From Selected button.

Recapture Constraints

Lets you add further constraints, created in the Constraint Manager assistant, to the captured structure.

Delete

Deletes any constraints, instances, net, or pins that are currently selected in the Object/Match Expression table from the structure.

Capturing New Structures

Before capturing a new structure it is recommended that you enter constraints for the devices of the structure. These constraints will then be captured with the structure and will become the default constraints for that structure.

To capture new structures:

  1. Select the instances and/or pins on the device canvas that you want to capture.
    Wires do not need to be selected as the connectivity between the selected objects will be captured automatically.
  2. Select the Capture Structure button on the Circuit Prospector assistant toolbar.
    This displays Capture Circuit Structure Form.
  3. Enter the Name of the structure.
  4. Enter the Type of the structure.
  5. Enter a Description of the structure.
  6. Optionally, edit any matched expressions for current instances (Insts).
    For more information, see the Edit Match Expression Form and the Edit Terminal Name Expression Form.
  7. Optionally, choose to add further instances, nets, or pins to the structure by selecting them on the canvas and then selecting the Update From Selected button.
  8. Optionally, choose to add further constraints to the captured structure using The Constraint Manager Assistant.
    Once these constraints have been created, select the Recapture Constraints to update the constraints in the Objects/Match Expression table.
  9. Click OK to capture the structure.
    The structure is now saved to the local .cadence directory and will be listed in the list of finders for the current category (in the Search for drop-down list box).
Before a structure is saved to disk, a connectivity check is performed to ensure that each instance in the structure is connected to at least one other instance in the structure. This is an essential requirement so that the structure recognition algorithm can find the structure. If there are any problems with connectivity, then an error pop-up window is displayed and the connectivity of the structure will need to be changed before it can be saved.
The captured structure device expressions have the ciMatchedInsts variable. This variable is a list of the device database IDs that have been matched for the structure so far, for example, to ensure all the devices matched for t. Use the addParallelDevices environment variable to control inclusion of parallel devices in the structures during structure matching.

Editing Structures

To edit a structure:

  1. Open the schematic from where the structure was captured.
  2. Select the structure from the list of finders in the Search for drop-down list box.
    Capture Circuit Structure Form will be displayed.
  3. Optionally, edit the Name of the structure.
  4. Optionally, edit the Type of the structure.
  5. Optionally, edit the Description of the structure.
  6. Optionally, edit any matched expressions for current instances (Insts).
    For more information see Edit Match Expression Form.
  7. Optionally, choose to add further instances, nets, or pins to the structure by selecting them on the canvas and then selecting the Update From Selected button.
  8. Optionally, choose to add further constraints to the captured structure using The Constraint Manager Assistant.
    Once these constraints have been created, select the Recapture Constraints to update the constraints in the Object/Match Expression table.
  9. Click OK to save the edited structure.

Deleting Structures

To delete a structure:

  1. Select the structure you want to delete from the Search for drop-down list box in the Circuit Prospector assistant.
  2. Click the adjacent Delete Finder (cross) button to delete the selected structure.
    A pop-up message asking you to confirm deletion is displayed.
  3. Select OK to confirm structure deletion, or select Cancel to cancel structure deletion.
    The structure will be removed from the Search for drop-down list box.

Using Repeatable on a Captured Structure

Checking any of the check boxes in the Repeatable column of Capture Circuit Structure Form will confirm that specific insts/nets can be repeated N times in the structure. See the Edit Terminal Name Expression Form for how to specify the way in which repeated device terminals should be connected.

For example:

Edit Match Expression Form

If you want to edit a match expression for a captured structure, double-click the displayed instance matched expression in the Capture Circuit Structure form or select Edit Expressions in the same form. This will display the Edit Match Expression form which allows you to utilize an integrated property editing facility. From here, you can choose relevant properties and add them to the expression.

Matched expressions can also utilize pre-defined helper functions, for example ciIsDevice, to filter the type of objects found.

Figure 2-5 The Edit Match Expression form

Edit Terminal Name Expression Form

You can use the Edit Terminal Name Expression form to edit terminal expressions and define connectivity between repeatable instances.

Example of How to Capture A Repeatable Structure Utilizing the Edit Terminal Name Expression Form

The following example describes how to capture a resistor network that compromises of a number of serial resistors (R0, R1, R2, and so on).

  1. Only the first two resistors in such a chain require to be selected in the design canvas (for example, R0 and R1).
    R0 will be considered to be the root part of the structure and R1 considered to be the repeatable part of that chain.
    Figure 2-6 Selecting Resistors R0 and R1 in the Design Canvas
  2. Click the Capture Structure option in the Circuit Prospector toolbar.
    The Capture Circuit Structure form is displayed.
    Figure 2-7 The Capture Circuit Structure Form with Instances R0 and R1 Expanded
  3. Ensure that the R0 and R1 instances are expanded and that the Repeatable check box for R1 is selected (as R1 is to be repeatable).
    The expansion of the R1 instance will display the terminals of that instance and the nets that they are currently connected to.
    Each terminal can now be selected, and its respective expression edited in the Edit Terminal Name Expression form. That expression will define how the connectivity between the repeatable instance and the root, or previous, instance must be set.
  4. Select a terminal to be edited.
  5. Click the Edit Expression button.
    The Edit Terminal Name Expression form is displayed.
    Figure 2-8 The Edit Terminal Name Expression Form
  6. In the Edit Terminal Name Expression form you could now, for example, define that:
    • the PLUS terminal of Rn be connected to the MINUS terminal of Rn-1 (that is, PreviousInsTerm: MINUS).
    • the MINUS terminal of Rn must be connected to a NewNet (a net that will not be connected to any other device terminal in the structure) or DontCare net (may or may not be connected to an existing device terminal in the structure).
      For more information on the DontCare option, see Figure 2-10 DontCare Repeated InstTerm Connection.
    • the B terminal must be connected to an ExistingNet called vdd!.
    • the B terminal must be connected to a NewSharedNet, meaning that two device terminals sharing the same net should share a new repeated net when those devices are repeated.
      For more information on the NewShareNet option, see Figure 2-11 NewShareNet Repeated InstTerm Connection.
  7. When all expressions have been correctly defined, ensure that a Name has been entered in the Capture Circuit Structure form.
  8. Click the OK button in the Capture Structure form and the new finder will automatically find all chains of serial resistors in the current schematic.
    Figure 2-9 The Circuit Prospector Assistant Displaying the Capture of a Repeatable Structure (R0-R5)
    Figure 2-10 DontCare Repeated InstTerm Connection

Figure 2-11 NewShareNet Repeated InstTerm Connection

Customization of the Circuit Prospector

The following table summarizes the current categories, finders, and default (associated) constraints that are available in the Circuit Prospector.

For more information see:

Categories

See also Creating and Editing Categories in this book and Creating New Categories in the Virtuoso Unified Custom Constraints Configuration Guide.

Categories are groups of related Finders (search algorithms) that are used to store structural definitions.

Finders search for devices/pins/nets that match certain customizable search criteria, for example common circuit structures, related devices (such as same size, area, or type), devices with particulars characteristics or connectivity, symmetrical devices/nets/pins, or devices with particular properties. The group of finders associated with a category represent a grouping of related finders, for example all fet related finders and/or a constraint creation flow (for example, create groups, find symmetries, and find structures).

By default, the Circuit Prospector provides you with a set of pre-defined categories that can be listed by clicking the Category drop-down list box (as shown below).

The following pre-defined categories are displayed in the Category drop-down list box by default:

The following pre-defined categories are also available for you, but are disabled by default:

To use any of these disabled pre-defined categories, you need to enable them by using the ciEnableAssistant SKILL function. The categories thus enabled start showing in the Category drop-down list box after you close the current Virtuoso Schematic Editor XL window and launch it again from Virtuoso. For example, if you run the following SKILL commands in the CIW, the Category drop-down list box is updated as highlighted in the figure below:

ciEnableAssistant("Properties" t)
ciEnableAssistant("Placement Constraints" t)
ciEnableAssistant("Routing Constraints" t)
ciEnableAssistant("Clusters" t)
ciEnableAssistant("Matched Parameters" t)
ciEnableAssistant("Modgens" t)

The ciEnableAssistant SKILL function can also be used to disable any pre-defined category (including the ones enabled by default). For example, when you run the following SKILL commands in the CIW, the specified categories get disabled and the Category drop-down list box gets updated accordingly (refer to the figure below):

ciEnableAssistant("Devices" nil)
ciEnableAssistant("Routing Constraints" nil)
ciEnableAssistant("Clusters" nil)

Rapid Analog Prototype

The Rapid Analog Prototype (RAP) category in the Circuit Prospector contains all the finders/generators required to automatically constrain a design with just a few mouse clicks. The resulting constraints result in good initial placement and routing from which layout effects (parasitic and device effects) can be extracted and taken into account during simulation early in the circuit design phase. Associated with the finders are dedicated modgen generators for common structures that automatically generate optimized structure specific modgens. These generators capture layout expertise and allow this expertise to be automatically re-applied to each structure in a design.

In addition, it is fully customizable to allow you to generate modgens to your particular requirements. It also includes template parameters for allowing modgen re-configuration in schematic and layout without the need to bring up the specialized Modgen Editor.

Combining these devices into modgens reduces the number of devices and constraints that the Analog Place and Route tools have to work with leading to faster run times, better results, and more predictability.

The finders/generators in the RAP category will generate all the constraints required to achieve a good initial (prototype) layout.

Most generators in the RAP category are also available in the Constraint Manager assistant under the Rapid Analog Prototype sub-menu (the image below shows the available generators.) This allows you to manually select the required structures on the schematic or layout canvas and run the required RAP generator on them.

Prototyping Flow using the RAP Finders

The RAP finder-based prototyping flow requires you to perform the following simple steps.

  1. Select ALL from the Search for drop-down list box to run all the finders in the RAP category.
  2. Then, run the default constraint generator for the RAP results. Constraint Generator dialogs will popup for each RAP constraint generator allowing you to configure the generator parameters for the associated set of devices. The device names are displayed in the title of the dialog box.
    The dialog box normally has four buttons: OK, Cancel, Defaults, Apply, and Help.
    When you click the OK button, the specified values get saved as the default values for the consecutive access of the same dialog box. For example, you created a MOS Current Mirror constraint, changed the setting of the Abut All check box, and clicked OK on the dialog box. Then, when you create a MOS Current Mirror constraint again on a different set of instances, the dialog box remembers the parameter values saved last. If the parameter values specified by you are incompatible with the last save, the default ones are set instead.
    The Defaults button can be used to rollback any user-defined values in the fields to their valid default values.
    When you select multiple RAP results from the list and click a constraint generator button, the form provides additional OK ALL and Cancel ALL buttons.
    The OK ALL button allows you to accept the default values for all subsequent constraint generators and the dialog boxes will not popup for those. Here, the default values depend on the last values set by the generator on a template.
    The Cancel ALL button cancels the current constraint generator and all subsequent constraint generators.
    If these additional buttons are displayed and you choose to click the Apply button, the OK ALL and Cancel ALL buttons disappear from the dialog box. In addition, different dialog boxes for each selected RAP result become visible for entering the required constraint parameters, as shown in the figure below.
    Optimized modgens are created for each type of structure is found, including Differential Pair, Current Mirror, and Large mfactor devices. The modgens capture analog design/layout engineer expertise for each type of modgen being created, for example, Rows/Columns, Patterns, Dummies, Guard Rings, and Body Contacts. In addition, Symmetry constraints are created for symmetrical devices and nets, Rail, and Net Priority, where as, Process Rule Override constraints are created for the supply nets. Vertical Orientation constraints are created on all devices and the pins are aligned on the cell boundary according to their placement in the schematic.
    At this point, with modgens created in the schematic it is possible to re-simulate the design taking into account the LDE effects on the devices in the modgens. For more information on LDE, refer to the Simulating Designs with LDE section in the Virtuoso ADE Assembler User Guide.
  3. Now, click Launch – Layout XL, select Create New in the Layout group box, and click OK to open the New File form. In this form, specify a new View name and Application to open with before clicking OK. These steps are shown in the figure below.
  4. To generate layout representations of the schematic design components, select the Connectivity – Generate – All From Source option.
  5. (IC6.1.8 Only) Start analog automatic placement by selecting the Place – Analog – Automatic Placement option.
    The automated placement result is displayed, as shown below.
    Constraining the critical devices as Modgens not only helps capture design intent more accurately but also leads to better overall placement and faster convergence. At this point, with devices and modgens placed it is possible to re-simulate the design taking into account the LDE effects on the placed devices. For more information on LDE, refer to the Simulating Designs with LDE section in the Virtuoso ADE Assembler User Guide.
  6. Start Analog Automatic Routing by selecting the Route – Automatic Routing – any of the given submenu options. The figure below shows how automatic routing is done for all nets when you select the All Nets submenu.
  7. Run PVS-CV and re-simulate the design with parasitics. For more information, refer to the An Analog Simulation Flow using PVS LDE section in the Virtuoso Parasitic Aware Design User Guide.

Template Parameters

By default, all RAP constraint generators that generate modgens creates the modgens within templates. The templates have the same parameters as those specified for the constraint generator that generated the modgen. You can modify the template parameters after the modgen has been created, which will trigger the modgen to be regenerated based on the new parameter settings. It is also possible to modify the template parameters within VSE XL, VLS XL, and the modgen editor.

If the Add GuardRing option is selected, the guard ring associated with the modgen will also be added to the template.

Changing the Style template parameter from DoubleRow to SingleRow re-invokes the Current Mirror constraint generator to regenerate the modgen for the Current Mirror on a single row with the appropriate interdigitation pattern.

RAP Finders

All RAP Finders and their associated constraint generators are detailed below.

Devices Finder

Description

MOS Cascode

Lists the following types of MOS transistors:

  • Transistors that share the same gate
  • Transistors that are connected to each other through a common source, as illustrated in the following figure:

When you generate a modgen constraint for the cascoded MOS transistors, all connected transistors are abutted in the layout. This results in an optimum and compact placement of the MOS transistors.

It will generate patterns similar to the MOS Current Mirror based on the option you select from the Style drop-down list box in the Module (Cascode MOS Transistors) form.

As shown in the figure below, the following options are available in the Style drop-down list box:

  • Style (Auto): Automatically picks the best number of rows based on the aspect ratio of the different possible row counts.
  • Style (SingleRow): Sorts the devices by mfactor based on the number of fingers. It places the largest mfactored devices at the two ends of a modgen and the smaller mfactored devices in between them.
  • Style (DoubleRow): It is same as the SingleRow option, but it places the mfactored devices in two rows.
  • Add Dummies: Controls whether to add dummies.
  • Abut All: Controls device abutment. When selected, abutment of devices is enabled.

  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options shown in the figure below.
    • Trim Trunks: This check box is selected by default. It means that while routing, both the ends of a trunk will be trimmed to the first twig on that trunk. If you deselect this check box, trunk trimming gets disabled and the length of the trunk will be the same as the width of the modgen.
    • Gate Layer: Select a gate layer on which a horizontal trunk should be created.
    • Gate Width: Enter a value that defines the gate width of the horizontal trunk when it is created.

    • Gate Offset: Enter the required gate offset (spacing) between horizontal trunks in the same channel.
    • Source Layer: Select a source layer on which a horizontal trunk should be created.
    • Source Width: Enter a value that defines the source width of the horizontal trunk when it is created.
    • Source Offset: Enter the required source offset (spacing) between horizontal trunks in the same channel.
    • Drain Layer: Select a drain layer on which a horizontal trunk should be created.
    • Drain Width: Enter a value that defines the drain width of the horizontal trunk when it is created.
    • Drain Offset: Enter the required drain offset (spacing) between horizontal trunks in the same channel.
    • Bulk Layer: Select a bulk layer on which a horizontal trunk should be created.
    • Bulk Width: Enter a value that defines the bulk width of the horizontal trunk when it is created.
    • Bulk Offset: Enter the required bulk offset (spacing) between horizontal trunks in the same channel.
    • Channel0 Device Spacing: Specify the spacing between the last (bottom) trunk in the channel and the devices immediately below it.
    • Channel1 Device Spacing. Specify the spacing between the first (top) trunk in the channel and the devices immediately above it.

MOS Cascoded Current Mirrors

It will generate a pattern similar to the MOS Current Mirror with an alternate between current mirror device and cascoded device. Select the required pattern from the Style drop-down list box in the Module (Cascoded Current Mirror) form.

As shown in the figure below, the following pattern options are available in the Style drop-down list box:

  • Style (Auto): Automatically picks between SingleRowInterdigitated, SingleRow, or DoubleRow styles based on the aspect ratio of the different possible row counts.
  • Style (SingleRowInterdigitated): Places all the devices in a single row. The devices are processed in a schematic order. The mfactored device and its cascode are added in an interdigitated alternating pattern.

  • Style (SingleRow): Places all the devices in a single row. The devices are processed in a schematic order. The mfactored device and its cascode are added in an alternating pattern.
  • Style (DoubleRow): Creates a two row pattern, which orders the devices as they are in the schematic.
  • Add Dummies: Sets the standard dummies option.
  • Guard Ring: Controls whether a guard ring should be added. Use the Guard Ring Settings button to view and set the standard guard ring options shown in the figure below. The standard guard ring options available in the Guard Ring group box are the same as discussed in the Adding a Guard Ring Around Generated Modgen section of Chapter 1, “The Constraint Manager Assistant.”

  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options. For description of the available standard routing options, refer to Routing explained with the MOS Cascode RAP finder description.

This finder group contains at least four devices registered as "fet". For more information, refer to the MOS Cascoded Current Mirror section of the Structure finder.

MOS Cascoded Current Mirrors2

It has a same pattern as MOS Current Mirror with an alternate between current mirror device and cascoded device.

This finder group contains at least four devices registered as "fet". For more information, refer to the MOS Cascoded Current Mirror2 section of the Structure finder.

MOS Current Mirror

This finder controls the modgen generation. As shown in the figure below, it has the following options in the Style drop-down list box:

  • Style (Auto): Automatically picks the best number of rows based on the aspect ratio of the different possible row counts.

  • Style (SingleRow): Sorts the devices by mfactor based on the number of fingers. It places the largest mfactored devices at the two ends of a modgen and the smaller mfactored devices in between them.
  • Style (DoubleRow): It is same as the SingleRow option, but it places the mfactored devices in two rows.
  • Add Dummies: Sets the standard dummies option.
  • Guard Ring: Controls whether a guard ring should be added. Use the Guard Ring Settings button to view and set the standard guard ring options shown in the figure below. The standard guard ring options available in the Guard Ring group box are the same as discussed in the Adding a Guard Ring Around Generated Modgen section of Chapter 1, “The Constraint Manager Assistant.”
  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options. For description of the available standard routing options, refer to Routing explained with the MOS Cascode RAP finder description.

This finder group contains at least two devices registered as "fet". For more information, refer to the MOS Current Mirror section of the Structure finder.

If the Add Dummies check box is checked on the Constraint Generator Dialog, dummy devices will be added to either end of each row of the generated modgen. Alternatively, you can set the currentMirrorIncludeDummies environment variable to t.

The first device in the matched structure acts as the reference device for the dummy device. The dummy device will have the same libName, cellName, width, length, fingerCount, and fingerWidth as the reference device.

The net to be used to connect the dummy device terminals are be determined from the bulk connectivity of the devices in the matched structure, or the power/ground nets connected to the devices in the matched structure if the devices have no bulk.

MOS Differential Pair

Lists the regular differential pair structures. If the diffPairRequireSourceNotSupply environment variable is not set, all differential pair structures will be recognized and listed. However, if you set this environment variable to t, the differential pair structures will be listed only if the source connection of the structure is not connected to a supply net.

It will generate patterns illustrated below based on the option you select from the Style drop-down list box in the Module (Diff Pair) form.

As shown in the figure below, the following options are available in the Style drop-down list box:

  • Style (Auto): Automatically picks between row1 and row2symmetric styles based on the device mfactors.

  • Style (row1): Simple one row alternating pattern.

  • Style (row2symmetric): If the mfactor is a multiple of 4 then a 2 row cross quad pattern will be used.

If the mfactor is not a multiple of 4 and Auto/row2symmetric style is selected, then a 2 row alternating pattern (ABAB…) will be used.

  • Add Dummies: Sets the standard dummies options.
  • Guard Ring: Controls whether a guard ring should be added. Use the Guard Ring Settings button to view and set the standard guard ring options shown in the figure below. The standard guard ring options available in the Guard Ring group box are the same as discussed in the Adding a Guard Ring Around Generated Modgen section of Chapter 1, “The Constraint Manager Assistant.”
  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options. For description of the available standard routing options, refer to Routing explained with the MOS Cascode RAP finder description.

For more information, refer to the MOS Differential Pair section of the Structure finder.

MOS Differential Pair - Cross Coupled

Lists the cross-coupled differential pair structures. Such structures are similar to the regular differential pair structures, but additionally the gate terminal of each transistor connects to the drain terminal of the other transistor (the two sources are connected as with any differential pair structure).

If the crossCoupleDiffPairRequireSourceNotSupply environment variable is not set, all cross-coupled differential pair structures will be recognized and listed. However, if you set this environment variable to t, which is the default, the cross-coupled differential pair structures will be listed only if the source connection of the structure is not connected to a supply net.

This finder generates same patterns as the MOS Differential Pair finder based on the option you select from the Style drop-down list box in the Module (Diff Pair - Cross Coupled) form. The Style drop-down list provides the same options as the MOS Differential Pair finder.

For more information, refer to the MOS Differential Pair section of the Structure finder.

Passive Arrays

Groups together series/parallel connected resistors and capacitors. The Constraint Generator generates a modgen for each group.

  • Style (auto): Automatically picks the best pattern based on the mfactor to give the squarest modgen. For example, if there are four devices, you will have a 2x2 pattern (a gap might be there if the number of devices is not a power of 2).
  • Style (Row1..RowN): Allows you to pick num rows, where N is the mfactor.

  • Add Dummies: Standard dummies option, as Current Mirror.
  • Guard Ring: Controls whether a guard ring should be added. Use the Guard Ring Settings button to view and set the standard guard ring options shown in the figure below. The standard guard ring options available in the Guard Ring group box are the same as discussed in the Adding a Guard Ring Around Generated Modgen section of Chapter 1, “The Constraint Manager Assistant.”
  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options. For description of the available standard routing options, refer to Routing explained with the MOS Cascode RAP finder description.

Active Same Cell large mfactor

Defines large mfactor device as mfactor*fingerCount > 5 that can be modified by you.

  • Style (Auto): Picks the best pattern automatically based on the mfactor to give the squarest modgen with no gaps.
  • Style (row1 .. rowN): Allows you to pick number of rows. Here, N is the mfactor.

  • Guard Ring: Controls whether a guard ring should be added. Use the Guard Ring Settings button to view and set the standard guard ring options shown in the figure below. The standard guard ring options available in the Guard Ring group box are the same as discussed in the Adding a Guard Ring Around Generated Modgen section of Chapter 1, “The Constraint Manager Assistant.”
  • Routing: Controls whether pin to trunk routing should be enabled. Use the Route Settings button to view and set the standard routing options. For description of the available standard routing options, refer to Routing explained with the MOS Cascode RAP finder description.

Symmetric Instance Pairs - By Connectivity

Groups pairs of instances that are determined to be symmetric based on their connectivity. This finder searches for only symmetric instance pairs.

The Symmetric Instance Pairs - By Connectivity and Symmetric Net Pairs iterators initially look for symmetrical triggering pairs in the current schematic. From these pairs, they will propagate symmetries along the nets and devices that are connected to the triggering pairs. There are three types of symmetrical triggering pairs:

  1. A pair of instances or nets with an existing symmetry constraint.
  2. A differential pair made up of fet and bjt devices (see below on how to define both of these categories).
  3. A pair of instances with Active Same Cell Name and Same Size fet and bjt devices, with mirrored orientation, aligned on the same Y coordinate.

Note:
  • The symmetries are propagated through nets using terminal names defined for each active device.
  • Symmetries are also transmitted to, and propagated through, passive devices.
  • To be a symmetrical pair, both instances must have the same cell name and size.
  • Symmetries for instances, or nets, are converted to self-symmetries when there is only one member on the path for symmetry propagation.
  • fets, bjts and passive must be registered for each PDK for the Circuit Prospector to identify symmetries.

To see the examples on fet and bjt devices, refer to the Example offet and bjt devices defined: section in the Structure finder.

Capacitor Cluster

Finds all capacitors to generate cluster constraints for them. This is necessary to prevent capacitors being placed on top of other devices.

Vertical Orientation

Sets the specified vertical orientation (R0/MY/MX/R180) constraints on all selected fets and bjts devices.

Positive/Negative Supply

Groups the positive or negative supply nets based on the type of finder chosen. Positive and negative supply nets are identified by matching their names against the nets registered as power/ground through ciRegisterNet() or through their sigTypes.

Using these two RAP finders, you can generate high priority constraints for the current cellview or each sub-cell. When you click the required constraint generator, one of the following forms is displayed depending on the chosen finder.

For each power or ground net, the following constraints are created:

  • A Net Priority constraint
  • A Rail constraint with the chosen layer, width, side, and offset

Nets (Symmetry By Connectivity)

This option enables you to create symmetry constraints on symmetrical net/inst pairs or self-symmetric nets/insts.

Top Pins (Alignment)

Creates an alignment constraint on all schematic pins that are placed on the top of the schematic.

Bottom Pins (Alignment)

Creates an alignment constraint on all schematic pins that are placed on the bottom of the schematic.

Left Pins (Alignment)

Creates an alignment constraint on all schematic pins that are placed on the left of the schematic.

Right Pins (Alignment)

Creates an alignment constraint on all schematic pins that are placed on the right of the schematic.

Enforce Precedence

The Enforce Precedence finder:

  • Enforces a single symmetry line.
  • Moves symmetry constraint from two symmetrical devices onto the modgens they are contained within.
  • Moves self-symmetry from a device to the modgen it is contained within if it is the only device in that modgen.
  • Deletes cluster members if the members are within modgens.
  • The alignment constraint on symmetrical pins is removed to ensure that the pin symmetry takes precedence.

ALL

Executes all finders of the current category sequentially in the order of their listing in the Search for list and displays the corresponding results in the browser.

Structures

Structures can be Devices, Nets, or Pins.

Structure finders do not work across hierarchical boundaries, as most structures only exist within the same cell.

All Finders related to structures are detailed below. Finder order is important and must follow the order given.

Structure finders can use “insts”, “nets”, and “pins” (lists of database objects found by structures finders) as variables for matched expressions. For example, for a MOS Differential Pair you could use:

car(insts)->cellName == cadr(insts)->cellName

Although the structures listed below only act on Devices, it does not limit the scope of what you can create.

For information on adding new structures, see Capture Circuit Structure Form.

For information on mapping structures, see ciMapTerm, ciPrintMappedParams, and ciGetDeviceTermName.

Structures Finder Description

MOS Cascode

Finds cascoded MOS transistor structures.

This finder group contains at least two devices registered as "fet".

G0 => D0
Gi => Gi+1  eg: G0->G1->G2->etc.
Si => Di+1  eg : S0->D1 ; S1->D2 ; etc.

MOS Current Mirror

Groups devices that form a MOS current mirror structure.

This finder group contains at least two devices registered as "fet".

S1 = S2 (=S3, etc.)
B1 = B2 (=B3, etc.)
G1 = G2 (=G3, etc.)
D1 != D2 (!=D3, etc.)
D1 = G1 XOR D2 = G1 (XOR D3 = G1, etc.)
Use the currentMirrorIncludeDummies environment variable to control the inclusion of dummies in Current Mirror structures.

MOS Cascoded Current Mirror

Groups devices that form a cascoded MOS current mirror structure.

This finder group contains at least four devices registered as "fet".

G1a = G2a ( = G3a, etc.)
G1b = G2b ( = G3b, etc.)
B1a = B2a ( = B3a, etc.)
B1b = B2b ( = B3b, etc.)
D1a != D2a ( != D3a, etc.)
D1b ! = D2b ( != D3b, etc.)
D1a = S1b
D2a = S2b
(D3a = S3b, etc.)
G1a != G1b
S1a != S1b
D1a != D1b
D1b = G1a  XOR  D2b = G1a  (XOR D3b = G1a, etc.).

MOS Cascoded Current Mirror2

Groups devices that form a cascoded MOS current mirror structure with at least one of the leading pairs being diode connected.

This finder group contains at least four devices registered as "fet".

G1a = G2a ( = G3a, etc.)
G1b = G2b ( = G3b, etc.)
B1a = B2a ( = B3a, etc.)
B1b = B2b ( = B3b, etc.)
D1a != D2a ( != D3a, etc.)
D1b ! = D2b ( != D3b, etc.)
D1a = S1b
D2a = S2b
(D3a = S3b, etc.)
G1a != G1b
S1a != S1b
D1a != D1b
(D1a = G1a XOR D2a = G1a (XOR D3a = G1a, etc.)) (D1b = G1b XOR D2b = G1b (XOR D3b = G1b, etc.))

MOS Transmission Gate

Groups devices that form a MOS transmission gate structure.

This finder group contains two devices:

  • Transistor M1 that must be registered as an "nfet".
  • Transistor M2 that must be registered as an "pfet".

The names of their terminals must be registered as "drain", "gate", and "source" respectively.

Their respective drain, source, and gate terminals must be connected as follows: 

D1 == D2 
S1 == S2 
G1 != G2

MOS Differential Pair

Groups devices that form a MOS differential pair structure.

This finder is based on terminals and is used for matching all electrical parameters (fingers width, fingers, length, multiplier). Cell name must match.

S1 = S2 and not connected to power net.

B1 = B2
G1 != G2
D1 != D2
G1 != D1
G1 != S1
D1 != S1
G2 != D2

There is an equivalent mapping for bjt devices:
("S" -> "E", "B" -> null, "G" -> "B", "D" -> "C")

Structure finders can use “insts”, “nets”, and “pins” (lists of database objects found by structures finders) as variables for matched expressions. For example, for a MOS Differential Pair, you could use:

car(insts)->cellName == cadr(insts)->cellName

MOS Differential Pair - Cross Coupled

Groups devices that form a MOS cross-coupled differential pair structure.

This finder group contains two devices registered as "fet".

D1 = G2
D2 = G1
S1 = S2
B1 = B2
D1 != G1
D1 != S1
G1 != S1
D2 != G2
There is an equivalent mapping for bjt devices: ("S" -> "E", "B" -> null, "G" -> "B", "D" -> "C")

MOS Parallel

Groups devices that form a MOS parallel structure.

This finder group contains at least two devices registered as "fet".

S1 = S2
B1 = B2
G1 = G2
D1 = D2

There is an equivalent mapping for bjt devices:
("S" -> "E", "B" -> null, "G" -> "B", "D" -> "C")

MOS Active Load

Groups devices that form a MOS active load structure.

This finder group contains at least two devices registered as "fet".

D1 = one of differential pair D

D2 = the other differential pair

B1 = B2

G1 = G2

S1 = S2 (and be connected to a power net)

D1 = G1 XOR D2 = G1

MOS Inverter

Groups devices that form a MOS inverter structure.

This finder group contains two devices.

  • Transistor M1 that must be registered as an "nfet".
  • Transistor M2 that must be registered as an "pfet".

The names of their terminals must be registered as "drain", "gate", and "source" .

Their respective drain, source and gate terminals must be connected as follows: 

G1 = G2
D1 = D2
S1 != S2

S1 connected to power supply

S2 connected to a different power supply

Symmetric Instance Pairs - By Pre-selection

Groups pairs of instances that are geometrically symmetrical about the center of the current selected set.

Instances in geometrically symmetrical regions of the schematic will need to be selected prior to running this finder.

Symmetric Instance Pairs - By Connectivity

Groups pairs of instances that are determined to be symmetric based on their connectivity. This finder searches for only symmetric instance pairs.

The Symmetric Instance Pairs - By Connectivity and Symmetric Net Pairs iterators initially look for symmetrical triggering pairs in the current schematic. From these pairs, they will propagate symmetries along the nets and devices that are connected to the triggering pairs. There are three types of symmetrical triggering pairs:

  1. A pair of instances or nets with an existing symmetry constraint.
  2. A differential pair made up of fet and bjt devices (see below on how to define both of these categories).
  3. A pair of instances with Active Same Cell Name and Same Size fet and bjt devices, with mirrored orientation, aligned on the same Y coordinate.

Note:
  • The symmetries are propagated through nets using terminal names defined for each active device.
  • Symmetries are also transmitted to, and propagated through, passive devices.
  • To be a symmetrical pair, both instances must have the same cell name and size.
  • Symmetries for instances, or nets, are converted to self-symmetries when there is only one member on the path for symmetry propagation.
  • fets, bjts and passive must be registered for each PDK for the Circuit Prospector to identify symmetries.
    Example of fet and bjt devices defined:
    ciRegisterDevice("fet"
       '((nil "nmos" nil)
         (nil "pmos" nil)
         (nil "nmos1v" nil)
            ...
     ))
     ciRegisterDevice("bjt"
        '((nil "npn" nil)
          (nil "pnp" nil)
          (nil "vpnp2" nil)
            ...
     ))
    Terminal names must be registered in the respective list of terminal place-holder names. The first one that is found from the list is used by the iterator.

  • “drain”, “gate”, “source”, and “bulk” are used for fet devices.
  • “collector”, “base”, “emitter”, and “bulk” are used for bjt devices.
    For example:
    ciMapTerm(("drain" '("d" "drain" "DRAIN" "Drain")) ciMapTerm("gate" '("g" "gate" "GATE" "Gate")) ciMapTerm("source" '("s"  "source" "SOURCE" "Source")) ciMapTerm("bulk" '("B" "S" "BULK" "well" "SUB")) ciMapTerm("collector" '("c" "C" "collector")) ciMapTerm("base" '("b" "B" "base" "BASE" "Base")) ciMapTerm("emitter" '("e" "E" "emitter"))

See also Nets

Self Symmetric Instances - By Connectivity

Groups the instances that are determined to be self-symmetric based on their connectivity.

Placement Path

Identifies current paths in the active schematic cellview and creates a Placement Path constraint in the schematic Constraint Manager.

Series Resistor Array

Groups arrays of sequentially-arranged resistors that form the longest serial chain between two nets. The series chain terminates at a branch that connects to multiple resistors. Branches that connect to devices other than resistors are ignored.

Using the Series Resistor Array finder, you can generate modgen constraints for resistor arrays for the current cellview or each sub-cell. When you click the required constraint generator, a form is displayed for specifying the required criteria for creating a modgen template for the selected series resister arrays. For detailed information about the components of the displayed form, see Creating Modgen Template for Resistor Arrays.

Parallel Net Resistor Array

Groups arrays of parallel-arranged resistors that start and end on the same net.

Using the Parallel Net Resistor Array finder, you can generate modgen constraints for resistor arrays for the current cellview or each sub-cell. When you click the required constraint generator, a form is displayed for specifying the required criteria for creating a modgen template for the selected series resister arrays. For detailed information about the components of the displayed form, see Creating Modgen Template for Resistor Arrays.

Parallel Resistor Array (Length)

Groups arrays of parallel-arranged resistors that are all of the same length when their m-factor and iteration are expanded.

Using the Parallel Resistor Array (Length) finder, you can generate modgen constraints for resistor arrays for the current cellview or each sub-cell. When you click the required constraint generator, a form is displayed for specifying the required criteria for creating a modgen template for the selected series resister arrays. For detailed information about the components of the displayed form, see Creating Modgen Template for Resistor Arrays.

The constraint generator for the Parallel Net Resistor Array and Parallel Resistor Array (Length) finders is the same. Therefore, the form displayed for both is also the same.

Block Resistor Array

Groups all resistors in the design to form a large block. The block can include any number of resistor chains.

Using the Block Resistor Array finder, you can generate modgen constraints for resistor arrays for the current cellview or each sub-cell. When you click the required constraint generator, a form is displayed for specifying the required criteria for creating a modgen template for the selected series resister arrays. For detailed information about the components of the displayed form, see Creating Modgen Template for Resistor Arrays.

ALL

Finds all of the listed structures sequentially in the order of their listing in the Search for list.

Devices

Examples of devices include:

Most Finders in this category group devices by cell type, the exception being Active Same Well, where the benefits of debugging an incorrect body connection outweighs the false positives avoided by adding a same cell name restriction.

All Finders related to devices are discussed below:

Devices Finder

Description

Active Common Gate

Group active devices with same cell name.

The result here will comprise of one or more devices registered as "fet" or "bjt", whatever the cell names, and for the following connectivity:

G1 (=G2, etc)  (common gate for "fet" devices)
B1 (=B2, etc)  (common base for "bjt" devices)

Active Same Cell

Identifies all instances with the same cell name.

You will be displayed all device groups that contain the same cell name, for example all pmos3 may be outlined in red and all pmos4 outlined in blue, and so on.

You can then cycle through the groups and apply constraints, after which devices will be haloed (see Creating User-Defined Constraints in the Virtuoso Unified Custom Constraints Configuration Guide).

Associated Constraint:

Group 1: Orientation Orientations= R0, R180, MX, MY

Active Same Cell and Common Gate

Groups active devices with same cell name connected with a common gate.

Active Same Cell and Common Bulk

Group active devices with same cell name and common bulk.

Active Same Cell, Common Gate, and Bulk

Group active devices with same cell name with common gate and bulk.

The result here will comprise of one or more devices registered as "fet" or "bjt". The cell names must be the same and the connectivity must be as follows:

G1 (=G2, etc)  (common gate for "fet" devices)
B1 (=B2, etc)  (common base for "bjt" devices)
BU1 (=BU2, etc) (common bulk)

Active Same Cell and Finger Width

Group active devices with same cell name and finger width to set a Matched Parameters constraint.

Active Same Cell and Size

Identifies all instances that match the editable parameters, for example instance parameters in the CDF.

All device groups that match in editable parameters will be displayed, for example all pmos3 outlined in red, all pmos4 outlined in blue, and so on. You can then cycle through the groups and apply constraints, after which, weak outlining will be applied for found devices, and haloing for constrained devices (see Creating User-Defined Constraints in the Virtuoso Unified Custom Constraints Configuration Guide).

Active devices will be grouped by cell name and size. For example, if device M1 is an nmos and has: w=2u, l=130nm, m=1, it will not be grouped with M2 which is a pmos of the same size.

The matching expression for Active Same Cell and Size is:

if(ciIsDevice(device "fet") then list(ciGetParamName(device "length") ciGetParamName(device "width")) else nil)
The Active Same Cell and Size finder is particular useful for electrical constraints.

Associated Constraint:

Group 1:

MatchedOrientation Orientations= R0, R180, MX, MY

Matched Parameters:

MatchedSubset=nil

Passive Same Cell Name

Identifies all instances with the same cell name.

You will be displayed all device groups that contain the same cell name, for example all pmos3 may be outlined in red and all pmos4 outlined in blue, and so on. You can then cycle through the groups and apply constraints, after which devices will be haloed (see Creating User-Defined Constraints in the Virtuoso Unified Custom Constraints Configuration Guide).

Associated Constraint:

Group 1: Orientation Orientations= R0, R180, MX, MY

Passive Same Cell Name and Size

Identifies all instances that match editable parameters, for example instance parameters in the CDF.

All device groups that match in the editable parameters will be displayed, for example all pmos3 outlined in red, all pmos4 outlined in blue, and so on. You can then cycle through the groups and apply constraints, after which, weak outlining will be applied for found devices, and haloing for constrained devices (see Creating User-Defined Constraints in the Virtuoso Unified Custom Constraints Configuration Guide).

The matched expression matches length, width, resValue, indValue, and capValue. For example:

if(ciIsDevice(device “passive”) then list(ciGetParamName(device “length”) ciGetParamName(device “width”) ciGetParamName(device “resValue”) ciGetParamName(device indValue”) ciGetParam(device “capValue”)) else nil)

Associated Constraint:

Group 1: MatchedOrientation Orientations= R0, R180, MX, MY

Matched Parameters:

MatchedSubset=nil.

ALL

Executes all finders of the current category sequentially in the order of their listing in the Search for list and displays the corresponding results in the browser.

Nets

Examples of nets are power, ground, and symmetry. All Finders related to nets are detailed below:

Net Finder

Description

Supply Nets

Represents all power/ground nets in the current cellview.

Supply nets are recognized by name, and the names can be set by calling ciRegisterNet with a list of supply net names, for example ciRegisterNet("supply" list("agnd" "agnd!" "avdd" "avdd!")).

The supply net finder uses the ciIsNet(net) function to check the net name against the list of supply net names (all names are converted to lower case).

Non-Supply Nets

Represents all nets in the current cellview that are not supply nets. For example, the finder expression is:

!ciIsNet(net "supply")

Symmetric Net Pairs

Groups pairs of nets that are determined to be symmetric based on their connectivity.

For full description of operation see Symmetric Instance Pairs - By Connectivity.

Bus Bundle

Creates a bus for all signals of a bus net.

Registered (sigType)

Creates a sigType property for each registered net.

Same sigType (None)

Group all nets with the same sigType property value.

ALL

Finds all supply and non-supply nets, and all symmetric net pairs sequentially in the order of their listing in the Search for list.

Pins

Pins are members of symmetry, alignment, and distance. All Finders related to pins are detailed below:

Pins Finders

Description

Pins (Symmetry By Connectivity)

Group pairs of pins that are determined to be symmetric based on connectivity.

Top Pins (Alignment)

Group all top pins together.

Bottom Pins (Alignment)

Group all bottom pins together.

Left Pins (Alignment)

Group all left pins together.

Right Pins (Alignment)

Group all right pins together.

Supply Pins (Alignment)

Group all left pins together.

Input Pins (Alignment)

Group all input pins together.

Output Pins (Alignment)

Group all output pins together.

ALL

Finds all pins sequentially in the order of their listing in the Search for list.

Inst Terms

All Finders related to Inst Terms are detailed below:

Inst Term Finders

Description

InstTerms by Instance

Groups all instTerms for the same instance together.

InstTerms by Name

Group all instTerms by their name.

InstTerms by Net

Group all instTerms connected to the same net.

ALL

Finds all inst terms sequentially in the order of their listing in the Search for list.

Other Pre-defined Categories (Disabled by Default)

This section covers details about the following pre-defined categories that are disabled by default, but can be enabled using the ciEnableAssistant SKILL function:

Properties

All Finders related to Properties are detailed below:

Properties Finders

Description

Registered Nets (sigType)

Creates a sigType for each registered net.

Same sigType Nets (none)

Group all nets with same sigType property value.

fets (variantInfo)

Create a variantInfo property on FET devices with w >5u with pairs of fingerCount and fingerWidth.

Same variantInfo Devices

Group all devices with the same variantInfo property value.

pfets (placerControlledWell)

Create a placerControlledWell property for each PMOS device.

Same placerControlledWell Devices

Group all devices with the same placerControlled property value.

The placerControlledWell property is only created if a layer with the function "nwell" is defined in the layerRules section of the technology file. The corresponding layer name is used to set the value of the property.

ALL

Finds all properties sequentially in the order of their listing in the Search for list.

Electrical Constraints

All Finders related to Electrical Constraints are detailed below:

Electrical Constraints Finders

Description

Symmetric Pairs (Correlation)

Group instances by symmetrical pairs according to connectivity to set a correlation constraint.

Same Cell, Size, Bulk Devices (Matched Parameters)

Group devices with same cell name, bulk, connection and size (w, l, r, c)

ALL

Finds all electrical constraints sequentially in the order of their listing in the Search for list.

Placement Constraints

All Finders related to Placement Constraints are detailed below:

Placement Finders

Description

Common Bulk (Cluster)

Group devices with same cell names and a common bulk.

Digital Cells (Cluster)

Group all standard cells together.

To be captured, all standard cells must be registered with the function:

ciRegisterDevice( “standardCell” list( list(“libName” “cellName” “viewName”) list(LCV2) ...)

Same Cell, Size, Bulk Devices (Modgen)

Group devices with same cell name, bulk connection and size (w, l, r, c).

Clusters (Cluster Boundary)

Create a Cluster Boundary for any cluster.

Clusters (Guard Ring)

Create a Guard Ring for any cluster.

Modgens (Guard Ring)

Create a Guard Ring for any modgen.

Same Device Type (Orientation)

Group all primitive instances according to device type.

Modgens (Orientation)

Group all devices for the same modgen to set an orientation constraint.

Inverters (Alignment)

Group devices that form an inverter structure.

Inverters (Distance)

Group devices that form an inverter structure.

ALL

Finds all placement constraints sequentially in the order of their listing in the Search for list.

Routing Constraints

All Finders related to Routing Constraints are detailed below:

Routing Finders

Description

Supply Nets (Net Priority)

Creates a group for each supply net.

Bus and Bundle (Bus)

Creates a bus for all signals of a bus net.

Bus Bits

Creates a bus for each collection of bus bits.

ALL

Finds all routing constraints sequentially in the order of their listing in the Search for list.

Clusters

All Finders related to Clusters are detailed below:

Clusters Finders

Description

Common Bulk (Cluster)

Group devices with same cell name and a common bulk.

Same Cell and Size (Cluster)

Group primitive devices with same cell name and size.

Same Cell, Finger Width MOS (Cluster)

Group active devices with same cell name, bulk connection and finger width.

Digital Cells (Cluster)

Group all standard cells together.

To be captured, all standard cells must be registered with the function:

ciRegisterDevice( “standardCell” list( list(“libName” “cellName” “viewName”) list(LCV2) ...)

ALL

Finds all clusters sequentially in the order of their listing in the Search for list.

Matched Parameters

All Finders related to Matched Parameters are detailed below:

Matched Parameters Finders

Description

Symmetric Pairs (Matched Parameters)

Group instances by symmetrical pairs according to connectivity to match their parameters.

Same Cell, Size, Bulk Devices (Matched Parameters)

Group devices with same cell name, bulk connections and size (w, l, r, c)

Same Cell, Finger Width MOS (Matched Parameters)

Group devices with same cell name and finger width (fw)

Current Mirror (Matched Parameters)

Group devices of a Current Mirror to set a Matched Parameters constraint.

ALL

Finds all matched parameters sequentially in the order of their listing in the Search for list.

Modgens

All Finders related to Modgens are detailed below:

Modgens Finders

Description

Same Cell, Size, Bulk Devices (Modgen)

Group devices with same cell name, bulk, connection and size (w, l, r, c).

Digital Cells (Modgen)

Group all standard cells together.

To be captured, all standard cells must be registered with the function:

ciRegisterDevice( "standardCell" list( list("libName" "cellName" "viewName") list(LCV2) ...)

ALL

Finds all modgens sequentially in the order of their listing in the Search for list.

Orientations

The Orientations category allows for setting orientations on instances either per device or as in schematic.

All finders in the Orientations category are detailed below:

Orientations Finders

Description

Orientation as in Schematic

Group all primitive instances according to schematic orientation.

Same Device Type (Orientation)

Group all primitive instances according to device type.

Modgens (Orientations)

Group all devices for the same modgen to set an orientation constraint.

ALL

Finds all orientations sequentially in the order of their listing in the Search for list.
The maxMatchedPerDevice environment variable is added to control the maximum number of matches that a device may appear in when the Circuit Prospector structure finders are run. For example, Diff Pair and Current Mirror. This environment variable takes the integer value that defaults to 1.

Symmetries

All Finders related to Symmetries are detailed below:

Symmetries Finders

Description

Instance (Symmetry By Pre-Selection)

Group pairs of instances that are geometrically symmetric about the centre of the current selected set.

Instances in geometrically symmetric regions of the schematic need to be selected prior to running this finder.

Instance (Symmetry By Connectivity)

Group pairs of instances that are determined to be symmetric based on their connectivity.

Nets (Symmetry By Connectivity)

Group pairs of nets that are determined to be symmetric based on their connectivity.

Pins (Symmetry By Connectivity)

Group pairs of pins that are determined to be symmetric based on their connectivity.

ALL

Finds all symmetries sequentially in the order of their listing in the Search for list.

Analog Device Structures

All Finders related to Analog Device Structures are detailed in the following table.

These finders are used to create either device groups or Modgens in the Virtuoso automated device placement and routing flow. For more information about this flow, see Virtuoso Automated Device Placement and Routing Flow Guide.

Analog Device Structures Finders

Description

APR Device Group from DI

Groups APR Group Design Intent structures that are set in schematic.

APR Differential Pair

Groups devices that form a differential pair structure.

APR Differential Pair - Cross Coupled

Groups devices that form a cross-coupled differential pair structure.

APR Current Mirror

Groups devices that form a current mirror structure.

APR Cascode Current Mirror

Groups devices that form a cascoded current mirror structure.

APR Cascode Series Current Mirror

Groups devices that form a cascoded series current mirror structure.

APR Cascode

Groups cascoded MOS transistor structures.

APR Active Same Size Common Gate

Groups same-sized devices that share the same gate connection.

APR Active Same Size Common Gate and Source

Groups same-sized devices with the same gate and source connections.

APR Active Same Size Common Source

Groups same-sized devices with the same source connection.

APR Active Same Cell M-Factored Device

Groups active devices with mfactor.

APR Active Same Cell Stacked Device

Groups transistors in series stacks.

APR Active Same Cell Iterated Device

Groups iterated devices.

APR Active Same Cell and Size

Groups active devices with same cell name and size.

APR Passive Same Cell and Size

Groups passive devices with same cell names or the same cell sizes and values.

APR User Defined Group

Groups device groups inside text boxes.

APR Instances (Symmetry By Connectivity)

Groups pairs of instances that are determined to be symmetric based on their connectivity.

APR Instances (Symmetry By Connectivity with common source or drain)

Groups pairs of instances that are determined to be symmetric based on their connectivity with a common source or drain.

APR Nets (Symmetry By Connectivity)

Groups nets that are determined to be symmetric based on their connectivity.

APR Pins (Symmetry By Connectivity)

Groups pins that are determined to be symmetric based on their connectivity.

Creating and Editing Categories

You can create a new category of finders, or edit existing categories, using the Edit Categories form accessible from the “...” option adjacent to the Category drop-down in the Circuit Prospector assistant.

Additionally, from here, any finder can be added or removed to/from any category, and the order of the finders can be changed for any category.

Figure 2-12 The Edit Categories Form

Figure 2-13

Figure 2-14 The Edit Categories Form Use Model

Adding a New Category

To add a new category to the Circuit Prospector assistant:

  1. Select the “...” option adjacent to the Category drop-down list box.
    This will display the Edit Categories form.
  2. Choose the Add New Category (“+” icon) option in the Edit Categories form.
    This will display the New Category form.
  3. Enter a new category Name.
  4. Optionally, add a Description for the new category.
  5. Click the OK button. The new category will be added to the Categories list in the Edit Categories form.
  6. Click the Save button, in the Edit Categories form, to update the category and finder information to allow access to them from the Circuit Prospector assistant.

Editing an Existing Category

To edit the name and/or description of a category:

  1. Select the “...” option adjacent to the Category drop-down list box.
    This will display the Edit Categories form.
  2. Select the category to be edited from the Categories listing.
  3. Choose the Edit Category (icon) option in the Edit Categories form.
    This will display the Edit Category form.
  4. Edit the Name and/or Description of the currently selected category.
  5. Click the OK button. The category name and/or description will be updated and displayed in the Edit Categories form.
  6. Click the Save button, in the Edit Categories form, to update the category and finder information to allow access from the Circuit Prospector assistant.

Adding and Removing Finders from a Category

To add or remove finders to/from a new or existing category:

  1. Select the “...” option adjacent to the Category drop-down list box for you category that you want to edit finder content for.
    This will display the Edit Categories form.
    Figure 2-15 myFlow Category - Currently Contains No Finders
  2. Select the category whose finders are to be edited from the Categories listing.
  3. Choose the Choose Finders for Category (icon) option in the Edit Categories form.
    This will display the Choose Finders form.
    Figure 2-16 The Choose Finders Form
  4. Select and/or deselect the finders that you want to include in the selected category.
  5. Click the OK button.
    The Finders for Category listing will be updated to reflect the changes made.
    Figure 2-17 New Finders Added for myFlow Category
  6. Click the Save button, in the Edit Categories form, to update the category and finder information to allow access from the Circuit Prospector assistant.
    Figure 2-18 myFlow Category with Finders

Detecting Current Paths and Creating Constraints

To use the Circuit Prospector assistant to detect current paths and create constraints in a schematic cellview:

  1. Display the Circuit Prospector assistant by selecting Window – Assistants – Circuit Prospector.
  2. Select the Structures circuit prospector category.
  3. Select the Placement Path finder to search for relevant design objects. The results (objects or groups of objects that meet the search criteria) are retrieved automatically and displayed in the results table.
  4. Select the objects to which the constraint needs to be applied. This is an optional step.
  5. Select the button to add the Placement Path constraint to the selected objects. The new constraints are added to the Constraint Manager table.

For more information on how to use the Circuit Prospector assistant, see The Circuit Prospector Constraint Creation Flow.

For more information on how to use the Constraint Manager, see Chapter 1, “The Constraint Manager Assistant.”

Finders

Finders are search algorithms that search for devices, pins, and nets that meet specific, customizable, search criteria. For example, common circuit structures, related devices (of the same size, area, or type), devices with certain characteristics or shared connectivity, or perhaps symmetrical devices with particular properties.

The Circuit Prospector provides a set of pre-defined finders that can be listed by clicking the Search for drop-down list box. New finders can be created, current finders edited, and no longer required finders deleted.

See also:

For information on pre-defined finders, the following sections on pre-defined categories each provide descriptions of the finders they contain.

Creating Finders

See also Creating New Finders in the Virtuoso Unified Custom Constraints Configuration Guide.

You can edit the settings of a current finder to create a new finder, based on existing and/or new settings.

  1. Click the ... (ellipsis) Edit Finder button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This will display Edit Finder Form.
    Figure 2-20 The Edit Finder form
  2. Enter the name of the new finder in the Name field.
  3. Enter a Description of the new finder.
    This text entered here will be displayed as a tooltip when you float your cursor over the finder when it is listed in the Search for drop-down list box.
  4. In the Search Using Iterator drop-down list box, choose the iterator from the drop-down list that you want the new finder to use when performing a search.
    Clicking the ... (ellipsis) button to the right of the Search Using Iterator Generator will invoke Edit Iterator Form where you can add, edit, or delete iterators. For more information see Iterators.
  5. In the Matching Expression section specify a SKILL expression for the chosen iterator to apply when it iterates over cellview objects.
    The Matching Expression field can call a number of pre-defined functions, for example ciIsDevice(device "fet"), to filter the type of objects found.
    If an expression returns a positive value the current set of iterated objects will be collected and returned once the iteration is complete. The current set of iterated objects may be a single object or a set of objects, dependent upon the iterator selected.
    To the right of the expression entry area is a property display area which lists all of the properties of the currently selected objects in the design canvas.
    Right-clicking over this table will display a context-menu which enables you to re-arrange the table display. For example, you can choose to View by Property or View by Object, Expand All or Collapse All of the properties displayed, or choose to move to the Next or Previous selected property.
    Figure 2-21 Matching Expression section of the Edit Finder form
  6. Select a Default Constraints Generator for the new finder to use.
    Once the finder has been run the selected constraint generator will be used when Generate Constraints on the Circuit Prospector toolbar is selected.
    Clicking the ... (ellipsis) button to the right of the Default Constraints Generator section will invoke Edit Generator or Action Form where you can add, edit, or delete constraint generators. For more information see Constraint Generators.
  7. Click the OK button to create the new finder. The new finder will be added to the list of finders available under the Search for drop-down list box.

Editing Finders

If you edit an existing pre-defined finder, then the modified finder will be stored in the local .cadence directory (.cadence/dfII/ci/finders/<finderName>.il) and will override the original pre-defined finder.
  1. Click the ... (ellipsis) Edit Finder button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This will display Edit Finder Form.
  2. Optionally, edit the Description of the finder.
  3. Optionally, click the ... (ellipsis) button to the right of the Search Using Iterator drop-down list box to invoke Edit Iterator Form.
    Here, you can add, edit, or delete the iterator associated with the finder. For more information see Iterators.
  4. Optionally, in the Matching Expression section, edit the SKILL expression which the iterator applies as it iterates over cellview objects.
    If an expression returns a positive value the current set of iterated objects will be collected and returned once the iteration is complete. The current set of iterated objects may be a single object or a set of objects, dependent upon the iterator selected.
    If you make any changes in the SKILL expression and click the Save button, the Confirm Overwrite Finder? dialog box is displayed asking for the confirmation to override the SKILL expression, as shown below.
  5. Optionally, change the Default Constraints Generator to be used.
    Clicking the ... (ellipsis) button to the right of the Default Constraints Generator section will invoke Edit Generator or Action Form where you can add, edit, or delete constraint generators. For more information see Constraint Generators.
  6. Click the OK button to apply the finder edits.

Deleting Finders

To delete a finder:

  1. Select the finder you want to delete from the Search for drop-down list box in the Circuit Prospector assistant.
  2. Click the adjacent Delete Finder (cross) button to delete the selected finder.
    A window message asking you to confirm deletion is displayed.
    Figure 2-22 Confirming the Deletion of a Finder
    You cannot delete a pre-defined finder.
  3. Select Yes to confirm finder deletion, or select No to cancel finder deletion.
    The finder will be removed from the Search for drop-down list box.

Iterators

Iterators are SKILL functions that analyze cellview devices, nets, and pins in a variety of ways, for example iterate all selected objects, all instances, or all symmetrical devices.

As already described, Finders are wrappers around iterators that provide a SKILL expression for an iterator to apply so that it can return a list of objects that will satisfy that expression. In this way, iterators can be used by a multitude of finders.

Iterators can also have their own internal filtering settings.

This section contains information on:

Pre-Defined Iterators

You can view a list of the pre-defined iterators by clicking the Search Using Iterators drop-down option in Edit Finder Form.

To view, add, or edit iterators click the ... (ellipsis) button to the right of the Search Using Iterators option. This will displays Edit Iterator Form.

Figure 2-23 Search Using Iterator drop-down list box of Edit Finder form

Pre-Defined Iterator

Description

Iterator SKILL Function Name

Same Cell Iterator

Iterate over all devices with the same cell name.

 
ciSameCellIterator

Pin Iterator

Iterate over all pins.

 
ciPinIterator

Net Iterator

Iterate over all nets.

 
ciNetIterator

Instance Iterator

Iterate over all instances. Variable “device” can be used in matched expression.

 
ciInstIterator

InstTerm Iterator

Iterate over all instance terminals. Variables “instTerm” and “inst” can be used in matched expression.

 
ciInstTermIterator

XY Symmetric Iterator

Iterate over all X/Y symmetric active devices with the same cell name.

 
ciXYSymmetricIterator

XY Net Symmetric Iterator

Iterate over all X/Y symmetric nets.

 
ciXYNetSymmetricIterator

MOS Cascode

Iterate over all cascoded MOS transistor structures

 
ciMOSCascodedIterator

MOS Current Mirror Iterator

Iterate over all MOS Current Mirrors.

 
ciMOSCurrentMirrorStructIterator

MOS Cascoded Current Mirror Iterator

Iterate over all MOS Cascoded Current Mirrors.

 
ciMOSCascodedCurrentMirrorStructIterator

MOS Cascoded Current Mirror Iterator2

Iterate over all MOS Cascoded Current Mirrors - with at least one of the leading pairs being diode connected.

 
ciMOSCascodedCurrentMirrorStructIterator2

MOS Transmission Gate Iterator

Iterate over all MOS Transition Gates.

 
ciMOSTransmissionGateStructIterator

MOS Differential Pair Iterator

Iterate over all MOS Differential Pairs.

 
ciMOSDifferentialPairStructIterator

MOS Common Gate Iterator

Iterate over all MOS Common Gates.

 
ciMOSCommonGateStructIterator

MOS Parallel Iterator

Iterate over MOS Parallels.

 
ciMOSParallelStructIterator

MOS Active Load Iterator

Iterate over all MOS Active Loads.

 
ciMOSActiveLoadStructIterator

MOS Inverter Iterator

Iterate over all MOS Inverters.

 
ciMOSInverterStructIterator

MOS Cross Coupled Quad Iterator

Iterate over all MOS Cross Coupled Quads.

 
ciMOSCrossCoupledQuadStructIterator

XY Instance Symmetric Iterator

Iterate over all X/Y symmetric devices with the same cell name.

 
ciXYInstSymmetricIterator

Signal Iterator

Iterates over all signals. Variable “signals” can be used in matchExpr.

 
ciSignalIterator

Bundle Signal Iterator

Iterate over all bundle nets and return the list of corresponding signals. Variable “bundleSignals” can be used in matchExpr.

 
ciBundleSignalIterator

XY Pin Symmetric Iterator

Iterate over all X/Y symmetric pins.

 
ciXYPinSymmetricIterator

The above information is also displayed in the Edit Iterator Form.

Iterator SKILL Functions

The iterator SKILL function is called to perform an iteration. The function takes CellView (object ID) and matchExpressions (string of characters) as arguments, where CellView is the current cellview and matchExpression is the Matching Expression (see Edit Finder Form) that was defined for the finder that will call the iterator.

The function returns a list of object lists that satisfy matchExpression, while iterating through the passed CellView.

Creating Iterators

To create a new iterator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Search Using Iterator drop-down list box in the Edit Finder form.
    This displays Edit Iterator Form.
  3. Replace the name of the iterator in the Name field to create a new iterator name.
    Editing the name of the current iterator will not remove it from the Iterators list.
  4. Edit the Description of the new iterator.
  5. Edit the Iterator SKILL function name for the new iterator.
    The Iterator SKILL function name is the name of the SKILL function that is to be called to perform the iteration. The function takes a cellview (as an object ID) and a matching expression (as a string of characters) as arguments, where the cellview is the current cellview and the matching expression is the matching expression that has been defined for the finder that will call this iterator (see Creating Finders). The function returns a list of object lists that satisfy the matching expression while iterating through the passed cellview.
  6. Specify whether or not the iterator Supports Flattened Hierarchy.
  7. Select the Add button to add the new iterator to the Iterators list.
  8. Repeat steps 3-7 as necessary to add further iterators.
  9. Click the OK button to accept the iterator additions you have made.
    The Edit Finder form will again be displayed and any new iterators will be included in the Search Using Iterator drop-down list box.
The iterator calls a number of pre-defined helper functions, for example ciIsDevice(device "fet"), to filter the type of objects found.

Editing Iterators

To edit a current iterator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Search Using Iterator drop-down list box in the Edit Finder form.
    This displays Edit Iterator Form.
  3. Select the iterator you want to edit from the Iterators list.
  4. Optionally, edit the Description of the selected iterator.
  5. Optionally, edit the Iterator SKILL function name of the selected iterator.
  6. Optionally, edit the Supports Flattened Hierarchy of the selected iterator.
  7. Repeat steps 3-6 as necessary to edit further iterators.
  8. Click the OK button to accept the edits you have made.
    The Edit Finder form will again be displayed with iterator edits applied.

Deleting Iterators

Care should be taken as you can delete pre-defined iterators.

To delete an iterator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Search Using Iterator drop-down list box in the Edit Finder form.
    This displays Edit Iterator Form.
  3. Select the iterator you want to delete from the Iterators list.
  4. Click the Delete button.
  5. Repeat steps 3-4 as necessary to delete further iterators.
  6. Click the Cancel button to apply the iterator deletions and return to the Edit Finder form.
    The iterators that you have deleted will no longer be listed in the Search Using Iterator drop-down list box.

Constraint Generators

Constraint generators are used to generate constraints for those groups of nets, instances, or pins that are selected in the results section of the Circuit Prospector assistant.

Nets are listed in the Circuit Prospector results table for all default constraint generators, as there may be default constraints associated with these nets that need to be considered.

A constraint generator will generate one or more constraints with either default or specific parameter values.

Constraint generators might need to access those object properties that are to be constrained (for example, the object’s orientation). As the associated finder may have been run hierarchically, the object may then be located in either the current cellview or a lower level cellview. Therefore, to get the database ID (dbID) of the object use:

ciFindObjectInHier(fullObjectName cache 'objType)

To ensure that the object is searched for at the correct hierarchical level use, for example:

ciFindObjectInHier("/I1/I2/MN1" cache 'inst)

A set of pre-defined constraint generators are provided along with the capability of creating new generators. For more information, see:

Pre-Defined Constraint Generators

The Circuit Prospector assistant provides pre-defined constraint generators for each base constraint type, plus a selection of variations with alternative parameter settings.

Pre-defined Constraint Generator Description Expression

Matched Parameters

Generate Matched Parameters

 
ciConCreateExpanded(cache ’matchedParameters ?members append(inst pins) ?verbose nil)

Matched Size

Generate Matched Parameters for l and w

 
ciConCreateExpanded(cache ’matchedParameters ?members append(insts pins ?params list( list("matchSubset" "l w") ) ) ?verbose nil)

Symmetry

Generate Symmetry with vSymm axis.

 
ciConCreateExpanded(cache ’symmetry ?members append(insts append(pins instTerms)) ?axis "vSymm" ?verbose nil)

vSymmetry

Generate Symmetry with vSymm axis.

 
ciConCreateExpanded(cache ’symmetry ?members append(insts append(pins instTerms)) ?axis "vSymm" ?verbose nil)

hSymmetry

Generate Symmetry with hSymm axis.

 
unless( ciAxisExists(cache "hSymm") ciAxisCreate(cache "hSymm" list(list("direction" "horizontal"))) ) ciConCreateExpanded(cache ’symmetry ?members append(insts append(pins instTerms)) ?axis "hSymm" ?verbose nil)

Alignment

Generate an alignment constraint

 
ciConCreateExpanded(cache ’alignment ?members append(insts append(pins instTerms)) ?verbose nil)

Orientation

Generate an orientation constraint

 
ciConCreateExpanded(cache ’orientation ?members append(insts pins ?verbose nil)

Module

Generate a modgen constraint

 
ciConCreateExpanded(cache ’modgen ?members insts ?verbose nil)

Same Cell Name - Group + Relative Orientation

Generate Cluster and Same Orientation Constraints

 
when( cadr(instsNetsPins) ciConCreateExpanded(cache ’cluster ?members insts ?note strcat("CP: Group together devices with same cell name") ?verbose nil) && ciConCreateExpanded(cache ’relativeOrientation ?members insts ?note strcat("CP: Matching orientation for devices with same cell name") ?verbose nil)

Common Gate - Group + Relative Orientation

Generate Cluster and Same Orientation Constraints

 
when( cadr(instsNetsPins) ciConCreateExpanded(cache ’cluster ?members insts ?note strcat("CP: Group together devices with common gate") ?verbose nil) && ciConCreateExpanded(cache ’relativeOrientation ?members insts ?note strcat("CP: Matching orientation for devices with common gate") ?verbose nil)

Same Well - Group + Relative Orientation

Generate Cluster and Same Orientation Constraints

 
when( cadr(instsNetsPins) ciConCreateExpanded(cache ’cluster ?members insts ?note strcat("CP: Group together devices with same well") ?verbose nil) && ciConCreateExpanded(cache ’relativeOrientation ?members insts ?note strcat("CP: Matching orientation for devices with common gate") ?verbose nil)

Module + Matched Parameters

Generate Modgen and Matched Parameters

 
ciConCreateExpanded(cache ’modgen ?members insts ?note strcat("CP: Module for devices of MOS cross coupled quad") ?verbose nil) && ciConCreateExpanded(cache ’matchedParameters ?members insts ?note strcat("CP: Matched parameters for devices of MOS cross coupled quad") ?verbose nil)

Group + Relative Orientation + Vertical Alignment

Generate Cluster, Same Orientation and Alignment with vAlign Axis

 
unless( ciAxisExists(cache "vAlign") ciAxisCreate(cache "vAlign" list(list("direction" "vertical"))) ) ciConCreateExpanded(cache 'cluster ?members insts   ?note strcat("CP: Group together NMOS and PMOS of transmission gate or inverter") ?verbose nil) && ciConCreateExpanded(cache 'relativeOrientation ?members insts ?note strcat("CP: Matched orientation of NMOS and PMOS of transmission gate or inverter") ?verbose nil) && ciConCreateExpanded(cache 'alignment ?members insts ?axis "vAlign" ?params list( list("side" "center")) ?note strcat("CP: Align vertically NMOS and PMOS of transmission gate or inverter") ?verbose nil)

Group + Relative Orientation + Horizontal Alignment

Generate Cluster, Same Orientation and Alignment Constraints

 
when( cadr(instsNetsPins) ciConCreateExpanded(cache 'cluster ?members insts   ?note strcat("CP: Group together parallel devices or devices of MOS current mirror") ?verbose nil)) && ciConCreateExpanded(cache 'relativeOrientation ?members insts ?note strcat("CP: Matched orientation for parallel devices or devices of MOS current mirror") ?verbose nil) && ciConCreateExpanded(cache 'alignment ?members insts ?note strcat("CP: Horizontal alignment for parallel devices or devices of MOS current mirror") ?verbose nil)

Group + Relative Orientation + Matched Parameters

Generate Cluster, Same Orientation and Matched Parameters

 
when( cadr(instsNetsPins) ciConCreateExpanded(cache 'cluster ?members insts  ?note strcat("CP: Group together devices with same cell name and size") ?verbose nil)) && ciConCreateExpanded(cache 'relativeOrientation ?members insts ?note strcat("CP: Matching orientation for devices with same cell name and size") ?verbose nil) && ciConCreateExpanded(cache 'matchedParameters ?members insts ?params list(list("matchSubset" nil)) ?note strcat("CP: Matched parameters for devices with same cell name and size") ?verbose nil)

Symmetry + Matched

Generate Symmetry with vSymm Axis and Matched Parameters

 
ciConCreateExpanded(cache 'symmetry ?members list(car(insts) cadr(insts)) ?axis "vSymm" ?note strcat("CP: Mirror symmetry for symmetrical devices") ?verbose nil) && ciConCreateExpanded(cache 'matchedParameters ?members append(insts pins)  ?note strcat("CP: Matched parameters for symmetrical devices") ?verbose nil)

Matched + Distance

Generate Matched Parameters and Short Distance

 
ciConCreateExpanded(cache 'matchedParameters ?members append(insts pins)  ?note strcat("CP: Matched parameters for devices of MOS differential pair") ?verbose nil) && ciConCreateExpanded(cache 'distance ?members append(insts pins)  ?params list(list("max" 10.0)) ?note strcat("CP: Close proximity for devices of MOS differential pair") ?verbose nil)

Matched + Symmetry + Distance

Generate Matched Parameters, Symmetry with vSymm Axis and Distance

 
ciConCreateExpanded(cache 'matchedParameters ?members append(insts pins)  ?verbose nil) && ciConCreateExpanded(cache 'symmetry ?members append(insts pins)  ?axis "vSymm" ?verbose nil) && ciConCreateExpanded(cache 'distance ?members append(insts pins)  ?verbose nil)

Group

Generate Cluster Constraint

 
ciConCreateExpanded(cache 'cluster ?members insts  ?verbose nil)

Supply Route Priority

Generate High Priority Constraint

 
ciCreateRoutePriorityCon(cache nets 128)

Non Supply Route Priority

Generate Average Priority Constraint

 
ciCreateRoutePriorityCon(cache nets 64)

Matching (strength)

Ask for Matching Variants

 
ciRunMatchingConstraintsGenerator(args insts cache)

Common Centroid

Generate Common Centroid Constraints

 
(_ciCommonCentroidGen args insts cache)

Inst Symmetry

Generate Symmetry, Matched Parameters and Correlation Constraints

 
ciGeneratorForInstSymmetry(cache insts )

Net Symmetry

Generate Symmetry with vertSymm Axis and High Priority

 
ciGeneratorForNetSymmetry(cache nets )

Same Orientation

Generate Orientation Constraint per Schematic Orientation

 
let( (inst) inst = substring(caar(insts) 2) while(nindex(inst "/") inst = substring(index(inst "/") 2)) ciConCreateExpanded(cache 'orientation ?params list( list("restrictTo" list(dbFindAnyInstByName(geGetEditCellView() inst)->orient)) ) ?members insts ?note strcat("CP: Same orientation as in schematic") ?verbose nil))

Orientation per Device Type

Generate Orientation Constraint per Device Type

 
let( (inst orientL) inst = substring(caar(insts) 2) while(nindex(inst "/") inst = substring(index(inst "/") 2)) inst=dbFindAnyInstByName(geGetEditCellView() inst) orientL=list("R0" "MY") when(ciIsDevice(inst "standardCell") orientL=list("R0")) when(ciIsDevice(inst "nfet") orientL=list("R0" "MY")) when(ciIsDevice(inst "passive") orientL=nil) ciConCreateExpanded(cache 'orientation ?params list( list("restrictTo" orientL)) ?members insts ?note strcat("CP: Orientation per Device Type") ?verbose nil))

Bus for Nets

Generate Bus Constraint

 
ciConCreateExpanded(cache 'bus ?members list(list(substring(caar(nets) 2) 'net)) ?verbose nil)

Bus for Signal Bits

Generate Bus Constraint

 
ciConCreateExpanded(cache 'bus ?members nets ?verbose nil)

sigType for registered nets

Set sigType Property per Net Registration

 
let((net) net=dbFindNetByName(geGetEditCellView() substring(caar(nets) 2)) when(ciIsNet(net "power") net->sigType="supply") when(ciIsNet(net "ground") net->sigType="ground") when(ciIsNet(net "clock") net->sigType="clock") when(ciIsNet(net "reset") net->sigType="reset") when(ciIsNet(net "analog") net->sigType="analog"

None

No action

 
t

Alignment for Right Pins

Generate Pin Alignment on the Right

 
ciAlignPinsOnCellSide(cache instsNetsPins ?side "right")

Alignment for Bottom Pins

Generate Pin Alignment on the Bottom

 
ciAlignPinsOnCellSide(cache instsNetsPins ?side "bottom")

Alignment for Left Pins

Generate Pin Alignment on the Left

 
ciAlignPinsOnCellSide(cache instsNetsPins ?side "left")

Alignment for Top Pins

Generate Pin Alignment on the Top

 
ciAlignPinsOnCellSide(cache instsNetsPins ?side "top")

variantInfo for FETs

Set variantInfo Property for FETs

 
ciVariantInfoForFingersAndFingerWidth( instsNetsPins ?minFingerWidth "0.5u" ?maxFingerWidth "30u")

placerControlledWell

Set placerControlledWell Property for pfets

 
ciPlacerControlledWellGeneration( instsNetsPins )

Correlation

Generate Correlation Constraint

 
ciConCreateExpanded(cache `correlation ?members instsNetsPins ?params list( list("coefficient" 0.9) ) ?note "CP: High Correlation for symmetric pair" )

Matched Parameters for Same Cell Size and Bulk

Generate Matched Parameters for Size and Value

 
ciMatchedParamsForSameSizeInstances(cache instsNetsPins)

Cluster for Devices with common bulk

Generate Cluster Constraint

 
let((cx) cx=ciConCreateExpanded(cache 'cluster ?members insts ?verbose nil ?note "CP: Cluster for devices with common bulk") )

Cluster for Standard Cells

Generate Cluster Constraint

 
let((cx) cx=ciConCreateExpanded(cache 'cluster ?members insts ?verbose nil ?note "CP: Cluster for standard cells") )

Modgen for Same Cell Size and Bulk

Generate Modgen Constraint

 
ciModgenForSameCellSizeAndBulk(cache instsNetsPins)

Cluster Boundary for Cluster

Generate Cluster Boundary Constraint

 
ciClusterBoundaryForCluster( cache instsNetsPins )

Guard Ring for cluster

Generate Guard Ring Constraint

 
ciGuardRingForCluster( cache instsNetsPins )

Guard Ring for modgen

Generate Guard Ring Constraint

 
ciGuardRingForModgen( cache instsNetsPins )

Orientation for modgen

Generate Orientation Constraint

 
ciOrientationForModgen( cache instsNetsPins )

Alignment for Inverters

Generate Alignment with vertAlign Axis

 
instsNetsPins = setof( x instsNetsPins (cadr(x) == 'inst) ) ciConCreateExpanded(cache `alignment     ?members instsNetsPins     ?axis "vertAlign"     ?params list( list("side" "center") )     ?note strcat("CP: Align NMOS and PMOS for an inverter") )

Distance for Inverters

Generate Short Distance Constraint

 
instsNetsPins = setof( x instsNetsPins (cadr(x) == 'inst) ) ciConCreateExpanded(cache `distance     ?members instsNetsPins     ?params list( list("min" 2.0)  list("max" 10.0))     ?note strcat("CP: Distance for the NMOS and PMOS of an inverter") )

Symmetry for Pins

Generate Symmetry with vertSymm Axis

 
let(() unless( ciAxisExists(cache "vertSymm") ciAxisCreate(cache "vertSymm" ))  ciConCreateExpanded(cache 'symmetry ?members setof(x instsNetsPins (cadr(x) == 'pin) ) ?axis "vertSymm" ?verbose nil ?note strcat("CP: Symmetry for symmetrical pins")))

Symmetry for Nets

Generate Symmetry with vertSymm Axis

 
let(() unless( ciAxisExists(cache "vertSymm") ciAxisCreate(cache "vertSymm" )) ciConCreateExpanded(cache `symmetry ?members instsNetsPins ?axis "vertSymm" ?verbose nil ?note "CP: Symmetry for pair of symmetric nets"))

Symmetry for Instance

Generate Symmetry with vertSymm Axis

 
let(() unless( ciAxisExists(cache "vertSymm") ciAxisCreate(cache "vertSymm" ))  ciConCreateExpanded(cache 'symmetry ?members instsNetsPins ?params list( list("mirror" 0) ) ?axis "vertSymm" ?verbose nil ?note strcat("CP: Mirror Symmetry for symmetric instances")))

MatchedParameters for Symmetric Instances

Generate Matched Parameters for Size and Value

 
ciMatchedParamsForInstanceSymmetry( cache instsNetsPins )

Matched Parameters for Current Mirror

Generate Matched Parameters for Size and Ratio

 
ciMatchedParametersForCurrent_Mirror( cache instsNetsPins )

Cluster for Devices with same name and size

Generate Cluster Constraint

 
let((cx) cx=ciConCreateExpanded(cache 'cluster ?members insts ?verbose nil ?note "CP: Cluster for devices with same name and size") )

Cluster for Devices with same finger width

Generate Cluster Constraint

 
let((cx) cx=ciConCreateExpanded(cache 'cluster ?members insts ?verbose nil ?note "CP: Cluster for devices with same finger width") )

Modgen for Standard Cells

Generate Modgen Constraint

 
ciConCreateExpanded(cache 'modgen ?members foreach(mapcar inst insts list(car(inst) cadr(inst) list(list("horiAlignment" "custom")))) ?verbose nil ?note "CP: modgen for standard cells")

Distance + Matched Orientation + Vertical Alignment

Generate Short Distance, Same Orientation and Alignment with vAlign Axis

 
unless( ciAxisExists(cache "vAlign") ciAxisCreate(cache "vAlign" list(list("direction" "vertical"))) ) ciConCreateExpanded(cache 'distance ?members insts ?params list( list("min" 2.0)  list("max" 10.0)) ?note strcat("CP: Short distance between NMOS and PMOS of a transmission gate or inverter") ?verbose nil) && ciConCreateExpanded(cache 'relativeOrientation ?members insts ?note strcat("CP: Matched orientation of NMOS and PMOS of transmission gate or inverter") ?verbose nil) && ciConCreateExpanded(cache 'alignment ?members insts ?axis "vAlign" ?params list( list("side" "center")) ?note strcat("CP: Align vertically NMOS and PMOS of transmission gate or inverter") ?verbose nil)

Common Bulk - Group + Matching Orientation

Generate Cluster and Same Orientation Constraints

 
ciConCreateExpanded(cache 'cluster ?members insts ?note strcat("CP: Group together devices with common bulk") ?verbose nil) && when( cadr(instsNetsPins) ciConCreateExpanded(cache 'relativeOrientation ?members insts ?note strcat("CP: Matching orientation for devices with common bulk") ?verbose nil))

Matched Parameters for Same Finger Width

Generate Matched Parameters for Finger Width

 
ciMatchedFingerWidth(cache instsNetsPins)

MOS Active Load - Matched + Symmetry + Distance

Create MOS Active Load constraints

 
ciConCreate(cache `matchedParameters ?members list(car(instsNetsPins) cadr(instsNetsPins)) ?verbose nil) && ciConCreate(cache `symmetry ?members list(car(instsNetsPins) cadr(instsNetsPins)) ?verbose nil) && ciConCreate(cache `distance ?members list(car(instsNetsPins) cadr(instsNetsPins)) ?verbose nil)

The above information can also be found in the Edit Generator or Action Form when editing a generator.

Creating Constraint Generators

See also Creating Custom Constraint Generators in the Virtuoso Unified Custom Constraints Configuration Guide.

To create a new constraint generator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays the Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Default Generator or Action drop-down list box in the Edit Finder form.
    This displays the Edit Generator or Action Form.
  3. Replace the name of the constraint generator in the Name field to create a new constraint generator.
    Editing the name of the current constraint generator will not remove it from the Generators or Actions list.
  4. Edit the Description of the new constraint generator.
  5. Edit the associated Expression for the new constraint generator.
  6. Select the Add button to add the new constraint generator to the Generators or Actions list.
  7. Repeat steps 3-6 as necessary to add more constraint generators.
  8. Click the Save button to accept the constraint generator additions you made.
    The Edit Finder form is displayed again and the new constraint generators are included in the Default Generator or Action drop-down list box.

Editing Constraint Generators

To edit a constraint generator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays the Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Default Generator or Action drop-down list box in the Edit Finder form.
    This displays the Edit Generator or Action Form.
  3. Select the constraint generator you want to edit from the Generators or Actions list box.
  4. Optionally, edit the Description of the constraint generator.
  5. Optionally, edit the associated Expression for the constraint generator.
  6. Repeat steps 3-5 as necessary to edit more constraint generators.
  7. Click the Save button to accept the constraint generator edits you made.
    The Edit Finder form is displayed again with the constraint generator edits applied.

Deleting Constraint Generators

To delete a constraint generator:

  1. Click the ... (ellipsis) button to the right of the Search for drop-down list box in the Circuit Prospector assistant.
    This displays the Edit Finder Form.
  2. Click the ... (ellipsis) button to the right of the Default Generator or Action drop-down list box in the Edit Finder form.
    This displays the Edit Generator or Action Form.
  3. Select the constraint generator you want to delete from the Generators or Actions list box.
  4. Click the Delete button.
  5. Repeat steps 3-4 as necessary to delete more constraint generators.
  6. Click the Cancel button to apply the constraint generator deletions and return to the Edit Finder form.
    The constraint generators that you have deleted will no longer be listed in the Default Generator or Action drop-down list box.

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