Product Documentation
Virtuoso Parasitic Aware Design User Guide
Product Version IC23.1, November 2023

C

Parasitic Aware Design and Diva Verification

This appendix describes parasitic aware design flows for analog and mixed-signal circuits. It comprises of the following sections:

Diva Flow: Simulating Analog Circuits with Parasitic Aware Design

This section describes how you can use Cadence® tools to investigate the effect of parasitics on analog circuits. By accounting for the effect of parasitics, you can improve the accuracy of your circuit simulations. If your design includes digital or mixed-signal circuits, skip this section and use Diva Flow: Simulating Mixed-Signal Circuits with Parasitic Aware Design.

This section comprises of the following topics:

For more information on Diva see the Diva Reference.

Overview

Simulating an analog circuit with parasitics requires these steps.

  1. Preparing cell libraries
  2. Creating an analog_extracted view of your design

In this step, the tool calculates parasitics from information in the layout view of your circuit.

The following flow diagram illustrates the substeps in creating an analog_extracted view using the Diva® physical verification tool. The substeps for the Cadence RC network reducer are shown with dotted lines because they are optional.

  1. Creating a configuration for your design.
  2. Simulating the design with parasitics included

After a successful simulation, you can select terminals and device pins on the schematic and use plot commands to display the results in a waveform window. The resulting waveforms can be used with all Virtuoso analog design environment (ADE) calculation and analysis tools.

Preparing Cell Libraries

Before you can follow the flow outlined in this chapter, you need to provide the following views and component description format (CDF) information for analog primitives and parasitic cells.

Analog primitives must have Parasitic cells (such as presistors and pcapacitors) must have

symbol cellview

symbol cellview

layout cellview or extraction rules that the extractor will recognize

auLvs cellview for analog primitives

Model matching the simulator you use

CDF simulation information for auLvs

auLvs cellview that provides parameter values used by LVS

CDF component parameters for resistance (r) and capacitance (c)

The analogLib library contains examples of analog primitives and parasitic cells that you can copy to create your cell library.

You can find the analogLib in the following hierarchy:

$CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib

Transferring Schematics from Diva to Assura

Any schematics, with placed estimated parasitic devices, that have been used with Diva will not be recognized if transferred to the Assura flow.

This is because the LVS (layout versus schematic) checks will ignore the following (shorted) devices: presistor, pinductor, tline2, tline3, tline4, tline4x, tline4p.

pcapacitor, pdiode, and tline1 are opened as expected.

Preparing Technology Files

To prepare a library for parasitic extraction,

  1. Describe the technology layers.
    For details about the technology layers, refer to the Incremental Technology Databases and Display Resources User Guide.
  2. Add or modify the verification rules used by the Diva processes DRC, Extract, and LVS.
    Refer to the Diva Reference for details about creating verification and extraction rules.

Adding Component Description Format Simulation Information

Refer to the Component Description Format User Guide for more details about the steps in this section.

To netlist primitives correctly, you must verify the auLvs CDF parameters for each primitive.

  1. Start the Cadence software by typing virtuoso& at the command prompt.

For more information about the options you can use with the command to start the software, refer to the Virtuoso Design Environment User Guide.

  1. In the command interpreter window (CIW), choose Tools – CDF – Edit.
    The Edit Component CDF form appears.
  2. In the upper portion of the form, choose Cell for CDF Selection and Base for CDF Type.
    You must edit the base-level CDF for changes to be effective.
  3. Fill in the Library Name and Cell Name fields, or click the Browse button to select the cell.
    The Edit Component CDF form expands to display additional information.
  4. In the Simulator Information area of the expanded Edit Component CDF form, click Edit.
    The Edit Simulation Information form appears, displaying existing CDF information about auLvs netlisting.
  5. Select auLvs in the Choose Simulator drop-down list box.
  6. Ensure that the netlistProcedure field specifies ansLvsCompPrim. This is the internal auLvs procedure for netlisting primitives.
  7. In the instParameters field, specify the parameters you want in the netlist.
    A component can have several parameters, such as temperature coefficients, that do not apply to LVS netlist comparison. You LVS comparison rules tell LVS how to handle such parameters.
    If model is included in the instParameters field, auLvs uses the value of the model property in the instance instead of the value of componentName in the netlist.
  8. In the componentName field, type the component name you want included in the netlist.
    This optional field allows you to use a common name in the netlist for different cells. For example, 3-terminal cellviews (with programmable bulk nodes) and 4-terminal cellviews (with a bulk node as a pin) that have distinct names like nmos3 and nmos4 can be netlisted with the same component name like nmos.
    The component names pcapacitor, presistor, pinductor, and pdiode are used for parasitic devices. All these devices are removed from the netlist before layout versus schematic (LVS) runs, but are used in simulation and backannotation. For presistors and pinductors, the nets are shorted together.
  9. In the termOrder field, type the names of the device terminals as they appear in the symbol cellview.
    This is the order in which the terminals are netlisted.
  10. If termOrder uses programmable nodes, type the names of the terminals in deviceTerminals.
    The input is the same as for termOrder, but programmable nodes are replaced by names in this field.
  11. For existing designs that use older databases, use prop Mapping to change the name of an instance parameter.
    This allows instParameter names that use lowercase letters to be mapped to LVS rules that are defined in uppercase letters.
    Do not use this feature for new designs.
  12. In the Permute Rule field, specify the LVS permute rule used to define equivalent pins.
  13. Click OK on the Edit Simulation Information form and Apply on the Edit Component CDF form to accept your changes.
The CDF parseAsNumber property distinguishes strings from numbers in numeric parameters. String parameters without the parseAsNumber property set to true are netlisted as strings beginning and ending with “\”. This feature is not compatible with releases before 4.4.2.

Creating Designs

If you intend to extract parasitic components from the layout view and run a simulation with parasitics, use the following guidelines to avoid problems as you plan your design.

Creating Extracted Views

You use the Diva physical verification tool to extract parasitics from the layout view of a block. Then you use LVS to compare the extracted view to the schematic view to identify areas that are not consistent between the views. After a successful LVS run, you create an analog_extracted view of the design.

Extracting Parasitics

To extract parasitics from the layout view of a cell or block,

Ensure that the environment variable CDS_Netlisting_Mode is set to Analog:
  1. Choose Verify – Extract from the layout cellview of the cell.
    The Extractor form appears.
  2. Choose flat for Extract Method.
    You need to use flat extraction because parasitic capacitance values can vary between different instances of the same cell. Each cell, therefore, must be extracted.
  3. (Optional) Choose Join Nets With Same Name.
    This ensures that nets with the same name are joined automatically.
  4. To select the types of parasitics you want extracted, click Set Switches.
    The Set Switches form appears. The parasitics displayed vary, depending on the extraction rules file defined for your design. In some cases, you do not need to make any selections.
    To select more than one item, click your first selection, then hold down the Control key and make the rest of your selections.
  5. When you have specified the parasitics you want, click OK.
    The Extractor form reappears with the parasitics you selected in the Switch Names field.
  6. Click OK or Apply to create the extracted views.
    A message in the command interpreter window (CIW) tells you when the extraction process is complete.

Comparing Schematic and Extracted Views

To compare the schematic view with the extracted view created earlier, follow these steps.

  1. From a window displaying the extracted view, choose Verify – LVS.
    The LVS form appears.
    For more information on the LVS form see Verify Menu Commands in the Diva Reference.
  2. Depending on which views are open, use one of the following procedures to identify the schematic and extracted views that you want to compare.
    If both the schematic and extracted views are open If only the extracted view is open
    1. Click the Sel by Cursor button below the schematic detail, then click the cursor in the open schematic view.
    2. Do the same for the extracted view.
    1. Click the Sel by Cursor button below the extracted detail, then click the cursor in the open extracted view.
    2. Click the Browse button below the schematic detail and select the schematic view.
  3. Enter the names of the rules file and rules library for the Diva LVS rules.
  4. Click the Run button to begin the comparison.
  5. When the comparison finishes, click Info.

The Display Run Information form appears.

  1. Click Log File.
    Scroll through the log file to the netlist comparison section near the end of the file. This section identifies any mismatches between the two files. Each error is described in the sections following the comparison results.
    Not all mismatches are fatal. Look over the comparison results to determine if you need to correct one of the files and redo the extraction and comparison or if you can proceed with the views as they are.
  2. Choose File – Close Window in the log file window.
  3. Click Cancel in the Display Run Information form.
  4. Correct any problems in the schematic or extracted views.
  5. If necessary, rerun the comparison.

Building an analog_extracted View

When the comparison between schematic and extracted views is acceptable, you need to select the parasitics to use for simulation. You also need to build the analog_extracted view.

  1. In the LVS form, click Build Analog.
    The Build Analog Extracted View form appears.
    For more information on the LVS form see Verify Menu Commands in the Diva Reference.
  2. Select one of the following choices to specify the analog parasitics that you want to use for simulation.
    Select If you want to

    Include All

    Simulate with all the parasitics that have been extracted.

    Set From Schematic

    Select parasitics to include in the simulation by placing special symbols (spresistor, spcapacitor, spinductor, and spcapacitor2) on nets in the schematic view. The spcapacitor2 device is used to include parasitics in the simulation that appear between two specified nets. If you add or remove symbols from the schematic, click Check and Save to save the modified view.

    The parasitics you select by placing these symbols (which are provided in sbaLib) are the only ones included in the simulation.

    The sbaLib can be found at the following location in the Cadence installation:

    <installation_dir>/tools/dfII/etc/cdslib/artist/sbaLib

    To define this library in your cds.lib you need to set the following:

    DEFINE sbaLib <installation_dir>/tools/dfII/etc/cdslib/artist/sbaLib

    If you choose Set From Schematic and click OK without identifying any nets on the schematic, the Extracted Parasitics Selective Annotation form asks you to confirm your choice.

    None

    Simulate with none of the parasitics.
  3. Click OK to accept your settings and build the analog_extracted view.

Creating and Using a Configuration

This section explains how to set up a configuration so that the simulator runs with the analog_extracted view created in the previous step. The steps given here for using the Cadence Hierarchy Editor to create a configuration are abbreviated. For complete information, see the Cadence Hierarchy Editor User Guide.

To create a configuration for your design,

  1. From the CIW, choose File – New – Cellview.
    The Create New File form appears.
  2. Choose the library for the new file.
  3. Type the name of the cell for which you want to create the configuration.

The top-level cell for your design is usually the appropriate cell to use.

  1. If you do not want to use config as the view name, type the name you want into the View Name field.
  2. Choose Hierarchy-Editor from the Tool drop-down list box.
  3. Ensure that the Library path file field correctly specifies the cds.lib file that contains the paths to your libraries.
  4. Click OK.

The New Configuration form appears.

  1. Click the Use Template button located at the bottom of the form.

The Use Template form appears.

  1. Select a template that is compatible with the simulator you are running from the Name drop-down list box.
  2. Click OK in the Use Template form.
    The New Configuration form redisplays with default data for the Top Cell and Global Bindings sections. This allows you to modify a typical view list and stop list, rather than creating them from scratch.
    Templates exist for each of the simulators. To create templates that provide defaults for these fields, see the Cadence Hierarchy Editor User Guide.
  3. In the Top Cell section, enter the library, cell name, and schematic cellview from which to build the configuration.
    Be sure to specify schematic for the view type because the configuration is built from the original schematic of your design.
  4. Click OK.
    The Hierarchy Editor window displays your data.
    The Hierarchy Editor window configures the design by using a default View List and Stop List in the Global Bindings section. You need to modify these lists for your design.
  5. Use one of the following methods to specify the analog_extracted view for the cells or blocks for which you want parasitics simulated.
    To specify views for individual blocks To specify views for multiple blocks
    1. In the Instance Binding section of the Hierarchy Editor window, position the cursor in the View To Use column of the appropriate block.
      If the Instance Binding section is not visible in the window, choose View – Instance Table to display this section.
    2. Press the right mouse key to display a list of commands.
    3. Choose Select View to display the list of views for this block.
    4. Choose analog_extracted as the view for this block.
    • In the Global Bindings section of the Hierarchy Editor window, add analog_extracted as the first view in the View List text field.
      This ensures that the analog_extracted view is the selected view for every cell that has an analog_extracted view.
  6. Choose View – Update to reconfigure the design to reflect your changes.

The Update Sync-up form appears.

  1. Click OK.
  2. Choose File – Save to save the configuration with your changes.
  3. Choose File – Exit to close the Hierarchy Editor.

Simulating the Design

To run the simulation,

  1. In the CIW, choose Tools – Analog Environment – Simulation.

The Analog Design Environment Simulation window appears.

  1. Choose Setup – Design.

The Choosing Design form appears.

  1. Select the library and cell name of your design.
  2. Select config from the View Name drop-down list box.
  3. Click OK.
    This view supplies configuration as well as schematic information.
  4. In the Analog Design Environment Simulation window, choose your simulator, model path, environment variables, analyses, and simulator options.
  5. Choose Simulation – Run.
    When complete, the schematic appears so that you can select outputs and probe the design.
  6. Choose Outputs – Set from Schematic.
  7. Select the terminals in the schematic, or in the layout views of the blocks where parasitics were extracted, to define outputs.
    The only places where connections on different views are guaranteed to match are on component terminals.

Probing Parasitic Values

By probing the schematic or extracted view, you can examine the instances of parasitic components. To probe parasitic values, follow these steps.

Parasitic probing in the Diva flow only works for simple nets. For full probing on iterated instances, bus wires, and wire bundles, you should use the parasitic’s Assura flow. For more information, see
  1. In the LVS form, click the Parasitic Probe button.
    The Parasitic Probing form appears.
  2. In the Max list size field, specify how many parasitic instances to display.
  3. Sort parasitics by resistance or capacitance by selecting R or C.
  4. Click the appropriate button to specify which parasitics should be collected.
    • Click Whole Net and then select a net in the schematic or extracted view to display an ordered list of all the parasitics on the net. The largest resistances or capacitances appear at the top of the list.
      You can click the Save button in the displayed Parasitics for net... form to save a text file of the parasitic results.
    • Click Point to Point and then select two pins or instance pins (on the same net) in the schematic or extracted view to collect all the parasitics between two points.
    • Click Net to Net and then select two nets in the schematic or extracted view to collect parasitic capacitances between two different nets.

    A list of the collected parasitic instances appears. Select an instance from this list to highlight the component symbol associated with this parasitic on the extracted view.

Probing Using the Diva Probing Form

If you choose to probe on a net by selecting Tools – Diva – Verify – Probe, you should be aware that the only probing option supported here, by parasitic aware design in the Diva flow, is where you choose to select Probing Method: single w/o parasitics, and then click the Add Devs for Net option.

For information on using the Probing form, see the Verify Menu Commands chapter in the Diva Reference.
Iterated instances, bus wires, and wire bundles are only partially supported using Diva probe functionality. For full support of these, you should use the Assura flow as described in chapters 1 and 2.

Out of Context Probing

A cell view is said to be in context when it is the view that is “bound” via the configuration, that is, the view that is picked up by the simulator.

A view can therefore be classified as being out of context when it is not the current bound view. For example, if you want to use an analog_extracted view in your simulation, you need to set up a configuration that will override the default view for one or more instances, likely to be schematic, to be “analog_extracted”.

When you now simulate this design, any views that are bound to “analog_extracted” will be netlisted to include the parasitics in them.

Performing Out of Context Probing

To perform out of context probing, using the above example, you would therefore have to descend into a view that is not analog_extracted, e.g. the schematic view.

From here, you would perform simulation probing within that view, for example from the Analog Development Environment (ADE). Within the ADE, you would select either:

Results – Direct Plot – Transient Signal

or

Results – Plot Outputs – Transient Signal.

If you are attempting a full chip simulation of an analog_extracted view, this can occasionally fail during the reading of the design with an “out of memory” error. If this happens, it can be due to the chip being too big to simulate. The recommendation, if this occurs, is to break the chip up into smaller blocks and then simulate partially with extracted views and partially with schematic views.

Backannotating Parasitic Values

  1. Click the Backannotate button on the LVS form to backannotate the resistances and capacitances to the schematic.
    The Parasitic Backannotation form appears.
  2. Select the font size and label offsets that you want and click the Add Parasitics button.
    Resistance and capacitance labels appear on the schematic view. To see them, you might need to zoom in on a portion of the schematic.
The new information displayed on the schematic is for viewing only. Using the Add Parasitics button does not include the parasitics in the schematic.
  1. Click the Remove Parasitics button to remove these labels.
  2. Choose Print All to write all of the parasitics to a file.
    The Print All Parasitics form appears.
  3. Click the appropriate Sort Parasitics by button.
    Select R for a list sorted by resistance or C for a list sorted by capacitance.
  4. Specify the filename for the printed listing.

Diva Flow: Simulating Mixed-Signal Circuits with Parasitic Aware Design

The information in this section describes how you can use Cadence® tools to investigate the effect of parasitics on mixed-signal circuits. By accounting for the effect of parasitics, you can improve the accuracy of your circuit simulations. If your design includes only analog circuits, go to Diva Flow: Simulating Analog Circuits with Parasitic Aware Design.

This section comprises of the following topics:

For more information on Diva see the Diva Reference.

Overview

The flows in this section describe two ways to calculate delays for mixed-signal circuits.

The pre-layout flow is discussed in Estimating Delays (Pre-Layout) For information on using layout information to calculate delays, see Calculating Delays (Post-Layout).

Before following any of the flows in this chapter, be sure that the environment variable CDS_Netlisting_Mode is set to Analog. To ensure that all the tools for the flow are available, start your session with the command virtuoso.

For more information about the options you can use with the command to start the software, refer to the Virtuoso Design Environment User Guide.

Estimating Delays (Pre-Layout)

Even without layout information, you can obtain useful delay estimates of digital partitions by following the pre-layout mixed-signal parasitic aware design. The figure below illustrates how the Pearl timing analyzer operates on the digital netlist to produce a standard delay format (SDF) file. The parasitic aware design flow then annotates the SDF file to the top-level cell instance.

Setting Up for Pre-Layout Delay Estimation

To specify that delays are to be estimated, set up the Mixed Signal Options form as described in the following steps.

  1. Choose Simulation – Options – Mixed Signal in the Analog Design Environment Simulation window.
    The Mixed Signal Options form appears.
  2. If necessary, set the DC Interval and Max DC Iterations fields.
  3. Choose the Estimate (Pre-Layout) button.
    The MIxed Signal Options form expands to reveal related options.
  4. Edit the delay calculator files as necessary.

For guidance, see Preparing the pearl.cmd and gcfConstraints.gcf Files.

  1. Ensure that you have a correctly set up the SDF annotator file (sdf.cfg).

For more information, see Editing the SDF Annotator File.

Preparing the pearl.cmd and gcfConstraints.gcf Files

The Pearl timing analyzer requires two control files: pearl.cmd and gcfConstraints.gcf. The pearl.cmd file is the command initialization file for the Pearl timing analyzer. The gcfConstraints.gcf file specifies the boundary and operating conditions for the analysis and lists the compiled timing library format (CTLF) file to be used. You can do either of the following:

Locations Searched for the pearl.cmd and gcfConstraints.gcf Files

The Pearl timing analyzer searches for the pearl.cmd and gcfConstraints.gcf files in the following locations, which are searched in the order given.

  1. The run directory
    For example, if the simulation directory is $HOME/simulation, the run directory is
    $HOME/simulation/topLevelCellName/simulatorName/viewName/netlist/digital
  2. Your working directory (where you start virtuoso or icms)
  3. Your home directory ($HOME)
  4. Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)

Editing the pearl.cmd and gcfConstraints.gcf Files

You can change the contents of the gcfConstraints.gcf and pearl.cmd files as necessary.

  1. To change the gcfConstraints.gcf file, click the Constraints button in the Mixed Signal Options form. Your default text editor opens, displaying the contents of the file. For example, the file might contain information llike this.
    Change the design name to the name of your top-level design. Ensure that the path to the CTLF files is specified with one of the following.
    • An absolute path
    • A relative path defined with respect to the run directory

For more information about the run directory, see Locations Searched for the pearl.cmd and gcfConstraints.gcf Files.

Do not use a tilde (~) to specify the path.

When you finish editing the file, save it.

  1. To change the contents of the pearl.cmd file, click the Command button in the Mixed Signal Options form. The Command Options form appears.
  2. Set the options as required.
  3. Click OK.

Editing the SDF Annotator File

The simulator uses the sdf.cfg file to control the SDF annotation. An existing sdf.cfg file that you want the simulator to use must be located in one of the following locations, which are searched in the following order. These are the same locations searched for the pearl.cmd and gcfConstraints.gcf files.

  1. The run directory
    For example, if the simulation directory is $HOME/simulation, the run directory is
    $HOME/simulation/topLevelCellName/simulatorName/viewName/netlist/digital
  2. Your working directory (where you start virtuoso or icms)
  3. Your home directory ($HOME)
  4. Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)

To edit the sdf.cfg file, or to copy a template so that you can create a new sdf.cfg file,

  1. Click Config on the Mixed Signal Options form.
    The SDF Annotator Config File form appears.
  2. Change the values as necessary.

Simulating a Design with Pre-Layout Estimation

After you set up the mixed-signal simulation options, you are ready to simulate. Follow the standard mixed-signal simulation process.

Calculating Delays (Post-Layout)

Simulating a mixed-signal design with parasitics calculated from layout information involves the following major steps:

  1. Preparing cell libraries
  2. Creating a mixed_extracted view of your design
  3. Creating or modifying a configuration for the design so that mixed_extracted views are used for the mixed-signal simulation
  4. Using one of the mixed-signal simulators to simulate the configured schematic with parasitics included

The figures below shows the flow for steps 2 and 3 in graphical format. The Cadence RC network reducer steps are shown with dotted lines because they are optional.

Digital parasitics are calculated by the Pearl timing analyzer or can be imported from an external calculator. The SDF file created by the timing analyzer is annotated to the netlist at simulation time.

Preparing for Post-Layout Mixed-Signal Parasitic Aware Design

Before you can run a post-layout mixed-signal parasitic aware design, you must ensure that the necessary preliminary steps are complete. The following sections describe the tasks.

Preparing Libraries for Post-Layout Mixed-Signal Parasitic Aware Design

Ensure that the cells and primitives that you plan to use in a post-layout parasitic aware design have the following required views and information.

Analog cells must have

Analog primitives must have

schematic view

simulation stopping view

symbol view

auLvs view (the default stopping view for auLvs)

layout view (with ivCellType = “graphic” for
analog layouts with pins)

CDF simulation information

Digital cells must have

Digital primitives must have

symbol view

parasitic aware design view

logic view (verilog, for example)

CDF simulation information for LVS

schematic view

If you are using the Pearl timing analyzer, an entry in a compiled timing library format (CTLF) file

layout view (with ivCellType = “graphic” for
hierarchical digital blocks)

The following sections describe how to prepare some of this information.

Creating an parasitic View for a Digital Primitive

Each digital primitive must have an msps stopping view, which is required for layout versus schematic (LVS).

To create parasitic views:

  1. In the CIW, choose Tools – Mixed Signal Environment – Prepare Library for MSPS.
    The Create msps views & auLvs CDF simInfo form appears.
  2. Select the primitives for which you want to create msps views. As described below, you can either select the primitives manually or select primitives that have certain specified views.

Selecting Primitives Manually

To select primitives manually,

  1. Choose a cell from the Not in the Selected List list box, and click the right-arrow button to add it to the In the Selected List list box.
    To select more than one cell, click your first selection, then hold down the Control key and click the rest of your selections.
  2. To create an msps view for each cell in the In the Selected List list box, click OK or Apply and then click Yes in the create msps views confirmation form.

Selecting Primitives with Specified Views

To select primitives that have specified views,

  1. Click Select Cells.
    The Select Cell Views form appears.
  2. Change the View Choice List field as necessary.
    The views specified in the View Must List field and the View Choice List field become the selection criteria for digital primitives. To be selected, a cell must have all the views specified in the View Must List field and at least one of the views specified in the View Choice List field.
    For example, assume that View Must List contains layout and symbol and that View Choice List contains behavioral and auLvs. Then any cell that has a layout view, a symbol view, and either a behavioral view or an auLvs view meets the search criteria.
  3. Click OK or Apply .
    The search results appear in the In the Selected List list box on the Create msps views & auLvs CDF simInfo form.
  4. In the Create msps views & auLvs CDF simInfo form , click OK or Apply to create an msps view for each cell in In the Selected List .
  5. Confirm your actions by clicking Yes in the create msps views confirmation dialog box.
  6. If any of the selected cells have existing auLvs CDF siminfo, the create auLvs Siminfo confirmation dialog box asks you to confirm the overwrite.

Preparing Layout Views for Analog and Digital Cells

In macro mode, the extractor treats any cell with pins as a macro cell and stops expanding it. If a block is an analog block or a hierarchical digital block and requires further expansion, you need to add the property ivCellType = "graphic" to the layout master of the block. With this property set, the extractor expands the cell even though pins exist.

You can set the ivCellType property at the instance level or for multiple cells in the macroCellFile. Refer to the Diva Reference for details on either of these methods.

For example, the following procedure sets the ivCellType property at the instance level for a cell. With this method, every instance of this cell in the design has the same setting.

  1. Open in edit mode the layout view of the instance you want expanded to the transistor level.
  2. From the Layout window, choose Design – Properties.
    The Edit Cellview Properties form appears.
  3. Choose Property.
    The Edit Cellview Properties form expands.
  4. Click the Add button.

The Add Property form appears.

  1. Type ivCelltype in the Name field.
  2. Set the Type drop-down list box to String.
  3. Type graphic in the Value field.
  4. Click OK to add the new property and its value.

Updating View and Stop Lists for LVS

The .simrc file contains the view lists and stop lists for Diva® LVS. For mixed-signal parasitic aware design, you must update these lists with the msps view before you run LVS.

To update the lists,

  1. Open the .simrc file using any text editor.
  2. Add or update the following variable definitions in the .simrc file so that the msps view appears at the beginning of each list. For example, after you update the file, the definitions might look like this: 
    lvsSchematicViewList = 
 '( "msps" "auLvs"
 "schematic" "symbol")
    lvsSchematicStopList = 
 '( "msps" "auLvs")
    lvsLayoutViewList = 
 '( "msps" "auLvs"
 "extracted")
    lvsLayoutStopList = 
 '( "msps" "auLvs")
    For standard settings for these variables, refer to the Diva Reference.
  3. Save the .simrc file.

Preparing to Create the top.spf File

The Pearl timing analyzer uses a standard parasitic format (SPF) file called top.spf, which contains the parasitic information for your design. In preparation for creating this file, you must ensure that the property names for resistance and capacitance are set to r and c.

Creating mixed_extracted Views

For mixed-signal blocks, the extraction process consists of

  1. Verifying consistent pin direction in schematic and layout views
  2. Extracting parasitics and creating extracted views
  3. Comparing the schematic and extracted views
  4. Creating mixed_extracted views and (optional) using the Pearl timing analyzer to generate delay calculation files

The mixed_extracted views and the optional SDF files become input to the simulation of the top-level design.

You can run the extraction process on selected blocks within the design or on the entire design.

Verifying Consistent Pin Direction

To verify that pin directions on the schematic and layout views are consistent,

  1. From a window displaying the layout or extracted view, choose Verify – MSPS Check Pins.
    The MSPS Check Pins form appears.
  2. Click OK.
    The CIW displays a list of any discrepancies. Fix them before you extract the parasitics.

Extracting Parasitics and Creating Extracted Views

To extract parasitics and create extracted views,

  1. From a window displaying a layout view of the cell, choose Verify – Extract.

The Extractor form appears.

  1. Choose macro cell for Extract Method.
    This allows the digital cells to be extracted at the macro level.
    Be sure that any analog blocks have the ivCellType property set to graphic. This ensures that the analog blocks are flattened. For more information, see “Preparing Layout Views for Analog and Digital Cells”.
  2. Choose Join Nets With Same Name (optional).
    This ensures that nets with the same name are joined automatically.
  3. Click Set Switches to select the type of parasitics you want extracted.
    The Set Switches form appears. The parasitics displayed vary, depending on the extraction rules file defined for your design. In some cases, you do not need to make any selections.
    To select more than one item, click your first selection, then hold down the Control key and click the rest of your selections.
  4. Click OK.
    The Extractor form reappears with the parasitics you selected in the Switch Names field.
  5. Click OK or Apply to create the extracted views.
    A message in the CIW tells you when the extraction process is complete.

Comparing Schematic and Extracted Views

To compare the schematic view with the extracted view created earlier, follow these steps.

  1. From a window displaying the extracted view, choose Verify – LVS.
    The LVS form appears.
    For more information on the LVS form see Verify Menu Commands in the Diva Reference.
  2. Depending on which views are open, use one of the following procedures to identify the schematic and extracted views that you want to compare.
    If both the schematic and extracted views are open If only the extracted view is open
    1. Click the Sel by Cursor button below the schematic detail, then click the cursor in the open schematic view.
    2. Do the same for the extracted view.
    1. Click the Sel by Cursor button below the extracted detail, then click the cursor in the open extracted view.
    2. Click the Browse button below the schematic detail and select the schematic view.
  3. Fill in the names of the rules file and rules library for the Diva LVS rules.
  4. Click the Run button near the bottom of the form to begin the comparison.
  5. When the comparison finishes, click Info.

The Display Run Information dialog box appears.

  1. Click Log File.
    Scroll through the log file to the netlist comparison section near the end of the file. This section identifies any mismatches between the two files. Each error is described in the sections following the comparison results.
    Not all mismatches are fatal. Look over the comparison results to determine if you need to correct one of the files and redo the extraction and comparison, or if you can proceed with the views as they are.
  2. Choose File – Close Window in the log file window.
  3. Click Cancel in the Display Run Information dialog box.
  4. Correct any problems in the schematic or extracted views.
  5. If necessary, rerun the comparison and compare the results.

Building a Mixed_Extracted View

When the comparison between schematic and extracted views is acceptable, you need to select the parasitics to use for simulation. You also need to build the mixed_extracted view.

  1. In the LVS form, click Build Mixed.
    The Build Mixed Extracted View form appears.
  2. Verify that the Library, Cell, and View fields correctly specify the configuration view that you want to use.
    If your design does not have a configuration view associated with it, refer to the Cadence Hierarchy Editor User Guide and create a configuration.
    The msps view, used as the digital stopping view for LVS, is also used as the internal stopping view for SPF generation when the build mixed process runs. Be sure the configuration stopping view stops at digital cells that have an msps view.
  3. Select one of the following options to specify the analog parasitics that you want to use for simulation.
    Select If you want to

    Include All

    Simulate with all the parasitics that have been extracted

    Set From Schematic

    Select parasitics to include in the simulation by placing special symbols (spresistors and spcapacitors) on nets in the schematic view.

    The parasitics you select are the only ones included in the simulation.

    The special symbols are available in the sbaLib library.

    If you choose Set From Schematic and click OK without identifying any nets on the schematic, the Analog Parasitics Selective Annotation form asks you to confirm your choice.

    None

    Simulate with none of the parasitics
  4. Ensure that the pearl.cmd and gcfConstraints.gcf files are ready and available in one of the following locations, which are searched in the order given.
    • The run directory
      library_path/cell/view/mixed_extracted/layout_msb
    • Your working directory (where you start virtuoso or icms)
    • Your home directory
    • Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)

    For guidance on using the Command and Constraints buttons to view or change these files, see Preparing the pearl.cmd and gcfConstraints.gcf Files. When the files are ready, turn on the Calculate button in the Digital Delays section.
    If you click OK without editing the pearl.cmd and gcfConstraints.gcf files or without ensuring that the files are available in the searched directories, the Delay Calculator Option Files message window is displayed.
  5. Click Yes if you want to use the default templates for the option files.
  6. To build the mixed_extracted view, click OK in the Build Mixed Extracted View form.

The build mixed process removes all digital parasitics and places them in the SPF file. The Pearl timing analyzer uses the SPF file to calculate the delays and generate an SDF file. The mixed_extracted view contains analog parasitics and analog and digital instances for netlisting and simulation.

The build mixed process creates or places the following files in the layout_msb directory.

Filename Description

msbCheckFile

Timestamp file specifying the SPF creation time

msbEnableFlag

Zero-length file that indicates the Pearl timing analyzer is on, and enables sdfAnnotate

pearl.cmd

Command initialization file for the Pearl timing analyzer

gcfConstraints.gcf

File that defines constraints, operating conditions, and compiled timing library format (CTLF) files used by the Pearl timing analyzer

top.spf

Detailed SPF file with digital parasitics

top.tmp.sdf

SDF file generated by the Pearl timing analyzer delay calculation

annotate.com

File that contains a $sdf_annotate command with the location of the top.sdf file

runPearl.log

Error and log file

Modifying the Configuration

To use parasitic aware design, you must specify mixed_extracted as the View To Use for each cell in your top-level design for which you want the extracted parasitics simulated.

To specify mixed_extracted as the View To Use, you modify the configuration for your top-level design. If your design does not have a configuration, refer to the Cadence Hierarchy Editor User Guide to create one.

To modify a configuration,

  1. Open the Hierarchy Editor and specify the configuration for your top-level design.
  2. Use one of the following methods to specify the mixed_extracted view for the cells or blocks for which you want parasitics simulated.
    To specify views for individual blocks To specify views for multiple blocks
    1. In the Instance Binding section of the Hierarchy Editor window, position the cursor in the View To Use column of the appropriate block.
      If the Instance Binding section is not visible in the window, choose View – Instance Table to display this section.
    2. Press the right mouse key to display a list of commands.
    3. Choose Select View to display the list of views for this block.
    4. Select mixed_extracted as the view for this block to update the View Found and View To Use fields.
    1. Add mixed_extracted as the first view in the Global Bindings View List text field. This ensures that the mixed_extracted view is the selected view for every cell that has a mixed_extracted view.
  3. Choose View – Update to reconfigure the design to reflect your changes.
  4. To save the configuration with your changes, choose File – Save.
  5. To close the Hierarchy Editor, choose File – Exit.

Partitioning is done automatically by comparing the Global Bindings Stop List field and the Analog and Digital Stop View Sets.

Setting the Mixed-Signal Simulation Options

To set up the Mixed Signal Options form for post-layout delay calculations,

  1. Choose Simulation – Options – Mixed Signal in the Analog Design Environment Simulation window.

The Mixed Signal Options form is displayed.

  1. If necessary, set the DC Interval and Max DC Iterations.
  2. Click the Use Existing (Layout) radio button.
    The form expands to allow you to use SDF files created during the build mixed process and to import SDF files.
  3. To use the SDF files created during the build mixed process, turn on the SDF From Mixed Extracted View button.
  4. To import SDF files created by a different tool, turn on the Import SDF Files button and fill in the associated fields.
    • In the File field, type the path to and filename of the SDF file that you want to import. The name you enter must be a legal Verilog® language name.
    • In the Scope field, type the hierarchical scope of the instance for which the delay file is to be annotated during simulation. For example, you might type something like I1/I3 to indicate an instance one level down in the hierarchy.
  5. If you want to import more SDF files, click the Import More button and fill in the Import SDF Files form as described in Importing Additional SDF Files.

Importing Additional SDF Files

The Mixed Signal Options form provides space for you to enter the name of one SDF file to be imported. If you want to import more than one SDF file, click the Import More button to open the Import SDF Files form.

To use the form,

  1. Type a number from 2 to 10 in the Number of Additional Files To Import field.
    The form expands to accommodate the information that you want to enter.
  2. For each additional file, type the name of the SDF file to be imported.
  3. For each additional file, type the hierarchical scope of the instance for which the delay file is to be annotated during simulation.

Simulating a Design (Post-Layout)

After you set up the configuration for the parasitic cells, you are ready to simulate the configured schematic using one of the mixed-signal simulators. Follow the standard mixed-signal simulation process.

Probing Parasitic Values

Although it is not required, you might want to probe the instances of parasitic components.

To probe parasitic values in the schematic or extracted views,

  1. In the LVS form, click the Parasitic Probe button.
    The Parasitic Probing form appears.
  2. In the Max list size field, specify how many parasitic instances to display.
  3. Sort parasitics by resistance or capacitance by selecting R or C.
  4. Click the appropriate button to specify the parasitics to be collected.
    • Click Whole Net and then select a net in the schematic or extracted view to display an ordered list of all the parasitics on the net. The largest resistances or capacitances appear at the top of the list.
      You can click the Save button in the displayed Parasitics for net... form to save a text file of the parasitic results.
    • Click Point to Point and then select two pins or instance pins (on the same net) in the schematic or extracted view to collect all the parasitics between two points.
    • Click Net to Net and then click two nets in the schematic or extracted view to collect parasitic capacitances between two different nets.

    A list of the collected parasitic instances appears.
    Select an instance from this list to highlight the component symbol associated with this parasitic on the extracted view.
  5. To backannotate the resistances and capacitances to the schematic view, click the Backannotate button on the LVS form.
    The Parasitic Backannotation form appears.
  6. Select the font size and label placement that you want and click the Add Parasitics button.
    Resistance and capacitance labels appear on the schematic view. To see them, you might need to zoom in on a portion of the schematic. The new information displayed on the schematic is for viewing only. Using the Add Parasitics button does not include the parasitics in the schematic.
  7. To remove these labels, click the Remove Parasitics button.
  8. To write all of the lumped parasitics to a file, click Print All.
    The Print All Parasitics form appears:
  9. Click the appropriate Sort parasitics by button.
    Select R for a list sorted by resistance or C for a list sorted by capacitance.
  10. Specify the filename for the printed listing.Even though you are simulating from the mixed_extracted view of the design, you can probe signals from the schematic view. This is called out-of-context probing. You can also probe the mixed_extracted view directly for analog and mixed nets.
    When you probe different types of signals (analog, digital, or mixed), keep in mind which nets exist in the mixed_extracted view. Probing a net or a terminal at a level of the schematic that does not have a simulation waveform causes a probing error.

    Because analog components are flat in the mixed_extracted view, you cannot probe nets connected to terminals of hierarchical analog blocks. You must descend to the transistor level of the schematic to probe these nets. It is only at the transistor level that the program can map terminals from the schematic to the mixed_extracted view.

To probe a signal, click the wire at a point close to the terminal. The probe automatically jumps to the closest terminal on that net. An X appears on the selected terminal as shown in the following figure.

You can select several terminals on the same net. Each selected terminal is marked with a different color X. The associated waveform displays in the same color as the X on the schematic.

You can select and probe only real geometries from a mixed_extracted view. For example, if the metal layer is broken up into resistors, the geometries do not have connectivity. In this case, you need to probe the metal layer at contacts and vias.

If you are unable to select a geometry on the mixed_extracted view, the layer might be invalid. Set valid layers from the Edit menu of the LSW form.

If you probe a net that cannot be mapped to a terminal in the mixed_extracted view, warnings similar to the following appear:

*WARNING* Could not obtain the external name
*WARNING* Unable to map net 'VBG'
*Warning* no valid full path name for net "VBG", selection not taken

You can probe mixed-nets connected to terminals of hierarchical analog blocks near the digital terminal, but not near analog terminals, as shown in the following figure.

The D2A and A2D elements are attached to the digital components in the netlist. The output of the D2A element or the input of the A2D element, therefore, is a valid analog net in the extracted view.

Because digital parasitics are removed from the mixed_extracted view, digital nets can be probed anywhere and do not have to be associated with terminals. An X is placed in the middle of the net indicating its selection.

For information on probing views that are out of context, see Out of Context Probing.

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