Product Documentation

Diva Reference
Product Version IC23.1, June 2023

Contents

Preface

Related Documents

Typographic and Syntax Conventions

SKILL Syntax Examples

1

Introducing Diva Verification

Diva Verification Tool Set

Diva Verification Programs

Diva Verification Product Flow

Prerequisites for Diva Verification

Design Framework II

Simulation Environment

Verification Rule File

Using Diva Verification

About the Mouse

Using the Verify Menu

2

Running Diva Verification

Interactive Mode

Controlling Diva Verification

Controlling Run Modes Using Properties

Creating a Log File

Using Checkpoints

Conditional Execution of Rules

Default ivIf Switch Values

Rules File Example

Controlling SKILL Access

Special Procedures

Controlling Properties and Variables

Storing Temporary Files

Including and Excluding Cells

Macro Cell Mode

Using Cadence Environment Variables With Diva

Environment variables affecting the DRC form

Environment variables affecting the LVS form

Other environment variables

3

Executing Diva Verification Using SKILL Commands

4

Writing Diva Verification Rules

Creating a Verification Rules File

Grouping Commands

Nesting Commands

Compiling and Optimizing Commands

Using Wildcards

Sample Verification Rules File

ERC and LVS Verification Rules

Sample ERC Rules File

Sample LVS Rules Files

Sample CMOS Rules File

Sample Bipolar Rules File

Creating a Run-Specific File

includeValueFunc

Sample Run-Specific File

Writing Rules for use by Diva and Assura

5

Layer Processing Concepts

Edge Boolean Commands

Invalid Graphics Data

Exclusive Selection

Data Integrity Checks

Graphic Layer Access Commands

geomArrayShapes

geomCellBoundary

Logical Commands

Relational Selection Commands

Sizing Commands

geomStretchCorner

General Selection Commands

geomContactCheck

geomEncloseRect

geomGetAdjacentEdge

geomGetAngledEdge

geomGetNonRectangle

geomGetRectangle

geomGetUnTexted

Generation Commands

geomGetLayerBBox

Layer Storage and Removal

6

Connectivity Extraction Concepts

How Connections Are Formed

Connectivity Commands

7

DRC Overview

Modes of Operation

Area Halo Processing

DRC Limitations

How DRC Performs Checks

Looking Through the Wall

Check Conjunction

Alignment and Registration

Cell-Based Options

Checking Commands

drcAntenna (old syntax)

drcAntenna (new syntax)

geomGetCoverage

drcDenseLineEnd

Check Modifiers

cornerToEdge, cornerToEdgeA, cornerToEdgeB

corner, cornerA, cornerB

length, lengtha, lengthb

opposite, oppositeA, oppositeB

shielded, shieldedA, shieldedB, shielded(layer)

Output Modifiers

edge, edgea, edgeb

fig, figa, figb

wholeEdge, wholeEdgea, wholeEdgeb

Alignment and Registration Modifiers

Other Modifiers

8

Models of Device Extraction

Macro Cell Mode

Full Hierarchical Mode

Incremental Hierarchical Mode

Device Recognition

Using Device Recognition

Device Recognition Polygons

Processing Pins

Device Extraction Commands

saveInterconnect

saveRecognition

9

Extracting Parameters (LPE)

Measurement Process

Measurement Commands

NULL Measurements

Measurement Optimization

Parameter Measurement Reference Commands

calculateParameter

measureParameter

10

Extracting Parasitics (LPE)

Netlisting Parasitics

Measurement Operators

NULL Measurements

Measurement Optimization

Parasitic Measurement Commands

calculateParasitic

complexParasitic

measureParasitic

multiLevelParasitic

attachParasitic

11

Extracting Parasitic Resistance (PRE)

What Is Parasitic Resistance Extraction?

How Do I Invoke It?

What Are the Results?

The Extraction Process

Resistor Formation

Contact Resistance

Edge Resistance

Area Resistance

Device Terminals

Bend Resistance

Transition Resistance

Network Reduction

Cross Coupling and Fringe Capacitance

Resistor Body Capacitance

Netlisting R-C Models

Multiple Layer Extraction

Unexpected Results

A Simple Approach

A Better Approach to get More Accurate Results

Using Shorts to Reduce Large Contact Array Resistor Networks

Command Reference

measureResistance

12

Checking Electrical Rules (ERC)

Program Functionality

Reducing Networks

Consolidating and Testing Parameters

Tracing and Connectivity Commands

checkDeviceNetCount

checkFloatingDevices

checkFloatingNets

checkNotConnected

checkOneNetDevices

checkOneTerminalNets

checkPullUpAndDown

Gates and Parameters Commands

displayFeedBackLoops

displayGateErrors

testDeviceProperty

testGateProperty

13

Comparing Layout to Schematic (LVS)

Verification Rules Functions

Permutating Devices

Ignoring Device Terminals

Ignoring Extraneous Devices

Removing Unwanted Devices

Parameter Analysis

Correspondence Points

Network Terminal Processing

Comparing Macro Cell

Working and Information Files

LVS Ambiguity File

Displaying Errors

Unmatched Instances

Unmatched Parameters

Unmatched Terminals

Pruned Instances

LVS Verification Rules Commands

compareDeviceProperty

parameterMatchDegree

parameterMatchType

Backannotation (lvsbx)

14

Verify Menu Commands

Extract Command

ConcICe Command

Inherited Connections for LVS in Diva Verification

Markers Command

15

Short Locator

How Short Location Works

Short Locator Form

Running Extraction

Adding Short Locator Labels

Deleting Short Locator Labels

Dealing with complex shapes

Restoring a previous run

Ending Short Locator

A

What’s New In Diva

B

Translating Dracula Files

Dracula To Diva Verification Translator: DraculaToDiva

Running DraculaToDiva

What Happens During Translation?

Dracula To Diva Verification Command Correspondence

Checking Philosophy

Translation Pitfalls

C

Improving Hierarchical DRC Performance

Assigning the hdrc boundary Layer

How the hdrc boundary Layer Works

Hierarchical DRC Switch Names

Rules File Example

D

Simulation and Environment Control

Directories and Files

Setting Up the Netlister

E

Application Techniques

Bipolar Processing

General Technique

Resistor Terminal Recognition

Extraction Device Library Entries

Substrate, Background, and Ground

Index

⠀ X