Reference

Model Equations

Some important model equations are listed as following for your reference:

Basic Equations Solved in the HiSIM SOI Core Part

Though all following descriptions are written for the n-channel MOSFET, they are also valid for the p-channel case. The Poisson equation solved in HiSIM SOI together with the Gauss law and boundary conditions together with the approximation of the linearly decreasing carrier density to the depth direction are

where Q’s are charges induced within the SOI-MOSFET as depicted in 32-4 and Q_h is the excess charge in the SOI layer due to the impact ionization, and

where VFBC is the flat-band voltage, TFOX is the physical gate-oxide thickness, and is the threshold voltage shift in comparison to the threshold voltage of a long-channel transistor [4]. is the permittivity of Si0₂. are the permittivity of vacuum and the dielectric constant of SiO₂, respectively.

Eqs. (6)– (8) are solved simultaneously within HiSIM SOI. For the body-tied case, the potential node is connected to the external node potential and solved by the circuit simulator. The solution takes place at source side and drain side. Prior to the Newton iteration, an approximated, analytical initial value for each variable is estimated in the code.

Figure -4 Band structure of SOI-MOSFET and generated charges

All device characteristics are determined on the basis of the charge control by applied voltages. All charges induced within SOI-MOSFET are functions of surface potentials written as

Drain Current

Under the gradual-channel approximation with further approximations of an idealized gate structure and uniform channel doping, the drain current I_ds is written as:

Threshold Voltage Shift

The surface-potential-based model requires no threshold voltage V_th in its core description of the model. However, HiSIM SOI has opted for modeling various submodels such as short-channel effects as a V_th shift from an otherwise ideal case.

The whole contribution to the V_th is summarised as

V_th = V_{th, SC}+ V_th,R + V_th,P + V_th,SCR + V_th,W + V_th,sm - S_pg

The modeled V_th is incorporated in the S iteration can be viewed as consisting of two main effects or components:

(I) the short-channel effect: V_{th, SC}

(II) the reverse-short-channel effect: V_{th, R} and V_{th, P}

The separation into these two components ( V_th = V_{th, SC} + V_{th, R} (or V_{th, P})) is schematically shown in Figure 32-5.

Figure -5 Schematic plot of the separation of Vth into the contributions of the short-channel and the reverse short-channel effect.

Mobility Model

The low-field mobility is described with the following expressions and includes the three independent mechanisms of Coulomb, phonon and surface-roughness scattering:

Channel-Length Modulation

As the gradual-channel approximation is not valid for large V_ds causing the pinch-off phenomenon in the channel. Without taking into account the pinch-off phenomenon, the calculated channel conductance gds enters abruptly into the saturation condition. To include the pinch-off phenomenon in HiSIM, we apply the conventional method of modeling the pinch-off region ( L) separately from the rest of the channel as depicted in Figure 32-6:

Figure -6 Schematic showing the correlation among physical quantities in the pinch-off region.

After taking into all effects, the final L is derived as:

Narrow-Channel Effects

The V_th reduction for reduced channel width (W_gate) is modeled under inclusion of the edge-fringing capacitances C_ef at the edge of the trench as:

Temperature Dependences

The temperature dependence is included automatically in the surface potentials through , which is the inverse of the thermal voltage. Additionally the band gap, the intrinsic carrier concentration, the carrier mobility, and the carrier saturation velocity are also temperature dependent.

Drain-side resistance

Source-side resistance

Gate resistance

Capacitance

Intrinsic Capacitance

The intrinsic capacitances are derivatives of the node charges determined as

Overlap Capacitance

To consider the overlap capacitance, the flag COADOV must be selected to 1, which is the default. The overlap capacitance includes three options as summarized in 32-7, where the drain side and the source side are treated as identical. If Flag COOVLP=0, the overlap capacitances are treated to be constant. If CGSO and CGDO are defined, these values are taken. If they are not defined, the values are calculated with the overlap length LOVER and oxide capacitance CFOX.

Figure -7 Model options of the overlap capacitance at the drain side are summarized.

Gate-Fringing Capacitance

The outer fringing capacitance is modeled as

Leakage Currents

Substrate Current

The substrate current is derived as

where

and X_j is the junction depth.

Gate Current

All possible gate leakage currents are schematically shown in Fig. 32.8

Between Gate and Channel, I_gate

Between Gate and Bulk, I_gb

The I_gb current under the accumulation condition is modeled as

Between Gate and Source/Drain, Igs/Igd

GIDL (Gate-Induced Drain Leakage)

Floating-Body Effect Model

Model selector COFBE as well as COISUB must be set to 1 to activate FBE model. In HiSIM SOI, Q_h is modeled as follows:

History Effect Model

Time constant for the history effect is modeled as:

where HIST1 and HIST2 are history effect model parameters.

Self-Heating Effect Model

The self-heating effect is modeled as a C-R thermal network with a heat resistance parameter RTH0 and capacitance parameter CTH0. The flag COSELFHEAT must be equal to 1 and RTH0 must not be equal to zero to activate this model. The SHE should be switched on/off only with the model flag COSELFHEAT.

Figure -8 Thermal Network applied for the self-heating effect

Source/Body and Drain/Body Diode Models

Diode Current

Between drain and body

The forward and backward currents between drain and body are calculated as:

The drain-body current equations are derived as follows:

Between source and body

Body-Tie Models

HiSIM SOI considers both the floating-body and the body-tie structures.

Body-Contact Capacitances

ABTN = LBT ·WBTN

ABTP = LBT ·WBTP

Overlap capacitance of body-tie area

The capacitance between the body-tied gate (hammer head) and the body-tied well is treated as MOS capacitance.

C_gb,bt = C_btN · ABTN + C_btP · ABTP

Overlap capacitance of body-tie periphery

Instance parameters PSBCP and PDBCP are introduced to take into account the overlap capacitance of the periphery of the body-tie contact. These lengths are added to the W_effc as:

W_effc,source = W_effc + PSBCP

W_effc,drain = W_effc + PDBCP

where

W_effc = W_gate - NBT · XWDBT- (2 - NBT) · XWDC

Diode current of body-tie periphery

The diode current also flows at the body-tie periphery. Therefore the lengths determined by the instance parameters PSBCP and PDBCP are added the width as

W_eff,source = W_eff + PSBCP

W_eff,drain = W_eff + PDBCP

where

W_eff = W_gate - NBT · XWDBT- (2 - NBT) · XWD

Gate-Fringing Capacitance

For body-tied devices, an additional gate-fringing capacitance is considered between gate and body:

Noise Models

1/f Noise Models

The 1/f noise is caused by both the carrier fluctuation and the mobility fluctuation. The final description for the drift-diffusion model is

where the parameters NFALP and NFTRP represent the contribution of the mobility fluctuation and the ratio of trap density to attenuation coefficient, respectively.

Thermal Noise Model

Van der Ziel derived the equation for the spectral density of the thermal drain-noise current at temperature T by integrating the trans-conductance along the channel direction y based on the Nyquist theorem

where _s, _d and _av are mobilities at the source side, the drain side, and averaged, respectively.

Induced Gate Noise Model

Coupling Noise Model

Non-Quasi-Static (NQS) Model

Formation of carrier

Carriers in the channel take time to build-up as opposed to the Quasi-Static (QS) approximation. To consider this phenomenon in HiSIM, the carrier formation is modeled as

where q(t_i) and Q(t_i) represent the non-quasi-static and the quasi-static carrier density at time ti, respectively, and t = t_i – t_i-1 is valid. Above equation implies that the formation of carriers under the NQS approximation is always delayed in comparison to the QS approximation, which is the basic origin of the NQS effect.

Delay Mechanisms

Weak inversion

Strong inversion

These two delay mechanisms (diffusion and conduction) are combined using the Matthiessen rule:

Applying the same approach for the formation of bulk carriers, leads to the approximation of the bulk carrier delay as an RC delay in the form

Component Statements

Instance Parameters

Refer to the following table for Instance Parameter details:

Gate length (Lgate).
Gate width (Wgate).
Area of drain junction.
Area of source junction.
Perimeter of drain junction.
Perimeter of source junction.
Number of gate contacts.
Distance from gate contact to channel edge.
Offset of gate length.
multiplicity factor.
Number of gate fingers.
Length of diffusion between gate and STI.
Length of diffusion between gate and STI.
Length of diffusion between gate and gate.
Parasitic perimeter length for body contact at drain.
Parasitic perimeter length for body contact at source.
diffusion length between gate and STI edge.
Device temperature.
Device temperature change.
Device temperature change.
Number of body contact.
Length of gate over body-contact well.
Distance of gate protrusion over body-contact well.
Distance of gate protrusion over body-contact well.
Area of N^+ poly area of body contact.
Area of P^+ poly area of body contact.
Number of squares in source .
Number of squares in drain .
Parameter for drift region length (drain) .
Parameter for drift region length (source) .
Substrate resistance network.
Substrate resistance network.

Model Definition

model modelName hisimsoi parameter=value ...

Model Parameters

Refer to the following table for Model Parameter details:

Gate length (Lgate).
Gate width (Wgate).
Maximum width for the model.
Minimum width for the model.
Maximum length for the model.
Minimum length for the model.
Previous phi_s flag.
Lateral field induced and overlap capacitances are added to intrinsic.
Substrate current flag.
Floating-Body Effect flag.
Gate current flag.
GIDL current flag.
Overlap capacitance model selector.
Induced gate and cross correlation noise flag.
1/f noise flag.
Thermal noise flag.
STI leakage current flag.
Non-quasi-static model flag.
Gate-contact resistance flag.
Valence-band-electron-tunneling-current model flag.
History Effect flag.
Self-Heating flag.
Symmetry treatment flag.
Lgate to Leff flag.
Qover capacitance model selector.
Gate/body contact well MOS-capacitance model selector.
Body contact node flag.
Switch scaling for Isub.
Switch Isub in FB mode: 0 with analytical Ids; 1 with iterative Ids.
print information selector.
Upper limit Qhs .
Delta VGPSUB (in addition to VFBSUB).
Delta VBSSUB for Qh effect.
1 for nMOS and -1 for pMOS.Possible values are p and n.
Model parameter version accepts only real number values, like 1.30 for version=1.3.0. The available versions are 1.30 and 1.40. Default version is 1.40.
Saturation velocity.
Temperature dependence of bandgap.
Temperature dependence of bandgap.
Bandgap.
Gate overlap length.
XLD for capacitance.
Flat-band voltage in overlap region.
Impurity concentration in overlap region.
Gate overlap width.
XWD for cap.
Reference distance from STI edge to Gate edge.
Reference distance from STI edge to Gate edge.
Distance from junction to max field point.
Vbs-dependence of Qy.
Lgate-dependence of Qy.
Gate sheet resistance.
Flat-band voltage.
Built-in potential.
Modification of pocket-impurity concentration.
Modification of pocket-impurity concentration.
SOI SCE parameter.
Depletion width of channel/contact junction.
Pocket penetration length.
Max pocket concentration.
Modification of pocket concentration for narrow W.
Modification of pocket concentration for narrow W.
Small-size effect parameter for STI leakage.
Small-size effect parameter for STI leakage.
Threshold voltage shift due to small-size effect.
Threshold voltage shift due to small-size effect.
Magnitude of short-channel effect due to pocket.
Vds-dependence of SCE due to pocket.
Vds-dependence of SCE due to pocket.
magnitude of short-channel effect.
Vds-dependence of short-channel effect.
Vbs dependence of short-channel effect.
Parameter for SCE via BOX.
Parameter for SCE via BOX.
Parameter for SCE via BOX.
Strength of poly-depletion effect.
Threshold voltage of poly-depletion effect.
Lgate-dependence of poly-depletion effect.
Depletion charge contribution to Eeff.
inversion charge contribution to Eeff.
inversion charge parameter.
Coulomb scattering.
Coulomb scattering.
Phonon scattering.
Phonon-related mobility reduction.
Phonon-related mobility reduction.
L-dependence of phonon mobility reduction.
L-dependence of phonon mobility reduction.
Mobility change due to small size.
Mobility change due to small size.
Temperature-dependence of saturation velocity.
Threshold voltage shift.
Surface-roughness scattering.
Surface-roughness scattering.
L-dependence of surface roughness on mobility.
Surface roughness-related mobility change.
Surface roughness-related mobility change.
L-dependence of surface roughness on mobility.
Temperature-dependence of phonon scattering.
High-field-mobility degradation.
Smoothing coefficient for Vds.
Lgate-dependence of smoothing coefficient.
Lgate-dependence of smoothing coefficient.
Substrate current coefficient of magnitude.
Substrate current coefficient of exponential term.
Lgate-dependence of SUB1.
Lgate-dependence SUB1.
Lgate-dependence of SUB2.
Substrate current dependence on Vds.
Substrate current dependence on Lgate.
Substrate current dependence on Vbs.
Lgate-dependence of SVBS.
Lgate-dependence of SVBS.
Substrate current dependence on Vgs.
Lgate-dependence of SVGS.
Lgate-dependence of SVGS.
Wgate-dependence of SVGS.
Wgate-dependence of SVGS.
Substrate current dependence on Lgate.
Substrate current dependence on Lgate .
Flatband voltage for Isub calculation.
Lgate-dependence of VFBSUB.
Lgate-dependence of VFBSUB.
Smoothing parameter (hisimsoi_fb only).
History-effect parameter.
History-effect parameter.
FBE parameter.
FBE parameter.
Electron tunneling from valence band.
Electron tunneling from valence band.
Electron tunneling from valence band.
Vbs dependence of Fowler-Nordheim current.
impact-ionization-induced bulk potential change.
impact-ionization-induced bulk potential change.
Substrate impurity concentration at STI edge.
Width of high-field region at STI edge.
Channel-length dependence of WSTI.
Channel-length dependence of WSTI.
Channel-width dependence of WSTI.
Channel-width dependence of WSTI.
The same effect as SC1 but at STI edge.
The same effect as SC2 but at STI edge.
Threshold voltage shift due to STI.
Vds dependence of STI subthreshold.
Mobility change due to diffusion length.
Mobility change due to diffusion length.
Mobility change due to diffusion length.
Pocket concentration modifier.
Pocket concentration modifier.
Pocket concentration modifier.
Channel concentration modifier.
Channel concentration modifier.
Channel concentration modifier.
Height of poly-Si gate for fringing cap.
Gate-to-B overlap cap.
Gate-to-drain overlap cap.
Gate-to-source overlap cap.
Coefficient for overlap capacitance.
Coefficient for overlap capacitance.
Saturation current density.
Emission coefficient.
Temp coefficient for forward current densities.
Temp coefficient for reverse current densities.
Diode threshold voltage at junction.
Reverse current coefficient.
Bottom junc cap/unit area at zero bias.
Sidewall junc cap grading coefficient.
Sidewall junc cap per unit length at zero bias.
Bottom junc cap grading coefficient.
Sidewall junc cap grading coefficient.
Gate sidewall junc cap grading coefficient.
Bottom junc built-in potential.
Sidewall junc built-in potential.
Gate sidewall junc built-in potential.
Overlap length.
Hardness coefficient of channel/contact junction.
Coefficient for QB contribution.
Coefficient for QI contribution.
CLM parameter.
CLM parameter.
Velocity overshoot effect parameter.
Leff-dependence of velocity overshoot.
Modification of max velocity due to small size.
Modification of max velocity due to small size.
Threshold voltage change due to cap change.
Substrate concentration modifier.
Substrate concentration modifier.
Upper limit of substrate concentration.
Lgate-dependence of substrate concentration .
Lgate-dependence of substrate concentration .
Vgs-dependence of quantum mechanical effect.
Vgs-dependence of quantum mechanical effect.
Minimum Tox modification.
Magnitude of GIDL.
field-dependence of GIDL.
Vds-dependence of GIDL.
Threshold for Vds dependence.
High-field correction.
Vb-dependence of GIDL.
Gate-to-channel current coefficient.
Gate-to-channel current coefficient.
Gate-to-channel current coefficient.
Gate-to-channel current coefficient.
G-t-C short channel correction.
G-t-C Vds-dependence correction.
G-t-C L and W dependence correction.
G-t-S/D current coefficient.
G-t-S/D current coefficient.
G-t-S/D current coefficient.
G-t-S/D current coefficient.
G-t-S/D current coefficient.
G-t-S/D current coefficient.
Symmetry conservation coefficient.
Symmetry conservation coefficient.
Ratio of trap density to attenuation coefficient.
Contribution of mobility fluctuation.
Cap caused by the interface trapped carriers.
Power of f describing deviation of 1/f.
Temperature selected as a nominal value.
Coefficient for delay due to diffusion of carriers.
Coefficient for delay due to conduction of carriers.
Coefficient for RC delay of bulk carriers.
Front oxide thickness.
Silicon film thickness.
Impurity doping depth.
Buried oxide thickness.
SOI layer impurity concentration.
Substrate impurity concentration.
Thermal resistance.
Thermal capacitance.
SCE parameter.
Punchthrough parameter.
Punchthrough parameter.
Punchthrough parameter.
Punchthrough parameter.
Strength of high-field effect.
Modification of channel conductance.
Modification of channel conductance.
Punchthrough parameter.
Punchthrough parameter.
Surface potential limiter.
Minimum resistance.
Phonon scattering.
Parameter for drift region length (drain) .
Parameter for drift region length (source) .
Source side resistance OFF(0)/ON(1).
Drain side resistance OFF(0)/ON(1).
Bulk resistance OFF(0)/ON(1).
Activate body resistance net (1) or not (0).
Drain diffusion sheet resistance .
impurity concentration in overlap region.
Mobility in drift region (drain).
Mobility in drift region (source).
Saturation velocity in drift region (drain).
Saturation velocity in drift region (drain).
Saturation velocity in drift region (source).
Temperature dependence of resistance.
Temperature dependence of resistance.
Junction depth at channel/drift region.
Degradation of the mobility in drift region (drain).
degradation of the mobility in drift region (source).
Temperature coefficient of RDRBB.
Wgate dependence of the saturation velocity in drift region.
Wgate dependence of the saturation velocity in drift region.
Lgate dependence of the saturation velocity in drift region.
Lgate dependence of the saturation velocity in drift region.
Lgate dependence of the mobility in drift region.
Lgate dependence of the mobility in drift region.
Substrate resistance network.
Substrate resistance network.
flag punchthrough.
flag Ps0 method for deep punchthrough.
Junction depth for deep punchthrough.
Junction doping conc; deep punchthrough.
Mobility for deep punchthrough.
dVfb for deep punchthrough.
Ps0 limit for deep punchthrough.
Offset of bulk resistance.
Bulk resistance per width.
Flatband voltage for overlapped MOSFET part.
N^+ poly capacitance.
P^+ poly capacitance.
BT overlap width.

Output Parameters

Refer to the following table for Output Parameter details:

meff

Effective multiplicity factor (m-factor).

Operating-Point Parameters

Refer to the following table for Operating-Point Parameter details:

Drift Resistance on Drain side.
Drift Resistance on Source side.
Body Contact Resistance.
Drain-Source current.
Substrate current.
Gate-Induced Drain Leakage current.
Gate-Induced Source Leakage current.
Gate-Drain current.
Gate-Source current.
Gate-Substrate current.
Transconductance.
Channel conductance.
Body effect (Back gate) transconductance.
Temperature transconductance.
Temperature.
Threshold voltage.
Saturation voltage.
Gate charge.
Drain charge.
Bulk charge.
g-g MOSFET capacitance.
g-d MOSFET capacitance.
g-s MOSFET capacitance.
b-g MOSFET capacitance.
b-s MOSFET capacitance.
b-d MOSFET capacitance.
d-g MOSFET capacitance.
d-d MOSFET capacitance.
d-s MOSFET capacitance.
b-d Diode current.
b-s Diode current.
b-d Diode conductance.
b-s Diode conductance.
b-d Diode capacitance.
b-s Diode capacitance.

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1	`l=5.0E-6 m`	Gate length (Lgate).
2	`w=5.0E-6 m`	Gate width (Wgate).
3	`ad=0.0 m^2`	Area of drain junction.
4	`as=0.0 m^2`	Area of source junction.
5	`pd=0.0 m`	Perimeter of drain junction.
6	`ps=0.0 m`	Perimeter of source junction.
7	`ngcon=1.0 -`	Number of gate contacts.
8	`xgw=0E0 m`	Distance from gate contact to channel edge.
9	`xgl=0E0 m`	Offset of gate length.
10	`m=1.0`	multiplicity factor.
11	`nf=1.0 -`	Number of gate fingers.
12	`sa=0 m`	Length of diffusion between gate and STI.
13	`sb=0 m`	Length of diffusion between gate and STI.
14	`sd=0 m`	Length of diffusion between gate and gate.
15	`pdbcp=0.0 m`	Parasitic perimeter length for body contact at drain.
16	`psbcp=0.0 m`	Parasitic perimeter length for body contact at source.
17	`lod=10.0E-6 m`	diffusion length between gate and STI edge.
18	`temp=0.0 C`	Device temperature.
19	`dtemp=0 C`	Device temperature change.
20	`trise=0 C`	Device temperature change.
21	`nbt=1.0`	Number of body contact.
22	`lbt=0.0 m`	Length of gate over body-contact well.
23	`wbtp=0.0 m`	Distance of gate protrusion over body-contact well.
24	`wbtn=0.0 m`	Distance of gate protrusion over body-contact well.
25	`abtn=0.0 m^2`	Area of N^+ poly area of body contact.
26	`abtp=0.0 m^2`	Area of P^+ poly area of body contact.
27	`nrs=1.0`	Number of squares in source .
28	`nrd=1.0`	Number of squares in drain .
29	`ldrift=1.0E-6 m`	Parameter for drift region length (drain) .
30	`ldrifts=1.0E-6 m`	Parameter for drift region length (source) .
31	`rbdb=50.0 Ohm`	Substrate resistance network.
32	`rbsb=50.0 Ohm`	Substrate resistance network.

1	`rdd (Ω)`	Drift Resistance on Drain side.
2	`rsd (Ω)`	Drift Resistance on Source side.
3	`rbulk (Ω)`	Body Contact Resistance.
4	`idse (A)`	Drain-Source current.
5	`isuba (A)`	Substrate current.
6	`igidle (A)`	Gate-Induced Drain Leakage current.
7	`igisle (A)`	Gate-Induced Source Leakage current.
8	`igde (A)`	Gate-Drain current.
9	`igse (A)`	Gate-Source current.
10	`igbe (A)`	Gate-Substrate current.
11	`ggm (S)`	Transconductance.
12	`ggds (S)`	Channel conductance.
13	`ggmbs (S)`	Body effect (Back gate) transconductance.
14	`ggmt (S)`	Temperature transconductance.
15	`deltemp (S)`	Temperature.
16	`vone (V)`	Threshold voltage.
17	`vdsate (V)`	Saturation voltage.
18	`qge (C)`	Gate charge.
19	`qde (C)`	Drain charge.
20	`qse (C)`	Bulk charge.
21	`cggbd (F)`	g-g MOSFET capacitance.
22	`cgdbd (F)`	g-d MOSFET capacitance.
23	`cgsbd (F)`	g-s MOSFET capacitance.
24	`cbgbd (F)`	b-g MOSFET capacitance.
25	`cbsbd (F)`	b-s MOSFET capacitance.
26	`cbdbd (F)`	b-d MOSFET capacitance.
27	`cdgbd (F)`	d-g MOSFET capacitance.
28	`cddbd (F)`	d-d MOSFET capacitance.
29	`cdsbd (F)`	d-s MOSFET capacitance.
30	`ibdb (A)`	b-d Diode current.
31	`ibsb (A)`	b-s Diode current.
32	`gbd (S)`	b-d Diode conductance.
33	`gbs (S)`	b-s Diode conductance.
34	`capbdb (F)`	b-d Diode capacitance.
35	`capbsb (F)`	b-s Diode capacitance.

Spectre Circuit Simulator Components and Device Models ReferenceProduct Version 23.1, June 2023

Reference

Model Equations

Basic Equations Solved in the HiSIM SOI Core Part

Drain Current

Threshold Voltage Shift

Mobility Model

Channel-Length Modulation

Narrow-Channel Effects

Temperature Dependences

Drain-side resistance

Source-side resistance

Gate resistance

Capacitance

Intrinsic Capacitance

Overlap Capacitance

Gate-Fringing Capacitance

Leakage Currents

Substrate Current

Gate Current

GIDL (Gate-Induced Drain Leakage)

Floating-Body Effect Model

History Effect Model

Self-Heating Effect Model

Source/Body and Drain/Body Diode Models

Diode Current

Between drain and body

Between source and body

Body-Tie Models

Body-Contact Capacitances

Overlap capacitance of body-tie area

Overlap capacitance of body-tie periphery

Diode current of body-tie periphery

Gate-Fringing Capacitance

1/f Noise Models

Thermal Noise Model

Induced Gate Noise Model

Coupling Noise Model

Non-Quasi-Static (NQS) Model

Formation of carrier

Delay Mechanisms

Component Statements

Instance Parameters

Model Definition

Model Parameters

Output Parameters

Operating-Point Parameters

Spectre Circuit Simulator Components and Device Models Reference
Product Version 23.1, June 2023