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The Spectre XPS Circuit Simulator

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Spectre® eXtensive Partitioning Simulator (Spectre XPS) is the next generation transistor-level circuit simulator of Cadence that provides high simulation performance and large simulation capacity. It addresses the design and verification needs of full-chip low-power designs at advanced process nodes. In addition, it incorporates a completely new circuit partitioning and multirate technology, and provides reasonable accuracy for timing and power to meet the tighter design margins.

This chapter discusses the following topics:

• Starting Spectre XPS Simulation Run
• Reviewing the Log File
• Output Files
• Multithreading Support
• Spectre XPS Options
• Post-layout simulation
• Spectre XPS SRAM Simulation
• Spectre XPS DRAM Simulation
• Spectre XPS Flash Simulation

Starting Spectre XPS Simulation Run

Most of the command-line options that are used to run Spectre XPS simulation are the same as Spectre and Spectre APS.

To start a Spectre XPS simulation run, type the following at the command line:

spectre +xps +cktpreset=dram -64 -f fsdb +spice +mt=N -outdir run1 -outname xps_out top.sp

The following table lists the command-line options and their descriptions:

You can also get more information about command options, components, analyses, controls, and other selected topics by using the spectre -h command to access the Spectre online help.

Reviewing the Log File

Spectre XPS shares the same format for the output log file as Spectre and Spectre APS. The log file provides important information about the Spectre XPS simulation run. Therefore, it is recommended to review the log file after starting the simulation.

The output log file displays the following information:

• Warning/Info/Error messages related to netlist parsing, models, and MDL (.measure)
• Staged run time and memory consumption information
• Circuit inventory details
• Output statistics for probe/save and measurement
• Simulation mode and important parameters/options used
• Detailed transient simulation information, which is controlled by the annotate parameter in the tran statement

The following sections discuss some of the important information stored in the log file and the options to control the log file in detail.

Spectre XPS cktpreset Mode Information

In the Spectre XPS log file, the following message indicates that DRAM mode with multithreading is successfully enabled:

Notice from spectre during initial setup.

XPS Enabled ( cktpreset=dram ).

……

Multithreading Enabled: 8 threads in the system with 20 available processors.

File Reading and Parsing Related Information

The Spectre XPS log file provides information on the files read in a simulation run, as shown below.

Reading file:  /projects/p100/simulation/xps_run/top.sp                                                                                                             

Reading file:  /projects/p100/simulation/xps_run/netlist.cdl                                                                                                                  

Reading file:  /projects/p100/simulation/xps_run//PDK/Spectre/v1.1/16nm_model.scs

Spectre XPS provides an option, print_section, with possible values of no and yes that enables you to print information about the library files read in the simulation, When this option is set to no, only the library file information is printed in the log file. However, when this option is set to yes, detailed sections of the library files read in the simulation are printed in the log file.

For example, if you specify print_section=yes, the log file displays the following information for the same example:

Reading file:  /projects/p100/simulation/xps_run/top.sp                                                                                                             

Reading file:  /projects/p100/simulation/xps_run/netlist.cdl                                                                                                                  

Loading section:  SS from file:  /projects/p100/simulation/xps_run//PDK/Spectre/v1.1/16nm_model.scs                                                       

Loading section:  TT_BIP_DIO from file:  /projects/p100/simulation/xps_run//PDK/Spectre/v1.1/16nm_model.scs                                                       

Loading section:  TT_RES_DISRES from file:  /projects/p100/simulation/xps_run//PDK/Spectre/v1.1/16nm_model.scs 

Output and IC/Nodeset Related Information

Spectre XPS provides useful information in the log file for the signals probed, measured, or set with IC/nodeset, especially with wildcards.

An example of the log file and the messages is given below.

Output statements:

             .probe 4

           .measure 1

               save 0

Design checks inventory:

         dyn_dcpath 2

            dyn_exi 1

Wildcard match summary:

              probe x(XI0.xTOP_0.xIO_SLICE.xio_right.*.vddpe) : 67

              probe i(vv*) depth= 1:     3

              probe i(XI0.*.x_mxmi41.mxppua) : 0

              probe v(*) depth= 5:       3938

                ic *.sao                64

                 ic *.ncored             32768

                 ic *.cored              32768

                 ic *.bl                 0

                 ic *.nbl                0

Output and IC/nodeset summary:

                 probe  4008

                 measure        1

                 ic     65600

Options to Control Warning/Error Messages in Spectre XPS

Messages in the Spectre XPS simulator, like Spectre and Spectre APS, are categorized based on three severity levels: INFO, WARNING, and ERROR. In addition, each message includes a unique alphanumeric message ID enclosed in parentheses.

You can use the following global options to customize the number of messages and their severity based on ID:

Examples

.option maxwarns=1

.option maxwarnstologfile=10

You can use the following options to control the number of messages or change the severity of a message based on ID:

.option warning_id=[SFE-3013] warning_limit=10

.option warning_id=[SPECTRE-17100] warning_change_severity=error    

Transient Simulation Information

Use the parameter annotate in the tran statement to display the status of the transient simulation in the log file. It is recommended to set the value of the annotate parameter to estimated to display detailed information in the log file. For example:

.tran 1n 1u annotate=estimated

The following is an example of the transient simulation information that is displayed in the log file:

transient0: time = 10.15 ns    (10.6 ), step = 735.2 fs     (764 u)

          cpu = 223.4 s, elapsed = 83.7 s, steps = 0, mem = 11770.8 MB

          estimated completion time:  00:11:49

transient0: time = 10.23 ns    (10.6 ), step = 3.639 ps    (3.78 m)

          cpu = 348.9 s, elapsed = 106.4 s, steps = 0, mem = 11771.8 MB

          estimated completion time:  00:14:54

transient0: time = 10.45 ns    (10.9 ), step = 69 ps       (71.7 m)

          cpu = 403.9 s, elapsed = 117.2 s, steps = 0, mem = 11773.2 MB

          estimated completion time:  00:16:01

    transient0: time = 11.5 ns       (12 ), step = 413.6 ps     (430 m)

          cpu = 416.4 s, elapsed = 119.7 s, steps = 0, mem = 11774.0 MB

The above log file contains the following information related to transient simulation:

• The current CPU time/elapsed time for transient simulation
• The estimated time required to complete the rest of transient simulation.
• The time step of Spectre XPS. This information can be helpful to debug performance issues. Spectre XPS takes bigger time steps if there is no activity in the circuit.

Output Files

After a simulation completes, Spectre XPS writes the following output files based on the design setup:

• Log file: Defined using the +log/=log/-log command-line options
• Measure results: *.measure and *.mt0 files
• Waveform files and format: Defined using the -format (or -f) command-line option
• Operating point files: *.ic0 and *.op0 files
• Circuit check results

Using the Command-Line Option -outdir

You can use the -outdir command-line option to specify the output directory for the simulation files.

The following example demonstrates the location and names of the output files.

 spectre -64 +xps +cktpreset=sram +speed=2 +spice -outdir xps_x4_out top.sp

The following are the file names and their locations:

xps_x4_out/

|-- top.log

|-- top.mt0

|-- top.measure

|-- top.ic0

|-- top.op0

|-- top.raw

    |-- logFile

    |-- transient1.tran.fsdb

    |-- transient1.meas_tran

    |-- top.sqldb

    |-- mmcheck2html.xsl

    |-- traverse.css

    |-- sorttable.js

    |-- top.dynamic.xml

    `-- top.dynamic.rpt

Using the Command-Line Option -outname

You can use the command-line option -outname to change the names of output files and their locations. When you use this option, the waveform files are moved from the raw directory to the specified output directory. The following is the syntax to specify the -outname command-line option:

-outname <out_dir_name>/<new_file_name>

Here, out_dir_name is the name of the output directory and new_file_name is the name of the new file. You can specify either of the two or both the options in a single statement.

Following are some of the examples of using the -outname command-line option.

Example1

 spectre -64 +xps +cktpreset=sram +speed=x4 +spice -outname xps_x4_out/ top.sp

In the above example, the value, xps_sp2_out/, of the command-line option -outname contains a slash (/), which means it is a directory name. Specifying this option will cause the waveform files to move outside the raw directory.

The file names and their locations are changed as follows:

xps_x4_outname/

|-- top.fsdb

|-- top.log

|-- top.measure

|-- top.mt0

|-- top.ic0

|-- top.op0

|-- top.raw

    |-- logFile

    |-- transient1.meas_tran

    |-- mmcheck2html.xsl

    |-- traverse.css

    |-- sorttable.js

    |-- top.sqldb

    |-- top.dynamic.xml

    `-- top.dynamic.rpt

Example2

 spectre -64 +xps +cktpreset=sram +speed=x4 +spice -outname out_newname top.sp

In the above example, only a name is specified with the -outname command-line option. This will cause the file name of the output files to change to the new one and the waveform files to move outside the raw directory. The file names and their locations are changed as follows:

./

|-- new_outname.fsdb

|-- new_outname.log

|-- new_outname.measure

|-- new_outname.mt0

|-- new_outname.ic0

|-- new_outname.op0

|-- top.raw

    |-- logFile

    |-- transient1.meas_tran

    |-- mmcheck2html.xsl

    |-- traverse.css

    |-- sorttable.js

    |-- top.sqldb

    |-- top.dynamic.xml

 `-- top.dynamic.rpt

Example 3:

 spectre -64 +xps +cktpreset=sram +speed=2 +spice -outname xps_x4_out/new_outname top.sp

In the above example, both output directory and output file name are specified with the -outname command-line option. The file names and their locations are changed as follows:

xps_x4_out/ 

|-- new_outname.fsdb

|-- new_outname.log

|-- new_outname.measure

|-- new_outname.mt0

|-- new_outname.ic0

|-- new_outname.op0

|-- top.raw

    |-- logFile

    |-- transient1.meas_tran

    |-- mmcheck2html.xsl

    |-- traverse.css

    |-- sorttable.js

    |-- top.sqldb

    |-- top.dynamic.xml

    `-- top.dynamic.rpt

Multithreading Support

The Spectre XPS technology supports multithreading on multicore computer platforms. The default behavior is to use a single thread for Spectre XPS. You can enable the multithreading feature by using the +mt command-line option of the Spectre binary, as shown below.

 spectre +xps +mt...

To manually specify the number of threads to be used, use the following command:

 spectre +xps +mt=8 ...

When multithreading is enabled, the Spectre XPS log file displays the following information:

Multithreading Enabled: 8 threads in the system with 20 available processors.

To get maximum performance gain from multithreading, it is recommended that the CPU cores for Spectre XPS are within one socket. This is because the CPU cores in one socket have less communication overhead. Spectre XPS automatically selects the CPU cores for optimized performance. You just need to ensure that the number of CPU cores in one socket is greater than the number of specified threads.

To get the server information, use the following command:

  spectre +query=sysinfo

The following hardware and OS platform information is generated. The server in this example has two sockets with 14 CPU cores in both.

OS      : Linux 2.6.18-194.el5 x86_64

Linux   : Red Hat Enterprise Linux Client release 5.5 (Tikanga)

Memory  : available 145.8051 GB         physical 405.6638 GB

Swap    : available 94.4486 GB  physical 137.4389 GB

CPU type: Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz

Hyperthreading is disabled

Socket  Proc    Core

 0       0       0      2600.1

         2       1      2600.1

         4       2      2600.1

         6       3      2600.1

         8       4      2600.1

        10       5      2600.1

        12       6      2600.1

        14       8      2600.1

        16       9      2600.1

        18      10      2600.1

        20      11      2600.1

        22      12      2600.1

        24      13      2600.1

        26      14      2600.1

 1       1       0      2600.1

         3       1      2600.1

         5       2      2600.1

         7       3      2600.1

         9       4      2600.1

        11       5      2600.1

        13       6      2600.1

        15       8      2600.1

        17       9      2600.1

        19      10      2600.1

        21      11      2600.1

        23      12      2600.1

        25      13      2600.1

        27      14      2600.1

To benefit from multithreading technology, a circuit should have at least 500 nodes. When a circuit is too small, multithreading is turned off automatically.

Spectre XPS Options

Spectre XPS can be configured to obtain optimized simulation results, performance, accuracy, and waveform file size. The general naming convention for the XPS configuration options is sim_opt_optName, which can be specified with:

Spectre format:

opt1 options sim_opt_optName=optValue {subckt=[subcktName]} 

opt2 options sim_opt_optName=optValue {inst=[instanceName]} 

SPICE format:

.options sim_opt_optName=optValue {subckt=[subcktName]}

.options sim_opt_optName=optValue {inst=[instanceName]}

Options Related to Circuit Partitioning

Spectre XPS supports the following two fundamental technologies for circuit partitions:

• Arbitrary partition can break the channel connections of transistors. Therefore, you should not tune this partition.
• To maintain good accuracy, a dynamic group is created for the partitions and their nodes with current conducting path and strong coupling. When the conditions are changed, the group may be destroyed to minimize the impact on performance.

Spectre XPS provides good usability with less user interfere on circuit partitions. However, you can use the sim_opt_one_part and sim_opt_analog options to fine-tune it for better accuracy/performance trade-off.

• sim_opt_one_part=2 subckt=[subckt_name*]
  Specifies the name of the subcircuit to be partitioned. It is recommended to set this option locally for sensitive blocks. Wildcard can be used with the parameter subckt. Possible values are:
  • 0: Uses the arbitrary partition algorithm to perform circuit partitioning. This is the default value.
  • 1: Treats the subcircuit as one partition. This is a conservative setting and is recommended for subcircuits with less than 100 MOSFETs.
  • 2: Performs channel connect partitioning inside the subcircuit. The subcircuit may contain several hundreds of MOSFETs.
• sim_opt_analog=6 | 7 subckt=[subckt_name*]
  The sim_opt_analog option with possible values of 6 and 7 can be set on analog blocks to obtain high accuracy. The subcircuits with this option are forced to create a dynamic group during the whole transient.
  • sim_opt_analog=6 can be set on bias, charge pumps, regular blocks, or other sensitive analog blocks (500-10k devices) to obtain good accuracy. For example:
    

    .options sim_opt_analog=6 subckt=[myCP myReg]

    .options sim_opt_analog=6 inst=[xiCP xiReg]

  • sim_opt_analog=7 is more conservative than value 6 and improves Spectre XPS accuracy further. However, it is targeted at smaller blocks to minimize the impact on performance. For example:
    

    .options sim_opt_analog=7 subckt=[myCP myReg]

    .options sim_opt_analog=7 inst=[xiCP xiReg]

• sim_opt_circuit_detect
  The sim_opt_circuit_detect=1 option enables Spectre XPS to detect sense amplifier and place it in one partition to obtain high accuracy. The default value is 0. For example:

  .options sim_opt_circuit_detect=1

• sim_opt_analog_rc_part_merge
  By default, Spectre XPS places the RC network from other devices in a separate partition. You can use the sim_opt_analog_rc_part_merge=1 option to enable Spectre XPS to place RC and other devices in the same partition to obtain high accuracy. The default value is 0.

  .options sim_opt_analog_rc_part_merge=1

Options Related to RC

For postlayout simulation, RC reduction is one of the fundamental technology. Spectre XPS optimizes RC reduction based on the circuit type. It provides two high-level options, sim_opt_rcr_sram and sim_opt_rcr_dram, for SRAM and DRAM designs.

• sim_opt_rcr_sram="NULL"
  Flag to set a group of RC reduction options for SRAM simulation. The greater the value the more aggressive is RC reduction. You can set the following values with the sim_opt_rcr_sram option:
  • NULL: The RC Reduction algorithm is enabled only for a SRAM application by specifying +cktpreset=sram at the command line. For the other applications, the value of this option is NULL, which means RC reduction is not enabled for SRAM.
  • 1: Performs conservative RC reduction for SRAM simulation at advanced technology nodes (below 10nm) and with smaller design margin, especially for designs with RC on power net. This value is set while using speed=1 for SRAM simulation
  • 2: Performs moderate RC reduction for SRAM general timing simulation. This value is set while using speed=2 for SRAM simulation.
  • 3: Performs liberal RC reduction for SRAM simulation with loose timing accuracy requirement, like function verification. This value is set while using speed=5 for SRAM simulation.
• sim_opt_rcr_dram="NULL"
  Flag to set a group of RC reduction options for DRAM simulation. The greater the value the more aggressive is RC reduction. You can set the following values with the sim_opt_rcr_sram option:
  • NULL: The RC Reduction algorithm is enabled only for a DRAM application by specifying +cktpreset=dram at the command line. For the other applications, the value of this option is NULL, which means RC reduction is not enabled for DRAM.
  • 1: Performs conservative RC reduction for DRAM simulation for better timing accuracy. This value is set while using speed=1 for DRAM simulation.
  • 2: Performs moderate RC reduction for DRAM general timing simulation. This value is set while using speed=2 for DRAM simulation.
  • 3: Performs liberal RC reduction for DRAM simulation with loose timing accuracy requirement, like function verification. This value is set while using speed=5 for DRAM simulation.

The following are some other RC-related options to control SRAM and DRAM simulation runs:

Options Related to Models

For MOSFETs in postlayout simulation, a model is with Layout Dependent Effect (LDE). As a result, its instance parameters or model parameters may have unique values for each MOSFET instance. Spectre XPS uses two levels of table model to enable sharing between MOSFET instances with good accuracy:

• Reference table model – A fully dense model that is accurate. Spectre XPS models all the required model effects in it.
• Ratio table – While building the model with mini-SPICE solver, Spectre XPS checks its coefficient with the reference table. If the accuracy meets the pre-defined criteria, this MOSFET instance is referred to the reference table, and a ratio table is built to model the mismatch. Ratio table is a sparse table and its size is much smaller than the reference table.

You can use the sim_opt_model option to control the accuracy of the table. This option accepts the following four possible values. The greater the value the more conservative is the table model.

• • 1: This is the default value. It uses the default table model for the generation of reference table and ratio table.
  • 2: Uses a tighter criteria to perform sharing using the ratio table by adding more checks on current and charge.
  • 3: Disables the ratio table. You may set it for pre-layout cases because there is no Layout Dependent Effect. For postlayout cases it increases the memory.
  • 4: Uses the equation model instead of the table model. It affects both performance and memory consumption. Set this option locally and use it for debugging purposes only.

The following are some other model-related options that you can use:

Option Related to SRAM Bitcell

To speed up SRAM simulation, especially for function verification, you can use the detect_memcell option to detect the bitcell for better performance. The detect_memcell option accepts the following two values:

• 0: Disables bitcell detection. This is the default in XPS, except SRAM function verification mode specified using +xps +cktpreset=sram +speed=x6.
• 1: Enables bitcell detection. It speeds up SRAM simulation; however, it may cause some timing accuracy loss. Therefore, it is recommended to use this option for SRAM function verification.

Options to Control Error Tolerance

You can use the following options to control error tolerance:

Option to Report DC Non-Convergence

You can use the sim_opt_dump_dc_report option, with possible values of 0 (default) and 1, to print the DC non-convergence information. sim_opt_dump_dc_report=1 prints detailed DC non-convergence information to a report file, <netlist>.dcrpt.

The criteria to write DC non-convergence is based on the sum of node currents. Based on Kirchhoff's Current Law (KCL), this current should be zero. If Spectre XPS DC does not converge fully for these nodes, their sum current is not zero. Spectre XPS reports the nodes with current larger than 0.1uA with the number of events (like time steps) in DC.

The following is an example of the <netlist>.dcrpt report with the lines sorted by node current value.

Options to Control Waveform and Output

You can use the following global options to control the waveform and output:

Post-layout simulation

Postlayout simulation with parasitic effects is essential for verification of memory designs like SRAM and DRAM, especially for timing accuracy. Like most of the postlayout simulations, two major effects need to be considered:

• The parasitic elements, especially resistors and capacitors. Effective RC Reduction algorithm of Spectre XPS, empowered by the port merge technology, improves the run time significantly while maintaining good accuracy.
• The Layout Dependent Effect (LDE) for transistors introduces challenges for the table model in FastSPICE technology since each transistor may have unique model parameters.

Spectre XPS effectively addresses the challenges of advanced process nodes. Postlayout simulation is one of them. For more information, refer to Chapter 17, “Postlayout Simulation,”.

Spectre XPS SRAM Simulation

For SRAM simulation, Spectre XPS supports a high performance/capacity FastSPICE mode (+xps) and a high accuracy SPICE mode (+xps=s). Each of these modes can be further optimized for timing simulation (+cktpreset=sram) and power simulation (+cktpreset=sram_pwr). In addition, there is a speed option (+speed) that can be used to trade-off accuracy and performance; speed=1 is the most accurate while speed=5 is the fastest.

The following table summarizes all available settings where indicates the availability of a particular setting:

The Spectre XPS use model has been updated for SRAM timing simulation. The updated use model combines the high performance/capacity and high accuracy modes. You can now use the +speed=x# option to control accuracy/performance. Legacy modes are also supported.

For example, to run a high-precision SRAM timing simulation, you can use the following command:

 spectre +xps +cktpreset=sram +speed=x2...

To relax the accuracy criteria and obtain high performance, use the following command:

spectre +xps +cktpreset=sram +speed=x4...

The following table summarizes all the available speeds and their corresponding legacy modes:

+xps=s +speed=3

When using a SPICE runset, add the +spice option to ensure that the netlist convention and device models are consistently interpreted as traditional SPICE, instead of Spectre.

Since most Spectre XPS applications are large postlayout designs, use the -64 command-line option to enable the 64-bit version of Spectre.

The high accuracy SPICE mode (+speed=x2) supports multithreading computation on multi-core platforms. Multithreading is enabled by default in Spectre XPS SPICE mode and the default number of threads used is 8. The maximum number of threads allowed is 64. You can turn off multithreading by using the following command:

 spectre +xps +cktpreset=sram +speed=x2 -mt ....

 spectre +xps=s +mt=4....

XPS SRAM Timing Simulation

When simulation speed is the primary concern, the default (speed=x6) FastSPICE mode (+xps) can be invoked in an SRAM simulation, as shown below.

 spectre +xps +cktpreset=sram input.scs …

The accuracy of the FastSPICE mode can be increased by using the speed option, as shown below.

 spectre +xps +speed=x5|x4 +cktpreset=sram input.scs … //(new use model)

 spectre +xps +speed=2|1 +cktpreset=sram input.scs … //(legacy use model)

To further increase the timing simulation accuracy, particularly for critical cut SRAM simulation, or small-medium sized full macro SRAM simulation, the SPICE mode (speed=x2) can be used, as follows:

 spectre +xps +cktpreset=sram +speed=x2 input.scs … //(new use model)

 spectre +xps=s +cktpreset=sram input.scs … //(legacy use model)

XPS SRAM Power Simulation

The SRAM timing simulation settings can be used in both timing and power simulation; however, a power simulation mode is available that further optimizes power and current accuracy and simulation performance.

To invoke power optimization in the FastSPICE simulation mode, use the following command:

 spectre +xps +cktpreset=sram_pwr +speed=2 input.scs …

This mode targets better performance with less physical memory consumption, and still maintains good accuracy for average current.

A more accurate mode is often used in power and current simulation if the peak current is also critical. The recommended setting is the same as accurate mode for timing simulation as follows:

 spectre +xps +cktpreset=sram +speed=x2 input.scs … //(only in the new use model)

XPS SRAM Postlayout Simulation

Spectre XPS is optimized to handle large postlayout SRAM designs. It directly simulates a flat DSPF/DPF/SPEF postlayout netlist by including the file that is commonly used in SRAM designs, as shown below.

Spectre format:

include "file.spf" 

SPICE format:

.include "file.spf" (SPICE syntax)

Due to the tight timing requirement for SRAM memory, backannotation postlayout simulation flow is not supported in SRAM.

XPS SRAM Leakage Current Simulation

Leakage current and power are measured in various standby and power-down modes. Traditionally, these simulations require a careful selection of measurement time points, where the circuit signals have to settle down to a steady state. Spectre XPS accelerates the leakage current and power simulation by deploying a new methodology that requires you to only provide the time point where all input signals are at their steady state. For SRAM designs, the algorithm for leakage simulation has been enhanced, especially for power-off modes, including retention, array shutdown, and total shutdown.

To enable the leakage current and power simulation in Spectre XPS in multiple power mode, use the following options:

Spectre format:

opt1 options leaki_times=[4u 10u] //(defines input-steady state time points in                                      multiple power mode)

save v1:p vdd:p //(current probes on power supplies)

SPICE format:

.options leaki_times=[4u 10u] //(defines input-steady state time points in                                 multiple power mode)

.probe tran i(v1) i(vdd) //(current probes on power supplies)

Following is an example of the command-line option to run the leakage simulation using SPICE runset:

 spectre -64 +xps +cktpreset=sram_pwr +spice input.sp... 

As a result of the above settings, Spectre XPS performs a transient simulation till 4us. It also performs a leakage analysis with the circuit biased at the 4us condition to calculate the leakage currents i(v1) and i(vdd). Spectre XPS then continues transient simulation till 10us and performs another leakage analysis with the circuit biased at the 10us condition. The result of the leakage current simulation is reported in a file with the extension leaki, as shown below.

i(v1): t= 4.0000e-06   val= -2.1293e-10

i(vdd): t= 4.0000e-06   val= -3.1166e-09

i(v1): t= 1.0000e-05   val= -4.3421e-10

i(vdd): t= 1.0000e-05   val= -6.9654e-09

To enable the leakage current and power simulation in single power mode, use the following options:

Spectre format:

opt1 options sim_opt_auto_leaki=1 //(defines input-steady state time points in                                      single power mode)

save v1:p vdd:p //(current probes on power supplies)

SPICE format:

.options sim_opt_auto_leaki=1 //(defines input-steady state time points in                                 single power mode)

.probe tran i(v1) i(vdd) //(current probes on power supplies)

Handling SRAM Designs at Advanced Technology Nodes

With shrinking process nodes, such as 7nm, there are several challenges for FastSPICE simulators to meet the tighter accuracy requirements of SRAM designs. The XPS SRAM speed=1 setting has been enhanced to handle the following challenges from the advanced process nodes, and provides the required timing accuracy:

• The IR drop caused by resistors and capacitors on a power net or a virtual power net (VPN) can significantly impact the timing accuracy. IR drop of several milivolts may result in 10+ps timing discrepancy of SRAM designs. You can use the XPS SRAM speed=1 setting to simulate the IR drop accurately to meet the final timing accuracy. To reduce the performance overhead, it is recommended to use RC reduction while extracting the RCs on power net or VPN nodes.
• The voltage of power supply for advance process nodes may decrease under 500mV. You can use the XPS SRAM speed=1 setting to provide good accuracy for most of the situations. For best accuracy results, set the option sim_opt_step_ratio option to a value between 0.5 to 1 (the smaller the value, the more conservative is the result).
• Due to the smaller size, the coupling effect is even stronger. This means that the number of coupling capacitors is greatly increased for the advanced process nodes. For better accuracy for coupling effect, set the option sim_opt_fcapl to 1e-18 (the default value is 1e-17 for XPS SRAM speed=1 setting).
• For RC on signal net, such as bit line, word line, and sense amplifier, you can use the XPS SRAM speed=1 setting for better timing and tighter accuracy requirements.

Spectre XPS DRAM Simulation

With advancing process technology nodes and high capacity of DRAM chips (including PCRAM), designers are facing increasing challenges to simulate and validate large full-chip DRAM designs with the extracted parasitic elements. The simulation accuracy requirement is tighter due to shrinking design margin.

Spectre XPS provides the following advantages for DRAM applications:

• Competitive performance empowered by multithreading support — The fundamental FastSPICE technology of Spectre XPS, including arbitrary partition, dynamic group, table model, and effective multirate, can work well for DRAM postlayout simulation.
• Accurate results for timing, voltage, and current signals — As the new generation FastSPICE simulator, Spectre XPS has been optimized to meet the accuracy challenges introduced by advanced process nodes and lower voltage supplies. Both areas that are critical for accuracy are handled effectively in Spectre XPS: RC reduction empowered by port merge for parasitic RC and the core solver with partition enabled.
• Simple and consistent use model — Spectre XPS provides a consistent use model for DRAM applications. A more conservative mode, +speed=1, is provided for better accuracy with acceptable performance degradation; normally less than 2X.
• Better handling of large DRAM designs — Spectre XPS reduces memory consumption, and therefore, it is suitable for big DRAM designs.

Spectre XPS DRAM Postlayout Simulation

Postlayout simulation with parasitic effects is essential for DRAM verification, especially for timing accuracy. Like most of the postlayout simulation scenarios, the following two major effects should be considered:

• Parasitic elements, especially resistors and capacitors. Effective RC Reduction algorithm of Spectre XPS, empowered by the port merge technology, greatly improves the run time while maintaining good accuracy.
• The Layout Dependent Effect (LDE) for transistors introduces the challenge for the table model of FastSPICE technology since each transistor may have unique model parameters.

Spectre XPS is optimized to address the challenges introduced by the advanced process nodes. Postlayout simulation is one of them.

For more information on the Postlayout simulation flow, refer to Chapter 17, “Postlayout Simulation,”.

Starting an XPS DRAM Simulation Run

The Spectre XPS DRAM simulation can be run using the following command:

spectre -64 +xps +cktpreset=dram +speed=2 +mt=8 top.sp....

spectre -64 +xps +cktpreset=pcram +mt=8 top.sp...

Alternatively, you can specify the +cktpreset and +speed options in the netlist, as shown below.

.options cktpreset=dram#1|2|5

.options cktpreset=pcram

When the simulation is run, the following message in the Spectre XPS log file indicates that DRAM mode with multithreading capability is successfully enabled:

Notice from spectre during initial setup.

XPS Enabled ( cktpreset=dram ).

……

Multithreading Enabled: 8 threads in the system with 20 available processors.

The Spectre XPS DRAM mode supports multithreading computation on multicore platforms. Multithreading is enabled by using the +mt option at the command line.

Overall Accuracy/Performance Tuning Strategy in Spectre XPS

Spectre XPS provides an application-based solution by using the +cktpreset command-line option. For example, to run a DRAM simulation, specify the +cktpreset=dram command-line option. The accuracy and performance can be optimized using the +speed option, which includes error tolerance definition for the simulator. For tuning error tolerance, it is important to first understand the accuracy requirement, and then choose the different values for the +speed option. Spectre XPS provides a complete set of simulation modes or high-level +speed settings that you specify at the command line to meet different requirements. These models are listed below in the order of increased accuracy.

You can use the following high-level options for different simulation modes:

High Accuracy Mode

One of the targets of Spectre XPS, including the DRAM application, is to simplify the use model by reducing the tuning effort on a case-by-case basis. However, to maintain the flexibility of better accuracy/performance trade-off, you can use any of the following methods for a DRAM application:

• Specify +speed=1 at the Spectre command line, as shown below.
  

   spectre -64 +xps +cktpreset=dram +speed=1 +spice …

• Specify the cktpreset and speed options in the netlist file, as shown below.
  Spectre format:

  Opt options cktpreset=dram#1

  SPICE format:

  .options cktpreset=dram#1

The above methods improve Spectre XPS accuracy by providing:

• Tighter error tolerance, especially for the lower voltage of power supply.
• Tighter time step control.
• Reduced threshold for coupling capacitor by splitting it from 1e-17 F to 1e-18 F. This threshold is defined using the sim_opt_fcapl option.
• Better accuracy for table model; however, it may increase memory consumption.

Function Verification Mode

The default speed option is +speed=2 for Spectre XPS DRAM application. It can be applied to general timing and power simulation. For function verification, the timing accuracy requirement may be relaxed using a reasonable range; however, you still need to keep the correct function. Spectre XPS provides the following two methods to define the function verification mode for DRAM simulation:

• Specify +speed=5 at the Spectre command line, as shown below.
  

   spectre -64 +xps +cktpreset=dram +speed=5 +spice …

• Specify the cktpreset and speed options in the netlist file, as shown below.
  Spectre format:

  Opt options cktpreset=dram#5

  SPICE format:

  .options cktpreset=dram#5

Accuracy for Analog Block in DRAM Simulation

In DRAM applications, most of the elements are from the DRAM bank or the peripheral logic blocks. However, there may still be some sensitive analog blocks inside it. You can set the sim_opt_one_part and sim_opt_analog options locally on such analog blocks to obtain high accuracy. It is recommended to set these options on small blocks to minimize the performance impact.

See Options Related to Circuit Partitioning for information on these options.

Examples of local options for analog blocks in DRAM simulation

• .option sim_opt_analog=7 subckt=[comparator SA]
  Use sim_opt_analog=7 on comparator and sense amplifier for better accuracy, if required.
• .option sim_opt_analog=7 subckt=[bandgap chg_pump]
  Use sim_opt_analog=7 on bandgap and charge pump for better accuracy.
• .option sim_opt_one_part=1 subckt=[vco delay_cell]
  Use sim_opt_one_part=1 on oscillator or delay block for SPICE-like timing.
• .option sim_opt_circuit_detection=1
  There is no need to set the local scope.
• .option sim_opt_analog_rc_part_merge=1
  There is no need to set the local scope.

Spectre XPS Flash Simulation

Spectre XPS has been designed to significantly reduce the simulation time of flash memory designs. In addition, the target is to complete a fully extracted postlayout simulation on full chip design within acceptable accuracy degradation.

For flash simulation, Spectre XPS supports a high performance/capacity FastSPICE mode (+xps), and an accurate SPICE mode for small blocks in a flash design. The +speed command-line option that is used in SRAM application is not supported for flash designs.

Adjusting Speed and Accuracy of Spectre XPS Flash Memory Simulation

You can use two global options, sim_opt_acc and sim_opt_analog, to adjust the speed and accuracy settings of a Spectre XPS flash memory simulation.

The sim_opt_acc option with possible values of 2, 4, and 8 can be used to get better speed and accuracy.

• sim_opt_acc=2 can be set on larger logic blocks (>10k devices) to get better performance.
• sim_opt_acc=4 can be set to get accurate power simulation or postlayout backannotation run.
• sim_opt_acc=8 can be set on smaller blocks (<500 devices) to get better timing accuracy.

The sim_opt_analog option with possible values of 6 and 7 can be set on pump/regulator blocks to obtain high accuracy.

• sim_opt_analog=6 can be set on charge pumps, regular blocks, or other sensitive analog blocks (500-10k devices) to obtain good accuracy. For example:
  

  .options sim_opt_analog=6 subckt=[myCP myReg]

  .options sim_opt_analog=6 inst=[xiCP xiReg]

• sim_opt_analog=7 is more conservative than value 6 and improves Spectre XPS accuracy further. However, it is targeted at smaller blocks to minimize the impact on performance. For example:
  

  .options sim_opt_analog=7 subckt=[myCP myReg]

  .options sim_opt_analog=7 inst=[xiCP xiReg]

Starting a Spectre XPS Flash Memory Simulation

You can invoke Spectre XPS flash simulation in FastSPICE mode, as shown below.

 spectre +xps +cktpreset=flash input.scs …

For small block-level designs that require high accuracy tolerance, the default SPICE mode can be used.

 spectre +xps=s +cktpreset=flash input.scs …

When using a SPICE runset, add the +spice option to ensure that netlist convention and device models are interpreted in a consistent manner as traditional SPICE, instead of Spectre. For large mixed-signal applications, it is recommended to use the 64-bit version of the tool with the -64 command-line option.

A configuration file may be used (+config file.cfg) to obtain optimized simulation results. All control options can be specified either in netlist file input.scs or the configuration file.

Flash Memory Postlayout Simulation

Spectre XPS is optimized to handle large postlayout flash memory designs. It annotates the DSPF/DPF/SPEF file back to the pre-layout netlist through parasitic backannotation options, as shown below.

Spectre format:

Opt1 options spf="scope filename" 

Opt2 options dpf="scope filename"

Opt3 options spef="scope filename"

SPICE format:

.options spf="scope filename" 

.options dpf="scope filename" 

.options spef="scope filename" 

Here, scope can be a subcircuit or an instance.

The Spectre XPS parasitic backannotation flow shares the same methodology and controls as Spectre APS. For more information on the parasitic backannotation related control options, such as spfscale, spfxtorprefix, and spfaliasterm, refer to Chapter 17, “Postlayout Simulation,”.