Product Documentation
Virtuoso MultiTech Framework User Guide
Product Version IC23.1, November 2023

Thermal Shrink Factor

The Virtuoso RF Solution lets you encapsulate dies of different semiconductor materials into a single package. Within a package, flip chip die-to-package assembly is done by soldering the IO pads in the die to the package substrate by heating both the die and the package. The bump flux in the flip chip die melts and fuses with the package substrate. Such connections might be impacted by the differences in the coefficients of thermal expansion (CTEs) of the semiconductor materials that are used in the package. Consider the following example:

To overcome such connectivity issues due to differences in CTEs, Virtuoso lets you set the thermal shrink factor for such dies. This option adjusts the initial positions of IO pads such that connectivity is not broken when the dies are heated. It is recommended that you apply the thermal shrink factor before defining connectivity, as shown in the following example:

Thermal shrink factor is defined as a parameter of the TILP instance. X Thermal Shrink Factor and Y Thermal Shrink Factor are percentage values for expansion or contraction along the x-axis and y-axis, respectively.

Thermal shrink is applied on IO pads as a factor of the distance of IO pads from center of the die.

dx = X * x_thermalShrink
dy = Y * y_thermalShrink

Closer the IO pad is to center of the die, less is the effect of thermal shrink factor. Farther the IO pad is from the center of the die, greater is the effect of thermal shrink factor.

If the IO pad is present at the exact center of the die, there is no effect of thermal shrink factor on that specific IO pad.

Impact of Applying Thermal Shrink Factor

Related Topics

Thermal Shrink Factor

Key Edit-in-Concert Views

Checking and Fixing IO Pad Locations

Edit Instance Properties Form (Die/Package TILP Parameters)


Return to top
 ⠀
X