I/O Pin Generation
You specify the pins to be generated on the I/O Pins tab of the Generate Layout form.
For each pin listed, the form shows the parameters that will be used to generate its equivalent in the layout. You can remove or change the specification of any of the listed pins, or add new pins to be generated.
When generating pins, Layout XL uses the same naming convention as the Virtuoso Schematic Editor, allowing you to assign different names to terminals and nets. Where terminal and net names are different in the schematic, Layout XL creates pins with the same terminal name as in the layout, even though the net name associated with the pin might be different.
By default, this section lists all the top-level pins detected in the schematic design, including schematic pins that are connected to I/O pads (cells of type pad, padSpacer, or padAreaIO). To generate only pads but no pins, turn on the Except Pad Pins option on the Generate tab on the Generate Layout form (or on the Update tab if you are using the Update Components and Nets form).
Power and ground pins defined at a lower level of the design hierarchy are not listed on the I/O Pins tab but are nevertheless generated in the layout view. The system issues an information message to tell you what has happened.
The system generates a pin for a stub net (a non-global netSet automatically created by the schematic extractor) only if the stub net is connected to an instance terminal. If it is unconnected, no pin is generated.
Layout XL also correctly propagates connectivity to nets that are connected via patchcords.
Specifying Default Values for All Pins During Layout Generation
Specifying Values for Selected Pins During Layout Generation
Adding a New Pin During Layout Generation
Creating Pin Labels During Layout Generation
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