Product Documentation
Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide
Product Version IC23.1, November 2023

Generate Layout Form

Use the Generate Layout form to generate layout representations of schematic design components.

The form is split into four tabs.

Tab Description

Generate

Lets you select which design objects are generated in the layout view.

I/O Pins

Lets you specify default attribute values for pins, select and update the attribute values of pins generated in the layout, and specify the type of label generated when you create a pin.

PR Boundary

Lets you specify the shape of the place and route boundary, how system calculates the shape and size of a rectangular boundary, and how the area boundary of a virtual hierarchy is estimated.

Floorplan

Lets you choose the floorplanning objects to be preserved in the generated layout.

Generate

The following table describes the fields available on the Generate tab of the Generate Layout form.

Field Description

Generate

This section lets you choose which design objects are generated in the layout view.

Instances

Lets you generate all the instances in the schematic that do not have one of the ignore properties attached to them.

Environment variable: initCreateInstances

  • Chain: Abuts MOS transistors automatically into chains during layout generation.
    Environment variable: initDoStacking
  • Fold: Divides devices into folds automatically to prevent the gate width from exceeding a specified size.
    If the disableFolding environment variable is set and the folding threshold for the component type is set to 0, folding is disabled. You can change the folding threshold using CPH Component Types mode or LAM.
    Environment variables: initDoFolding, disableFolding
  • Chain Folds: Automatically chains the individual folds of a transistor.
    For the Chain Folds option to be available, only the Fold check box must be selected. If you select the Chain check box as well, Chain Folds is deactivated.
    Environment variable: chainFolds

I/O Pins

Generates all the pins listed on the I/O Pins tab. The generated pins are automatically snapped to the placement grid.

Environment variable: initCreatePins

  • Except Global Pins: Stops Layout XL generating layout pins for the global nets in the schematic.
    Environment variable: initGlobalNetPins
  • Except Pad Pins: Stops Layout XL from generating layout pins for schematic pins that are connected to I/O pads (cells of type pad, padSpacer, padAreaIO, or coverBump).
    When unchecked, the software generates pads, coverBumps, and pins.
    Environment variable: initCreatePadPins

PR Boundary

Lets you generate a PR boundary based on the settings on the PR Boundary tab. All placements and estimations are based on the generated PR boundary.

Environment variable: initCreateBoundary

  • Snap Boundary: Generates a rectangular snap boundary that encloses the generated PR boundary. You can generate a snap boundary only if PR Boundary is selected.
    Environment variable: initCreateSnapBoundary

Position

This section lets you specify the positions of instances.

Minimum Separation

Positions the instances in the layout at a minimum separation based on the value you specify. You can also control this option by using the lxPositionMinSep environment variable.

The minimum separation value is honored even if the lxGenerateInBoundary environment variable is set. Therefore, with lxGenerateInBoundary set, if the minimum separation value you specify is large, the instances may still get positioned outside of the design boundary.

Environment variables: lxPositionMinSep, lxGenerateInBoundary, lxGenerateInBoundary.

In Boundary

Generates layout representations within the design boundary when the Generate All From Source command is run.

Environment variable: lxGenerateInBoundary

Device Correspondence - Preserve User-Defined Bindings

Preserves user-defined bindings of devices between the schematic and the layout. This option preserves only user-defined one-to-one, many-to-many, many-to-one, and one-to-many device correspondence defined in the Define Device Correspondence Form. It does not report missing devices or shapes within a bound group.

Environment variable: initCreateMTM

Connectivity Extraction - Extract Connectivity After Generation

Runs connectivity extraction as part of the layout generation process. Check this option to see the incomplete nets in the design immediately after layout generation has run.

Design Planning

This group box is available only when you have the Layout EXL or higher license checked out.

Virtual Hierarchy

Generates a virtual hierarchy using the area boundary options selected on the PR Boundary tab, or updates an existing virtual hierarchy to match the schematic hierarchy. When updating an existing virtual hierarchy, the area boundary of the virtual hierarchy is not updated.

Environment variable: generateVirtualHierarchy

Auto Generate Soft Blocks

Generates soft blocks for top-level virtual hierarchy blocks that have no schematics available or have schematics with only pins but no instances or physical binding. For the virtual hierarchy blocks that have no schematic available, soft block generation uses the bound symbol view to generate pins. Soft block boundary is generated using the options defined on the PR Boundary tab.

Environment variable: generateSoftBlocks

I/O Pins

The following table describes the fields available on the I/O Pins tab of the Generate Layout form.

Field Description

Default Values

This section lets you specify attribute values and Apply them to all the pins shown in the list box.

Type

Specifies the type of pin. Valid values are Electrical and Optical.

This option is available only when both electrical and photonic data is present in the schematic.

The following options are available, if you choose pin type as Electrical.

Layer

Specifies the layer-purpose on which the pins are generated. The cyclic field lists only the conducting layers.

You can use the initIOPinLayer environment variable to specify the layer-purpose pair that you want to use for generating the pins. The default is the current layer selected in the Layer Assistant, provided it is a valid layer. Else, it is the first extractable layer in the technology file that has a pin purpose. If an extractable layer with a pin purpose does not exist, the first extractable layer with a drawing purpose is selected as the default. If there are no extractable layers, the cyclic field lists all the valid layout layers.

The layers are extracted from the validLayers constraint if they have a purpose defined. However, the purposes are not used to restrict the displayed layer-purpose pairs. To filter the purposes, use the initIOPinPurposeNames environment variable.

Environment variables: initIOPinLayer, initIOPinPurposeNames, validLayers

Width

Specifies the width for each pin. The default is the minWidth value set for the current layer in the technology file. Any change to the value is applied only if the new value is greater than the default value.

Environment variable: initPinWidth

Height

Specifies the height for each pin. The default is the minWidth value set for the current layer in the technology file. Any change to the value is applied only if the new value is greater than the default value.

Environment variable: initPinHeight

Num

Specifies how many instances of this pin to generate. If you type 0, the pin is not generated.

Environment variable: initPinMultiplicity

Apply

Applies the Layer, Width, Height, Num, and Create settings for all the listed pins.

The following options are available, if you choose pin type as Optical.

You need to check out the Virtuoso_Multitech and Virtuoso_Photonics_Option licenses to create optical pins for the design. (Virtuoso Photonics Option)

You can specify the default pin values, such as Width, Radius, and Input Angle for the optical pins using the I/O Pins tab.

Layer

Specifies the layer-purpose on which the optical pins are generated.

The default layer is the determined from the value set for the phoPinLayer environment variable. If no value is set for the environment variable, the first photonic layer in the validLayer list is used.

Environment variable: phoPinLayer (Virtuoso Photonics Option)

Width

Specifies the width of the waveguide associated with the photonic port.

Environment variable: phoPinWidth (Virtuoso Photonics Option)

Radius

Specifies the curvature of the waveguide associated with the photonic port.

Environment variable: phoPinRadius (Virtuoso Photonics Option)

Input Angle

Sets the pin angle for all the input pins in the table. The other pin angles are then derived from this value.

  • Input pin - Sets to the specified value.
  • Output pin - Sets to the 180 degree complementary angle of the input angle.
  • All other pins - Not set and must be set individually by selecting the pin and using the field below the pin table.

Environment variable: phoPinInputAngle (Virtuoso Photonics Option)

Apply

Applies the Layer, Width, Radius, and Input Angle,  settings for all the listed optical pins.

Specify Pins To Be Generated

This section lets you select pins from the list box and update the attribute values used when those pins are generated in the layout.

Click Update to update the Layer, Width, Height, and Num settings for the currently selected pins.

Term Name

Specifies the schematic terminal name. You cannot change this value.

Net Name

Specifies the net associated with the pin in the layout. You cannot change this value.

If terminal and net names differ in the schematic, Layout XL generates a pin with the same name as the schematic terminal and a net with the same name as the net attached to the terminal in the schematic. If there is no explicit net label in the schematic, both the pin and the net names in the layout are the same as the schematic terminal. This is the default behavior.

Layer

Specifies the layer-purpose on which the pins are generated. The cyclic field offers only the conducting layers.

You can use the initIOPinLayer environment variable to specify the layer-purpose pair that you want to use for generating the pins. The default is the current layer selected in the Layer Assistant, provided it is a valid layer. Else, it is the first extractable layer in the technology file that has a pin purpose. If an extractable layer with a pin purpose does not exist, the first extractable layer with a drawing purpose is selected as the default. If there are no extractable layers, the cyclic field lists all the valid layout layers.

See validLayers.

Width

Specifies the width for each selected pin. The default is the minWidth value set for the current layer in the technology file. Any change to the value is applied only if the new value is greater than the default value.

Environment variable: initPinWidth

Height

Specifies the height for each selected pin. The default is the minWidth value set for the current layer in the technology file. Any change to the value is applied only if the new value is greater than the default value.

Environment variable: initPinHeight

Radius

Curvature of the waveguide associated with the photonic port. By default, the radius is not defined. (Virtuoso Photonics Option)

This column is visible only when there are optical pins in the design.

Angle

Access direction of the photonic port. (Virtuoso Photonics Option)

This column is visible only when there are optical pins in the design.

Num

Specifies how many instances of each selected pin are generated. If you type 0, the selected pin is not generated.

To limit the number of pins that are displayed in the pin table, set generatePinsDisplayLimit to the required display limit. If the design includes more pins than the number allowed to display in the form, the additional pins are suppressed and the form is updated to mention the number of suppressed pins, as shown below. You can right-click the suppressed pin notification, and choose Un-suppress to display all the pins.

Environment variable: initPinMultiplicity

Add New Pin

Opens the Add A New Pin Form dialog, where you can specify the name of a terminal for which to generate a new pin.

To view this option, right-click in the pins table.

Pin Label

This section lets you specify the type of label generated when you create a pin. This setting is honored by the Generate All From Source and Generate Selected From Source commands.

Create Label As

Specifies whether a pin label is created when the pin is generated. You can choose to create either a Label object or a Text Display.

Environment variable: initIOLabelType.

Options

Accesses the Set Pin Label Text Style Form, where you can set the size, font, style, justification and orientation of the label lettering, and the drawing or pin layer on which the labels are displayed.If your pin labels are not visible in the canvas, turn on the Pin Names option in the Display Options form.

For this setting to take effect, you must also set the createPinLabel environment variable to t.

PR Boundary

The following table describes the fields available on the PR Boundary tab of the Generate Layout form.

Field Description

Shape

This section lets you specify whether the place and route boundary is a rectangle or a polygon.

Rectangle

Specifies a rectangular place and route boundary. Use the Area Estimation group box to specify how the size of the boundary is calculated.

Origin

Specifies the coordinates of the boundary’s origin. The default is (0.0 0.0).

Polygon

Specifies a polygonal boundary. Use the Points List to specify the coordinates of each of the vertices of the polygon.

Area Estimation

This section lets you specify how the system calculates the shape and size of a rectangular boundary.

Area estimation comprises two parts: the first specifies the aspect ratio and utilization of the boundary; the second estimates the size of boundary required to accommodate the components to be generated. To specify the aspect ratio and utilization, set two of the following four parameters. Choose one of the parameters from the first cyclic list and any one of the remaining valid choices from the second cyclic list.

Width

Specifies the width of the design boundary. The default is the size of the last boundary or 10.

Height

Specifies the height of the design boundary. The default is the size of the last boundary or 10.

Utilization (%)

Specifies the percentage of area within the cell boundary that you want to fill. The default is 25.

Environment variable: initUtilization

When the Chain, Fold, or Chain Folds options are switched on, the Utilization value is applied only after chaining and folding is complete so that the size of the boundary is calculated accurately.

Aspect Ratio (W/H)

Specifies the width-to-height ratio of the design boundary. A value of 1 specifies a square boundary; 0.5 specifies a boundary twice as high as it is wide; and 2 specifies a boundary twice as wide as it is high. The default is 1.

Environment variables: initAspectRatio and initAspectRatioOption

Estimator

Lets you choose the type of area estimator to be used.

  • PR Boundary Based: Calculates the area based on the sum of the areas enclosed by all the place and route boundaries of the components to be generated.
    Environment variable: initAreaFuncName
  • BBox Based: Calculates the area based on the sum of the areas enclosed by all the bounding boxes of the components to be generated.
    Environment variable: initAreaFuncName

Register

Opens the Add Area Estimators form, which lets you register a user-defined SKILL function to estimate the area enclosed by a PR boundary or by the area boundary of a virtual hierarchy block.

  • The SKILL function registered for estimating the PR boundary appears in the Estimator drop-down list and can be used to estimate the area of the top-level boundary when generating a layout.
  • The SKILL function registered for estimating the area boundary appears in the Soft Block – Area drop-down list and can be used to estimate the area of the virtual hierarchies when generating a layout.

If you specified deferred when you registered the PR boundary area estimator and are now choosing to generate virtual hierarchies with area boundaries, the PR boundary estimation will be deferred until the area boundary of the virtual hierarchy is created. This allows the area estimation function to use the virtual hierarchy area boundary values to determine the area for the PR boundary.

See Creating and Registering a User-Defined Area Estimation Function.

Virtual Hierarchy Area Boundary

This section lets you specify how the area boundary of a virtual hierarchy is estimated. This group box is available only when you have the Layout EXL or higher license checked out

Enclose by

Specifies the distance from the objects inside the virtual hierarchy at which the area boundary is created.

Utilization (%)

Specifies the acceptable area utilization percentage for deriving the size of the area boundary for the virtual hierarchy.

Environment variable: areaBoundaryUtilization

Top Level

Specifies that the selected area boundary settings be used for generating virtual hierarchy area boundaries only at the top level.

All Levels

Specifies that the selected area boundary settings be used for generating virtual hierarchy area boundaries at all levels in the virtual hierarchy of the top-level design.

None

Specifies that the virtual hierarchies for the design are generated without an area boundary.

Soft Block

Specifies the area of a soft block to be created. This group box is available only when you have the Layout EXL or higher license checked out.

Area

Specifies the acceptable area value of the soft blocks to be created.

The value specified using the Area field is applied by default to all the soft blocks that are generated. To override this value and to customize the area of each generated soft block, you can specify a cellview property area on the Symbol Generation Options form when creating a new symbol. Alternatively, you can update the property for an existing symbol using the Edit Cellview Properties form. In either case, a floating point value is specified for the area property.

If a SKILL function has been registered to estimate the area of a virtual hierarchy, the function appears in the drop-down list associated with the Area field. The same area estimator function can be accessed using the Adjust Area Boundary form in the Virtuoso Design Planner.

Environment variable: softBlockArea

Floorplan

The following table describes the fields available on the Floorplan tab of the Generate Layout form.

Field Description

Preserve Floorplanning Objects

This section lets you choose the floorplanning objects to be preserved in the generated layout.

All

Selects all the items in the list.

None

Deselects all the items in the list, or selects one or more floorplanning objects to preserve them in the generated layout.

Rows and Custom Placement Areas

Preserves any existing rows and custom placement areas in the layout. Also preserves rowRegionSpec and row regions in the layout when Generate All From Source is run.

Cellviews containing row regions open in Layout XL in read-only mode. For editing such cellviews, the layout must be opened using Launch – Layout EAD.

Environment variable: preserveRows

Blockages

Applies only to standalone blockages that have no parent object; a blockage with a parent object is preserved automatically along with its parent.

Environment variable: preserveBlockages

Area Boundaries

Preserves all existing area boundaries.

Environment variable: preserveAreaBoundary

Track Patterns

Preserves all existing track patterns.

Environment variable: preserveTrackPattern

Clusters

Preserves any existing clusters.

Environment variable: preserveClusters

Cluster Boundaries

Preserves cluster boundaries only if clusters are also being preserved.

Environment variable: preserveClusterBoundaries

PR Boundary

Preserves any existing PR boundaries.

Environment variable: preservePRBoundary

Snap Boundary

Preserves snap boundaries only if PR boundaries are also being preserved.

Environment variable: preserveSnapBoundary

All

Selects all the listed floorplanning objects and preserves them during layout generation.

None

Deselects all the listed floorplanning objects, marking them as not to be preserved during layout generation.

Related Topics

Add Area Estimators Form

Symbol Generation Options

Adjust Area Boundary

Edit Cellview Properties

Layout Generation

Generating All Components from Source

Rapid Adoption Kit (Introduction to Connectivity-Driven Design in VLS XL)

Add A New Pin Form

Set Pin Label Text Style Form

Generation of RF TLine Chains (Virtuoso MultiTech Framework)

Define Device Correspondence Form

Layout XL Forms


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