Cadence provides the EE_pkg package that defines the built-in nettype, EEnet that allows you to establish a SystemVerilog UDN-Electrical ((V, I, R values) connection. You can port existing wreal models to SV.
The EE_pkg.sv package file contains the definition of EEnet nettype (UDN), EEstruct (UDT), and res_EE (UDR).
The user-defined type (UDN, EEnet) handles pins that are structures (UDT EEstruct) of the three fields: V (voltage), I (current), and R (R). This allows lots of options for how the net can be driven such as:
- Specify V and R with I=0 for voltage with series resistance
- Specify I and R with V=0 for current with parallel resistance
- Specify V with R=0 for ideal voltage source
- Specify I with R=
`wrealZStatefor ideal current source
EEnet models a combination of a series of voltage sources and resistors and a parallel current source and defines the resolution function (res_EE) to generate a resolved voltage from any useful combination of the inputs. The EEnet nettype is ideally suited for situations where a single node manages interactions between several drivers and loads. Also, in cases where the V/I/R values for sources and loads are directly defined at any given point in time, which results in a direct solution by the EEnet resolution function.
Resolution with the built-in UDR function provides:
-
V = resolved node voltage (or
`wrealXStateif multiple ideal voltage drivers) -
R = effective impedance at node (parallel combination of all connected resistances)
-
I = 0 normally (or current through voltage source if driven by ideal voltage src)
-
The package is included in the installation at $INSTALL_ROOT/tools/affirma_ams/etc/dms/EE_pkg.sv. When the software is installed, the package is compiled into the $INSTALL_ROOT/tools/affirma_ams/etc/dms/dmsLib directory.
The new EE_pkg package contains the definition of EEnettype and resolution. It provides the user-defined type EEnet that handles pins that are structures (EEstruct) of three real values {V,I,R} (Voltage, Current, Resistance). EEnet models a combination of a series of voltage sources and resistors and a parallel current source and defines the resolution function to generate a resolved voltage from any useful combination of the inputs.
You can also refer to the examples related to electrical equivalent (EE) controlled elements for use with EE_pkg to model the electrical operations in SV in the $INSTALL_ROOT/tools/affirma_ams/etc/dms/dmsLib/EE_pkg_examples directory. See the Readme.txt file in the EE_pkg_examples directory for more information on the examples.