Product Documentation
Virtuoso ADE Explorer User Guide
Product Version IC23.1, November 2023

15

Working with AMS Simulator

ADE Explorer and ADE Assembler provide seamless integration of the Spectre AMS Designer and Xcelium Mixed-Signal simulator. The integration of the Spectre AMS Designer simulator with ADE Explorer or ADE Assembler creates a design environment with the look and feel expected by the analog and mixed-signal designers who already use these tools. When using this integration, you can access designs using the same tools you currently use for pure analog and mixed-signal designs.

You can use the Virtuoso® Hierarchy Editor to specify the cellviews that you want to use in your design. A configuration (config) is a set of binding rules that defines which cellviews are part of the design for a given purpose (such as netlisting and simulation). Using the Virtuoso Hierarchy Editor, you can view the hierarchy of these cellviews and apply view switching to mix and match abstraction levels depending upon which phase of the design cycle you are performing.

To simulate your design with AMS Designer in ADE Explorer or ADE Assembler, you must specify a top-level config cellview for your design hierarchy. The design can contain other config cellviews at lower levels in the hierarchy. See Creating a Configuration Cellview for information on how to create a config view

You can use the variable TESTBENCH_TOPCELL to access the top cell name of a testbench and to backannotate the SDF delays. This variable is automatically saved in the runSimulation script generated by AMS Designer.

For example:

The top cell name is written into the TESTBENCH_TOPCELL variable through the runSimulation script as follows.

export TESTBENCH_TOPCELL="test_sim"
xrun -f xrunArgs

The following xrun option is specified with a file that uses this variable. On running a simulation, it backannotates the SDF delays and writes them to the log file sdf.log.

-sdf_cmd_file c_sdf
cat c_sdf 
COMPILED_SDF_FILE = "${CDIR}/top_cell.sdf.X",
SCOPE = "${TESTBENCH_TOPCELL}.I0",
LOG_FILE = "sdf.log"
When ADE Explorer is running a single-point simulation, you can use the ‘Optimize Single Point Run’ option on the job policy setting form to optimize the run. For more details, refer to the section Optimizing a Single Point Run.

This chapter covers the following topics:

For an overview of the above steps, see the Running AMS Simulation in ADE Explorer video on Cadence Online Support.

Creating a Configuration Cellview

A configuration (or config) is a view of the cell (or cellview). You can have different config cellviews for different purposes.

To simulate your design in the AMS Designer Virtuoso ADE Explorer environment, you must have a top-level config cellview. The top-level config cellview can be a HDL text module or a schematic. The top-level config can contain other config cellviews lower in the hierarchy.

Configurations let you bind to different cellviews as your design evolves from concept to finish. For example, you might begin the design process using high-level behavioral models of your design components; later, you might insert modules into test fixtures; you might replace behavioral descriptions with schematics and finally, add post-layout views, as the design process approaches implementation.

You can create configuration rules that define what views to include in the hierarchy at three different levels:

Global level

Using a global view list and stop list

Cell level

Using cell-based view lists — which affect the cell as well as the structures below the cell in the hierarchy — and cell bindings

Instance level

Using instance-based view lists — which affect the instance as well as structures lower in the hierarchy — and instance bindings.

You can use the Virtuoso® Hierarchy Editor to create a configuration (config) cellview as follows:

  1. Choose File — New Config to view the New Configuration form.
  2. On the New Configuration form, click Use Template.
    The Use Template form appears.
  3. Select AMS from the Name drop-down list.
    The resulting view list is:
    verilogams veriloga behavioral functional schematic symbol
    Symbol views must have associated underlying models that describe the represented device for AMS simulation.
  4. Click OK.
    All design instances and their cell bindings appear in the Virtuoso Hierarchy Editor window.
  5. (Optional) In the Global Bindings group box, you can type directly in the fields to edit the lists as required. For example, VHDL users might want to add a wildcard asterisk to View List.
  6. Choose View - Update to check and save the new configuration.

An Update prompt appears.

  1. Click OK to save the config view.

Setting Up the Default Simulator for a Configuration

By default, a configuration uses the default simulator which is set using the variable asimenv.startup simulator.

To use a specific simulator for a particular configuration,

  1. Set the variable hed.ade setAmsSimulator to nil.
  2. Define a constant named simulator through the Edit Constants form in Virtuoso Hierarchy Editor.
  3. Specify a simulator name as the constant value.
    For example, setting the value spectre for the constant simulator, will set Spectre as the default simulator for the config view.
    Here, the value of the simulator constant will override the default simulator, set using asimenv.startup simulator. If the simulator constant is invalid, an error message is displayed in the CIW and the default simulator, Spectre, is used.
    For more information about adding constants, see Using Constants.

Setting Up a Config Cellview Using Virtuoso Schematic Editor or Virtuoso Text Editor

While working on a schematic cellview or a text cellview, you can set up a corresponding config cellview directly from Virtuoso Schematic Editor (VSE) or Virtuoso Text Editor.

To view the Configuration menu in VSE and Text Editor,

The Configuration menu includes the following options:

For more information, see:

Using VHDL Design Units in a Configuration

To instantiate a VHDL design unit in a text module or schematic, bind to the architecture view of the VHDL design unit in the configuration. You can also instantiate Verilog-AMS modules in VHDL modules.

Netlisting to Make the HDL Design Unit Information Current

If you edit an HDL design unit through Virtuoso (such as a SystemVerilog text module ) using the text editor (such as vi), you must netlist your design to ensure that the Virtuoso® Hierarchy Editor has up-to-date information. Otherwise, design expansion might not result in what you expect.

The integration of the AMS Designer simulator and Virtuoso ADE Explorer has the following features:

To read some frequently asked questions about AMS-in-ADE Explorer, choose Session – FAQ from the ADE Explorer window.

ADE Explorer and AMS Integration

Following significant differences are introduced with the AMS integration:

cds_alias

cds_alias is a simple cell which is defined in the library "basic". This cell is required only if your design contains the cds_alias instances. If the design that you are using contains cds_alias and you have not defined a library "basic" in your cds.lib, then a default cds_alias cell is created under the top design.

For example, if the cell, cds_alias is in library "basic", you need not do anything. It will be compiled under implicit_tmp_dir/basic/cds_alias/functional. However, if the library "basic" is not present in cds.lib, AMS-ADE Explorer will itself compile it in implicit_tmp_dir/<design_lib>/cds_alias/functional.

Setting up AMS Options

By default, when you select ams as your simulator, Spectre is selected as the solver for the simulation. But you can select the UltraSim solver by clicking the Simulation - Solver menu option, and selecting UltraSim from the Choose Solver form. After selecting the solver, you can set Spectre AMS Designer and Xcelium Mixed-Signal simulator options by choosing the appropriate option from the Simulation – Options submenu.

Starting Xcelium 20.03, the AMS simulator does not support the UltraSim solver.

Choosing a Solver

Choose Simulation – Solver to open the Choose Solver form, in which you can select either Spectre or UltraSim as the solver.

Your choice appears next to the name of the selected simulator below the title bar as highlighted in the snapshot below.

If you are using the Spectre AMS Designer Simulator in IUS 8.1 or later releases, and have selected Spectre as the solver, you can choose Setup – Performance to specify performance options.

When you change the solver, the values in all GUI fields will be reset to the default values for that solver.

Analog (Spectre)

Choose Simulation – Options – Analog (Spectre). The Simulator Options form appears.

For details, refer to the Immediate Set Options in the Spectre Circuit Simulator Reference.

FastSPICE (UltraSim)

Choose Simulation – Options – FastSPICE (UltraSim). The FastSPICE (UltraSim) Options form appears.

For more details about the Virtuoso UltraSim simulator options, refer to the Virtuoso UltraSim Simulator User Guide.

AMS Simulator

You can set the AMS options using the AMS Options form. To open this form, choose Simulation – Options – AMS Simulator.

The next sections explain the tabs in the AMS Options form.

Main tab:

In the Main tab, you can specify INCLUDE, TIMESCALE, DISCIPLINE, LIBRARY COMPILATION, and OTHER options.

You can manually reorder the specified files with the up and down arrows.
For the AMS Unified Netlister with xrun mode, the LIBRARY COMPILATION OPTIONS section is displayed in the Main tab.

In the OTHER OPTIONS section, specify the following:

Netlister Tab:

In the Netlister tab, you can specify DEFAULT GLOBAL SIGNALS DECLARATION and NETLISTER OPTIONS. The following options are available in this tab:

The following scenarios apply to its flow:

Working with Global Signals in AMS

A global signal is a signal that is connected by name across all levels of a design hierarchy without using pins. Global signals can come from schematic data or from text modules. AMS is aware of only global signals that come from schematic data. You can use the Global Signals form to declare a signal that is used as an out-of-module signal reference.

To add a global signal,

  1. In the AMS Options form, on the Netlister tab, click the Global Signals button.
    The Global Signals form appears. If the design has not been netlisted after recent changes, you are prompted to netlist the design so that the Global Signals form can display the latest data.
  2. Global signals are displayed in a tabular format. It includes the following information.
    • The first column indicates the alias of aliased signals. They represent:
      • The beginning of the aliased set: /--
      • The aliased signals in between: |--
      • The end of the aliased set: \--
    • The Origin column is either blank if the signal was added using the Global Signals form, or it has the value D to indicate that a signal has been extracted from the design.
    • The Signal column shows the name of the signal.
    • The Namespace column displays the namespace in which the signal was created.
    • The Wire Type column shows the wire type of the signal.
    • The Discipline column shows the discipline of the signal.
    • The Ground column indicates if the global signal is used as a ground reference.
      Netlisting extracts the signals in the design and merges them with the signals created using the Global Signals form. If you open the form without netlisting, it would be empty.
  3. The input fields below the report get populated by signal details when you select any signal. To change these values, you can either type over them or select values from the cyclic lists and then click the Change button.
  4. To add new global signals,
    1. Type a unique name for the signal in the Signal field. You can specify a range such as <5:8> by post-fixing it to the name.
    2. Select the namespace as CDBA, Spectre, Spice or Verilog-AMS from the Namespace cyclic list.
    3. Select one of these from the Wire Type cyclic list: wire, supply0, supply1, tri, tri0, tri1, triand, trior, trireg, wand, wor, or wreal.
      If the signal name you specify is included in the supply0 or supply1 field of the Netlister Options form, the default value for wire type would be changed to supply0 and supply1 accordingly.
    4. Type a discipline name for the signal in the Discipline field.
    5. If you want to use the global signal as a ground reference, select the Ground option. You can select this option only for signals that have the wire type wire or tri.
      If the signal name you specify is included in the ground field of the Netlister Options form, this field appears selected by default.
    6. Click the Add button.
      The new global signal appears in the list of global signals.
      You can create a new global signal from an existing one by selecting one, modifying its values and clicking Add.
  5. To delete one or more signals, select them and click the Delete button.
    You cannot delete a global signal that is extracted from the design. If you select such a signal, the Namespace and Name fields appear non-editable. If you change any of the other values, the Database Values button is enabled, using which you can set the fields back to their original values from the database.
  6. You can alias global signals into groups. Aliased signals in a group are electrically equivalent, as if they are joined by a wire. To alias global signals, select the signals to be aliased and click the Alias button.
    To select signals listed consecutively, hold down the Shift key while you click the signal names to be aliased. To select signals that are not listed sequentially, hold down the Ctrl key while you click the signal names.
    When you alias signals, they redisplay consecutively in the global signal list, joined by a vertical connecting bar. If you alias signals belonging to separate aliased signal groups, all of the signals in the groups are aliased.
  7. To unalias signals, select the signals to be unaliased from the group, and click the Unalias button. If an alias set has only two signals, and you unalias one, the other also gets automatically unaliased.
  8. When you have finished editing the list of global signals, click OK.

You need to regenerate the netlist so that the changes made in this form reflect in the netlist and cds_globals module is regenerated. If you try to create or re-create the netlist without applying the changes in the Global Signals form, your changes get overwritten by the netlist. This is the reason a prompt appears as follows: 

While netlisting, the globals would again be extracted from the design and the globals form would be updated. Unsaved changes, if any on the globals form would be lost. Proceed with netlisting?

Netlisting includes the following actions:

  1. It extracts information about all the global signals and design variables from the design.
  2. Information about variables is merged with the design and written as it is to the verilog.vams file.
  3. The global signals information is updated with any new extracted global signals that you modified in the current session.
  4. If an extracted global signals exists in the global signals information and its origin is marked as D, and it has not been modified in the design, it is not copied.
  5. If an extracted global signals exists in the global signals information and its origin is marked as D, and you modified it using the Global Signals form in the current session, the values are copied over and a message appears saying so.
  6. If it exists in the global signals information for the session and the Origin is not marked as ‘D’, a prompt appears as follows:
    A global with the name ‘%s’ already exists in the session and is now also found in the design. Using the one that exists in the session.

The Global Signals form appears updated the next time it is opened.

The Mixed Signal Netlisting Options are available in the Netlister tab of the AMS Options form for AMS simulator only when the AMS Unified Netlister with xrun option is selected from the Netlist and Run Options form.

These options enable the Embedded Module Hierarchy (EMH) CDL netlister to generate the digital and analog CDL netlists, simultaneously.

The Use maskLayout views for binding digital instances field allows you to enable the EMH netlisting.

The Digital Netlist File Name field allows you to specify the name of the output file.

The Print power/ground connectivity field allows you to print the power or ground connectivity across the digital module hierarchy. This does not impact the top-level netlist.

The List of digital instance in schematic hierarchy field allows you to specify the list of digital instances in the design.

This field is automatically populated if the top-level design contains instances with the lxEMHStart property. You will need to update the mapped name to ensure the mapping is correct. For example, (“L/C/Sch” “I0” “L/C/Lay”) should be replaced with (“L/C/Sch” “I0” “L/C/Lay” “|I0”).

If the top-level design does not contain any instance having the lxEMHStart Boolean property, the List of digital instances in schematic hierarchy text box is automatically populated without the instance names. For example, if (“DemoLib/top/schematic” “” “DemoLib/top/layout”), you need to update the instance names in this text box.

It is recommeded that before generating a netlist, you review the list to verify that it contains only valid SKILL forms and update accordingly. You can choose to generate the netlist in any one of the following way:

Sample inputs:

(("DemoLib/top/schematic" "I1" "DemoLib/block/layout") ("DemoLib/mid/schematic" "I0" "DemoLib/top/layout"))

(("DemoLib/top/schematic" "I0" "DemoLib/block/layout"  “|I0”))

(("DemoLib/block/schematic" "I0" "DemoLib/block/layout"  t))

The Print physical only instances in digital hierarchy field allows you to print the physical only instances in digital module hierarchy.

The Print definition of leaf cells in digital hierarchy field prints the empty standard cells in the digital netlist.

The digital module hierarchy in the layout contains instances of standard cells. By default, these instances are considered as stopping instances, and the mixed-signal netlister does not print the subcircuit definition for standard cells. If you have the standard cell definitions available from the foundry, you can directly include these definitions during LVS or SVS.

However, if the Print definition of leaf cells in digital hierarchy option is selected, the mixed-signal netlister prints the empty standard cell definitions in the digital netlist.

The Only include instances of these physical cells field allows you to specify the physical instances that need to be printed in the netlist. If you do not specify a cell name, then all the physical instances are printed in the netlist.

You can also use * wildcard as a suffix when specifying cell names, such as FILL*, MFILL*. The physical instances of cells matching the specified pattern are printed in the netlist. However, other physical-only instances are ignored.

The Netlist macro instances from these libraries field allows you to specify the libraries from the cds.lib file. The instances of analog schematic cells from the specified libraries are considered hierarchial instances and are netlisted hierarchically by the mixed-signal netlister.

Messages Tab

Using the Messages tab, you can control the messages for xmvlog, xmelab, xmsim and xrun. In this tab, you can specify the following options:

Maximum number of errors: Number of error messages for xmvlog, xmelab, and xmsim.

Print informational messages: If selected, displays the message from the tool.

Display runtime status: If selected, displays the runtime status.

Suppress all warnings: Suppresses all warnings. If this field is selected, the Suppress all warnings field is disabled.

Suppress specific warnings: Suppresses warnings with a code.

Print Messages about resolving instances: This option prints informative messages during execution.

Suppress e-pulse error messages: This option suppresses pulse control error messages.

Print extended VHDL assert messages: This option displays VHDL assert messages with additional information specifying the location in code from where the function or procedure is being called.

Select the PLI tab.

In the PLI tab, you can specify the following options:

Dynamically load VPI libraries: Dynamically loads the specified VPI application.

Dynamically load PLI libraries: Dynamically loads the specified PLI application.

Enable delay annotation at simulation time: This option disables the optimization in the simulator that take delays into account. Use this option if you intend to modify delays at simulation time. Using this option sets the default access to simulation objects to read/write when the design is elaborated.

Suppress VPI/PLI warning and error messages: Disables printing of PLI warning and error messages.

Suppress VPI/PLI messages caused by optimizations: Prints a warning message only the first time that a PLI read, write, or connectivity access violation is detected.

Disable constraint checking in VDA applications: The VDA library is a C interface library that provides a mechanism for interaction between other C interface libraries and the objects, scopes, and data types in the VHDL model. VDA also contains routines for examining and manipulating the values of VHDL objects, as well as for setting up callbacks on signal events and simulation times. See Chapter 6, The VHDL Design Access Library, in the Cadence NC-VHDL Simulator C Interface User Guide for details on VDA functions.

SDF Tab

In the SDF tab, you can specify the following options:

Use SDF command file: Specifies the command file to be used.

Delay type: Enables you to select the delay type. By default, it is set to None.

Suppress SDF warnings: Disables the SDF warnings.

Allow unique delays for each source-delay path: Enables or disables unique delays for each source-delay path.

Include detailed information in SDF log file: Allows you to print information in SDF log file.

Round precision of timing in SDF file: Allows for precision of timing in SDF file.

In VERILOG section, you can specify the following options:

Suppress SDF cmd file info msgs (Verilog): Allows printing of command file information messages.

Disable celltype validation (Verilog): Enable or disable celltype validation.

Allow SDF worst-case rounding (Verilog): Allows for worst-case rounding of SDF.

Do not run $sdf_annotate tasks automatically (Verilog): Allows you to disable the automatic sdf_annotation tasks.

In VHDL section, you can specify the following option:

Select delay value for VitalInterconnectDelays (VHDL): Specifies minimum or maximum delay value to be used during VITAL SDF annotation.

Timing Tab

In the Timing tab, you can specify the timing options for VERILOG and VHDL.

Miscellaneous Tab

In the Miscellaneous tab, you can specify INCLUDE options used by xmvlog, ACCESS options used by xmelab and PROFILER options used by xmsim. You can also specify few other VHDL options used by xmvhdl.

You can select the Linter check option to turn on the AHDL linter feature that enables you to detect modeling issues in analog/mixed-signal Hardware Description Languages (AHDL). The AHDL linter feature comprises of static and dynamic lint checks. Static lint checks are performed before analysis. Dynamic lint checks are performed during analysis for dynamic modeling issues. Choose Simulation – Linter Log in the simulation window to view the AHDL Linter report.

For more information about the AHDL Linter feature, refer to the description of AHDL Linter in the Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide.

You can select custom AHDL library by specifying the directory path in AHDL Library Directory. If it is left empty, the default -ahdllibdir value is used.

Additional Arguments Form

The Additional Arguments form lets you add additional arguments that cannot be specified in the AMS Options form.

Field/Column Description

Additional Arguments

This table lets you specify additional arguments that cannot be specified in the AMS Options form.

Enable

Enables or disables the specified argument.

Argument Type

Specifies whether the given argument is a Spectre or xrun argument.

Additional Argument

Lets you specify additional arguments that cannot be specified in the AMS Options form.

Pre-commands for xrun

Controls the availability of the fields KSH Commands being included and KSH File including commands.

  • none: Disables the fields KSH Commands being included and KSH File including commands.
    This is the default.
  • command: Enables the field KSH Commands being included.
  • file: Enables the field KSH File including commands.

KSH Commands being included

Specifies the ksh commands to be added to the runsimulation file, before the xrun -f command.

KSH File including commands

Specifies a file containing Ksh commands that are then copied to the runSimulation file, before the xrun -f command.

Setting up Environment Options

To set the environment options for the AMS simulator:

Configuring IE card information using IE card setup in ADE Explorer

Setting IE Cards

The interface element (IE) card specifies the parameters, optionally, for a particular design unit. If you do not specify a design unit, the elaborator applies the parameter settings to all IEs globally.

You can use an IE card to automate the process of creating a custom discipline and connect rule for connecting the custom discipline to the electrical discipline. The software applies the custom discipline to domainless nets in your design. So, if you have digital modules with undeclared port disciplines, you can use an IE card to specify a discrete discipline for domainless nets and the elaborator will insert the appropriate connect module automatically.

To set the IE card parameters:

  1. In the ADE Explorer window, choose Setup – Connect Rules/IE Setup.
    The Interface Element (IE) Setup form appears.

    The Interface Element (IE) Setup form enables you to add an interface element and its parameters. Each row in the table contains the following information:
    • Enable: If selected, adds the IE card information in the amsd control block. You can select the check box in the Enable column to add an IE card.
    • Scope: Specifies the scope for the IE card. By default, global is selected as the scope. However, you can select the following scopes from the drop-down list: lib, cell, celluport, cellport, inst, instport, net.
    • Scope Applied To: Specifies the name of the instance/port/net/library/cellname, based on value selected from the Scope drop-down list, to which the scope is applied. You can either type a value in this field or click the table cell and then click the browse button ( ) to select the instance/port/net/library/cellname from the schematic or Library Manager. Alternatively, you can click the schematic button( ) to select a value from the schematic or LibraryManager. This field is editable and can also accept wild cards to specify designated multiple instances/nets/ports. You can specify multiple entries with each entry separated by a semicolon (;) as the delimiter.
      All scope types, except global, require a value to be specified in the Scope Applied To field to generate the IE card.
    • Supply Type: Specifies the voltage power supply type, based on the value selected from the Supply Type drop-down list, namely, Value, DVS NET and Hier-DVS NET. If you set this field to Value, then the Supply Value/Net field will accept a Supply voltage value. If you set this field to Hier-DVS NET then the Supply Value/ Net field will accept a hierarchical path to a net as a value.
    • Supply Value/Net: Specifies the voltage power supply value. You can either specify a constant value, a design variable by using the VAR syntax, or type the hierarchical path to a net in this field. Alternatively, you can click the table cell and then click the browse button ( ) to select the net from the schematic. A net selected from the schematic automatically becomes a VDD net. Based on the value that you specify on this field, the connrule parameter value in the Extended tab automatically changes to CR_full_fast versus CR_dynsup_full_fast and the respective supply parameter receives the value vsup or vddnet on the respecitive connect rules.
      The CR_dynsup_full_fast connect rule is available in INCISIV 15.1 or a later release. Therefore, to access dynamic voltage supply feature, you need to set the appropriate INCISIV release.
      For example, a numeric value or design variable leads to the selection of the CR_full_fast connect rule, whereas a hierarchical net will lead to the selection of the CR_dynsup_full_fast connect rule.
      When the CR_dynsup_full_fast connect rule is selected, you must specify a value for the mandatory parameter, vssnet, which is displayed on the Basic tab.
      You must specify a value in the Supply Value/Net field whenever a connect rule associated with selected IE card needs voltage supply.
      When the CR_dynsup_full_fast connect rule is selected, the Supply Value/Net field only accepts a hierarchical path to a net as a value.
      The default connect rule for the IE card is CR_full_fast, which has vsup as the supply parameter with a default value of 1.8V. Therefore, by default, 1.8V is specified for this field. There are some other connect rules for which vsup is not required. For such connect rules, this field does not contain any value.
      If you have two IE cards that have the same discipline, you must specify the same supply voltage for them.
    • Updated Parameters: Displays the IE card parameters that have been updated.
      You can move an IE card up or down the table by clicking the up ( ) and down ( ) arrow buttons. You can view the connect rule associated with the selected IE card by clicking ( ). You can delete an IE card by clicking the delete ( ) button.

    You can also select some of the above options by clicking the right mouse button on the selected IE card and selecting the required option from the context menu, as shown below.
    You can select the Advanced Setup option to change the IE card parameters for the selected scope. When you select the Advanced Setup check box, the Interface Element (IE) Setup form expands to display the IE card parameters that you can modify for the selected IE card in the IE cards table.
    The IE control and parameters section consists of three tabs, Basic, Extended, and EEnet listing the parameters with their default values. You can modify a parameter by changing the value as per your requirements. You can place the mouse pointer over a parameter name to display a tooltip that provides a brief description about the parameter and its default value in the associated connect rule, which can be changed using the Extended tab.
    In the Extended tab, you can set the following parameters:
    • mode - Enables you to insert the interface element as splitted or merged.
    • connrule - Enables you to select a connect rule for the associated IE card in the IE cards table from the drop-down list. The default connect rule is CR_full_fast.
      Select the <Using UCM> option to set up IE cards using the Universal Connect Module (UCM) and to view the options accuracy and supply.
    • discipline: Enables you to select the discrete discipline associated with the automatically chosen connect module from the selected connect rule. Default is an empty discipline which causes xmelab to automatically generate a discipline, however, if you have your own discipline then you can specify it in this field. The drop-down list contains built-in disciplines in addition to any other predefined disciplines that are specified using the .cdsinit disciplinesList variable. For example, envSetVal("ams.envOpts" "disciplinesList" 'string "discipline1 discipline2") in the .cdsinit file will add discipline1 and discipline2 along with the built-in disciplines in the discipline drop-down list.
      In addition, you can change other IE parameters such as vto, rz, vdelta, vtoldelta and so on.
    • Enable IE Report: Generates a detailed IE report containing information about IE, port discipline, sensitivity, and so on. This option is also presented under the Miscellaneous tab of the AMS Options form. You can choose Simulation – Output Log – IE Report in the ADE Explorer window to view the IE report.
    • Always Use IE-card Based Setup: Disables the options Interface Element/lE-card Based Setup(OSS/UNL) and Connect Rule/Connect Module Based Setup and displays only the options available for IE-card based setups.
    • Use UCM as Default: Specifies that by default, any new IE cards must be inserted using the UCM. UCM consolidates and replaces the existing connect modules in connectLib in the Xcelium installation. The IE cards are then created with the default UCM configuration unless the parameter values are specified explicitly. This means that by default, the values for the parameters accuracy and supply are set to moderate and Const/LPS respectively.
      Note the following:
      • This check box is selected automatically when the simulation performance mode is set to Spectre FX.
      • Selecting this check box does not affect the existing IE cards in the table.
      • Cadence recommends that you enable this feature by using the environment variable ams.envOpts ieUseUcmAsDefault while setting up a maestro session.

Click the Default button to change the values of all IE parameters back to their default values.

Click the View Connect Rule File button to open the connect rule file.

The connect rule file opens in a text editor. Click any hyperlink provided in the connect rules file to view the associated connect module file, as shown below:

The connect module file opens in a text editor.

connectRules_newIE.il file

The connectRules_newIE.il file contains the built-in connect rules which are displayed in the connrule drop-down list box.

ADE Explorer searches for the connectRules_newIE.il file in the following locations:

If multiple connectRules_newIE.il files are located, their contents are concatenated and displayed in the Interface Element (IE) Setup form.

All Cadence-supplied connect rules or connect modules are stored in the connectRules_newIE.il file located in the /tools/affirma_ams/etc/connect_lib/connectLib directory in your Cadence Incisive Unified Simulator (IUS) installation directory.

You can use the genIeConnRulesFile command to invoke automatic compilation of your user-defined connect rules into a custom connectRules_newIE.il file.

genIeConnRulesFile [-help] [-destpath <destination path>] -lib <lib1> <file1> 
[file2 ...] [-lib <lib2> <file3> [file4 ...]] [-rulefile <rulesFile>] [-rule <ruleName1> [ruleName2 ...]]

Here:

When importing user-defined connect rules from a connect rule file or a pre-compiled connect library, ADE compiles the connect rule file and generates the connectRules_newIE.il file under the /tmp directory and then it merges the imported connect rules with the existing connect rules in the IE Setup form. The connect rule file from pre-compiled connect library is searched under the selected library, cell, and view.

A few points to note:

For an overview of IE Card Setup, see the Configuring IE Card Information Using IE Card Setup in ADE Explorer demonstration available on Cadence Online Support.

Setting Connect Rules

A connect rule specification is used to insert selected connect modules within a mixed signal scope. A connect module is a module that is automatically inserted to connect the continuous and discrete domains through disciplines (mixed-signal nets) of the design hierarchy, together. For more information, see the Connect Modules section in the “Mixed-Signal Aspects of Verilog-AMS” chapter of the Cadence Verilog-AMS Language Reference.

To set connect rules,

  1. In the ADE Explorer window, choose Setup – Connect Rules/IE Setup.
    The Interface Element (IE) Setup form appears.
  2. Choose the Connect Rule/Connect Module Based Setup option.
    The form displays a list of connect rules used in the simulation that are passed to the elaborator. For using the default set of connect rules, you can set an environment variable called connectRulesList in .cdsinit.
    • The List of Connect Rules Used in Simulation table displays the connect rules that will be used when the run mode is AMS Unified Netlister with xrun. For more information about the AMS Unified Netlister with xrun run mode, see Setting Up the AMS Netlister Options.
      Each row in the table has the following details:
      • Type—Displays the type of the connect rule as Built-in, User-defined or Modified built-in.
      • Rules Name —Displays the name of the rule, which is the cell name.
      • Details—Displays the name of the library in which the rule exists and the view name for the rule.
        You can use the genConnRulesFile command utility to have your user-defined rules displayed as built-in rules from the Built-in rules group box. For more information about the genConnRulesFile command, see connectRules.il File.

Adding Connect Rules

You can add built-in or user-defined connect rules. To add a built-in connect rule, choose the built-in connect rule from the Rules Name drop-down list and click Add.

For more information about customizing built-in rules, see Customizing Built-in Rules.

When you customize a built-in rule, its type appears as Modified built-in and a number is suffixed to its name. For example, a built-in rule ConnRules_3V_mid, when customized, is renamed to ConnRules_3V_mid1.

Renaming Connect Rules

To rename a rule in the List of Connect Rules Used in Simulation table,

  1. Select a rule from the table.
  2. Click the Rename button.
    The Rename Connect Rules pop-up box appears.
  3. Specify a unique name for the selected connect rule and click OK or Apply.
    If a rule by the same name exists in the Connect Rules table, an error message appears and the pop-up remains open.
    The list of rules in the Select Connect Rules from also shows the modified connect rule name.

Deleting Connect Rules

To delete a rule in the List of Connect Rules Used in Simulation table,

  1. Select one or more rules in the List of Connect Rules Used in Simulation table.
  2. Click the Delete button.

Copying Connect Rules

To copy a rule in the List of Connect Rules Used in Simulation table,

  1. Select a rule in the List of Connect Rules Used in Simulation table.
  2. Click the Copy button.
    The Copy Connect Rules form appears.
  3. Select either Library or File in the Copy to pull-down box to indicate where you want the rule copied to.
    If your choice is Library, the Library and Rules Name fields are enabled and you need to specify the relevant values in them. You may either type in these values or select them using the Browse button. If your choice is File, the File field is enabled and you need to specify a filename for the rule to be copied into. You can specify a filename indicating the path. If you specify a filename without a path, it implies that it is in the current working directory. If you specify a name for a file on which you do not have read permission, you will see an error message saying so.
    The Browse button brings up the library browser if you select Library and the file browser if you select File.
  4. Click OK.
    The new copied rule appears in the connect rules table. This is a convenient way to copy your modified connect rule to a permanent location in your library. The connect rules will be saved in your state files, but you may want to save it to a permanent library as well.

Changing the Sequence of Connect Rules

To change the sequence of the rules displayed in the List of Connect Rules Used in Simulation table,

  1. Select a rule in the List of Connect Rules Used in Simulation table.
  2. Click the Up or Down buttons.
    All the selected rules are auto-compiled. They are passed to the elaborator for processing. If two rows have a matching statement, the first of these rows is used. If two rules in a particular row have a matching statement, the last of these statements is used.
  3. Click OK to save the settings in the current session.

connectRules.il File

The connectRules.il file contains the built-in connect rules that were specified when running the genConnRulesFile and are displayed in the Select Connect Rules form.

ADE Explorer searches for the connectRules.il file in the following locations:

If multiple connectRules.il files are located, their contents are concatenated and displayed in the Select Connect Rules form.

All Cadence-supplied connect rules/ connect modules are stored in the connectRules.il file located in the /tools/affirma_ams/etc/connect_lib/connectLib directory in your Cadence Incisive Unified Simulator (IUS) installation directory.

You can use the genConnRulesFile command to invoke automatic compilation of your user-defined connect rules into a custom connectRules.il file.

genConnRulesFile [-help] [-destpath <destination path>] -lib <lib1> <file1> 
[file2 ...] [-lib <lib2> <file3> [file4 ...]] [-rulefile <rulesFile>] [-rule <ruleName1> [ruleName2 ...]]

where:

If you place your custom connectRules.il files in one of the locations where ADE Explorer searches for the connectRules.il files, the connect rules defined in the custom files are also displayed as built-in rules in the Select Connect Rules form.

Customizing Built-in Rules

This form appears when you click the Customize button in the Select Connect Rules form.

You use this form as follows:

  1. Specify a description for the rule in the Description field. This replaces the contents of the corresponding non-editable field in the Select Connect Rules form.
  2. The Connect Module Declarations table displays the following information about the modules in the selected connect rule:
    • Module shows the name of a connect module.
    • Mode can be blank or have either of the values merged or split. When it is blank, it indicates that there is only one port of discrete discipline on the signal. The split value indicates that there should be one connect module inserted for each port. The merged value, which is the default, specifies that only one connect module should be inserted for all the ports on a signal.
    • Parameter/Values shows a list of parameter values.
    • The direction of the first port appears in the Direction1 column and for the second port in the Direction2 column. These columns can be blank or have one of these values: input, output or inout.
      You may need to scroll to the right to see these and the remaining columns.
    • The discipline information for the first port appears in the Discipline1 column and for the second port under Discipline2. These columns may be blank for modules that do not have them specified.

    Select a module by clicking on the related row.
  3. When a module is selected, these fields get populated with the related values: Mode, Direction1, Direction2, Discipline1, and Discipline2. After you modify one or more values, click the Change button just below the Connect Module Declarations table. The changes are reflected in the table. If you select multiple rows, this Change button appears disabled.
    When you select a row, the Parameters table is also populated. You can change values by selecting a row in this table, modifying the Value and clicking the Change button next to it.
  4. If you want to see the connect module file, click the View connect module button.
    This brings up the related connect modules file as shown below.
    If a corresponding file does not exist, an error message appears.
  5. When you select only one module in the Connect Module Declarations table, the related parameters and values are listed in the Parameters table. You can select a parameter and change its value by typing over it in the Value field and clicking the Change button next to it.
    When you select multiple rows in the Connect Module Declarations table, a union of all the parameters is shown in the Parameters table with their values. If a parameter has different values in different modules, its value is shown as blank. You can specify a value to be used for a particular parameter in the Value field and click the Change button next to it. The specified value applies to all the selected modules.
  6. The Direction1 and Direction2 fields are blank by default. The possible combinations of values you may specify are:
    • input, output
    • output, input
    • inout, inout
  7. The Discipline1 and Discipline2 fields are also blank by default. They may remain blank or you may specify a discipline-pair for the selected module.
    You can also create discrete disciplines and specify them in these fields by clicking the Disciplines button, which brings up the Create Discrete Disciplines form.
    It shows a list of disciplines. You may type in a name in the Discipline Name field and click Add to create a new discipline. The name should be a legal verilog identifier. You may select one or more discipline names listed in the table and click the Delete button to delete them. This information is saved for the session when you click OK and is included in the connect modules information saved in a state file.
  8. The Connect Resolutions button brings up the Connect Resolutions form.
    It shows a list of Resolved Disciplines and Equivalent Disciplines. You can specify a discipline to be used when multiple nets with compatible disciplines are part of the same domain net.
    • You can add a new association by specifying a Resolved Discipline and an Equivalent Discipline and clicking the Add button.
    • You can modify an association by selecting a row, modifying the values in the Resolved Discipline and Equivalent Discipline fields and clicking the Change button.
    • You can select one or more rows and delete them by clicking the Delete button.
  9. Click the OK button to update the connect rules information with the changes made for connect resolutions.
  10. Click the OK button in the Customize Built-in Rules form to update the connect rules information for the session.

Using MATLAB/Simulink

The ability to run a cosimulation using MATLAB®/Simulink ®with AMS is now available. There are three use models to choose from:

MATLAB and Simulink are registered trademarks of The MathWorks, Inc.

Setting up the AMS/MATLAB Co-simulation

In order to cosimulate between AMS and Simulink®, coupler modules are required for both AMS and Simulink. For AMS, the coupler module, will be placed as part of your design in the schematic. Associated with each coupler is a verilog.vams file that contains the coupler module. This coupler module contains the system calls: $couple_init which calls the VPI code that will be used to communicate with Simulink. The system task $set_access_readwrite ensures that the proper read/write access is set for the coupler module.

There are two types of coupler cells to choose from: fixed cell coupler or Pcell coupler. The Pcell coupler is located in analogLib. For more information, see description for simulinkCoupler in Analog Library Reference. You can place the Pcell coupler and configure the number of input and output pins along with other options described below. You can create the matching verilog.vams file that contains the correct inputs/outputs as configured in the Pcell on the schematic by using the GUI in ADE Explorer as described below.

If there are specific input/output configurations that you know you will use frequently, you can create a fixed cell coupler and use that fixed cell in your schematic rather than a Pcell. The verilog.vams file will be created for the fixed cell when the fixed cell is created. To create a fixed cell coupler:

  1. In the schematic, choose Launch – Plugins – Mixed Signal Options – AMS.
    This results in the AMS menu being added to the Composer banner.
  2. Select AMS - Simulink Coupler Creation.
    The Simulink Coupler Fixed Cell Creation form opens.
  3. Enter the Library name where you want the fixed coupler to be placed. You may want to create a coupler library for all the fixed couplers that you would require or create them in your design libraries. Enter the coupler domain, Number of input and output pins and click the Generate Fixed Coupler button to generate a fixed coupler that can be used in any future design. A fixed cell coupler is created in the library that you specify. The name of the fixed cell coupler that gets created is: coupler_<numInputPorts>_<numOutputPorts>_[d,a]

Starting MATLAB

You can start MATLAB directly from ADE Explorer. If your design is using Pcell coupler blocks, then you need to create a verilog.ams file for the Pcell coupler block before netlisting. In the simulation window, choose Setup – MATLAB/Simulink – Create Pcell Coupler File. The Create Pcell Coupler File form appears.

If the block selected on the schematic is not a Pcell coupler block, the message about an incorrect selection appears in CIW.

After creating the verilog.vams file for the Pcell coupler, or if you are using a fixed cell coupler, choose Setup – MATLAB/Simulink – Start.

The Setup MATLAB form appears.

  1. Enter the command for starting MATLAB using MATLAB start command field. The default command to start MATLAB is “matlab”. You can enter any other command along with the command-line argument.
  2. Enter the path to the directory where matlab is launched in the MATLAB startup directory field.
  3. Enter the path to the MATLAB design in the MATLAB design name field.
  4. Enter simulation initialization timeout in AMS delay to allow MATLAB initialization. It is required to give Simulink a chance to start up before AMS. After Simulink is initialized, you can run the simulation.
  5. Do one of the following:
    Select IF

    no

    If you select the no option for Start MATLAB, MATLAB will not be started. This may be useful if you want to keep same form setup but do not want to run cosimulation or if you want to start MATLAB yourself, independent of ADE Explorer.

    before AMS starts

    If you want to start the MATLAB automatically, select the before AMS starts check box in Start MATLAB section. When you select the before AMS starts option, all the fields in the form are enabled. To run Simulink simulation automatically when AMS starts, you need to have a startup.m file that contains the sim() command in the directory, which is specified in the MATLAB startup directory field.

    now

    If you want to launch MATLAB manually, select the now option in Start MATLAB. The Start button appears and the AMS delay to allow MATLAB initialization is disabled. Click Start button to launch MATLAB.

About the AMS Unified Netlister

AMS Unified Netlister (AMS UNL) provides a comprehensive netlisting and binding framework for the Spectre AMS Designer Virtuoso use model (AVUM).

On using AMS UNL with Xcelium 21.02 a001 or a higher release version, ensure that the environment variable $PATH has the Spectre 19.1 ISR15 installation path specified in it.

The following flowchart describes the AMS UNL flow:

Benefits of AMS UNL

Some of the important benefits of AMS UNL are:

Things to Know When Using the AMS UNL Flow

AMS UNL Architecture

The following figure describes the AMS UNL architecture:

The Simulator Environment Interface processes the design and configuration information specified using ADE Explorer and provides the following information to the simulator (xrun):

AMS UNL Methodology

Hierarchy Editor

The AMS UNL flow is sensitive to the HED configuration settings — Library List, View List, and Stop List — that are available in the Global Bindings section of HED. Therefore, you must ensure the following while setting these options:

Library List

You must specify all the DFII 5x libraries used in the design in the Library List field. It is recommended to specify the libraries in the order of preferred precedence. The order can be used to influence the binding search order if there are same cells from multiple libraries.

View List

You must specify all the view types used in the design in the View List field. It is recommended to specify the cellviews in the order of preferred precedence. The order in the list determines what a particular cell uses as its default View To Use. If you do not explicitly set any view for a cell, the default View To Use is considered as the first existing view in the list. For VHDL, add the VHDL architecture names to the HED View List, and bind the VHDL cellviews to the VHDL architecture names and not the entity names.

Stop List

You must specify only the view names for which you wish the netlister to stop traversing the cell's hierarchy in the Stop List field. A hierarchical text cellview used as a stopping view in HED Stop List generates an error during elaboration. Stopping views must have no hierarchy or must be leaf-level. It is recommended to use symbol view, or a copy thereof, for text stopping views. A stopping view that has hierarchy assumes that the leaf-level hierarchical content will be found using other ways external to DFII. By default, spectre is considered the analog stop view and symbol is considered the digital stop view.

When adding or removing views from Stop List, configuration binding gets refreshed immediately upon an HED update. For example, when a symbol is added and a cell's View To Use is changed to symbol, the 5x hierarchy of the cell is removed from HED and is no longer visible. This assumes a blackbox condition and expects the cell's hierarchy (if there is any) to come from external sources, such as xrun external HDL specification (-v, -y, -f, and so on).

In addition to setting the fields in the Global Bindings section, ensure that all cellviews that are displayed as “red” in HED are properly resolved. You should either fix the unresolved cells in “red” manually, or bind them to an External HDL setting for proper blackbox resolution. This can be done by right-clicking a cell in the Cell Bindings section of HED and selecting the Set Cell View - Mark as External HDL Text (AMS UNL only) option from the context menu.

New Binding Engine

For the AMS UNL flow, a new binding engine has been implemented. The new binding engine:

Importing Text Views into Virtuoso (WDU Libraries)

The AMS UNL flow supports importing of text views into Virtuoso. You can import a text view into the Cadence 5x library/cell/view structure by using any of the following methods:

It is recommended that you use the cdsTextTo5x command because it uses xrun in the background. Also, the xmvlog -use5x and xmvhdl -use5x commands have been deprecated.

External Text Referencing (BDUs for Verilog/VHDL)

The AMS UNL flow supports configuration of text views as stop view or leaf, where the parent-level text view and its entire hierarchy can be made invisible to HED. For such design units, you can configure the parent-level text view in HED to be the stopping view, or use external text referencing with External HDL binding. The parent-level text view and its hierarchy needs to be configured using xrun specifications. AMS UNL supports the following methods:

Text Referencing Methods

A text view can be referenced as follows:

Migrating to AMS UNL

If you are migrating from a Cell-Based netlisting flow to the AMS UNL flow, consider the following:

Features of AMS UNL

This section describes the following features of AMS UNL:

Creating Text Libraries for use with the Precompiled WDU Supplemental Flow

HDL languages require file/library-specific options/bindings that must stay consistent throughout the design development cycle. The use of VHDL/SV packages need careful attention and are better managed as precompiled objects and shared between all source code requiring them. Design cycles can be better optimized by reusing precompiled objects and sharing them with multiple design groups.

The recommended methodology is to precompile the text source/packages code ahead of time with these specific requirements and then lock-down the libraries so as not to disturb the consistent and stable "IP". At the same time, HED configurations using a visible, 5x WDU approach need to access and use these precompiled "IP" libraries in a "WDU-like" use model. This creates all possible HED 5x possibilities for library and view bindings to externally referenced text in a pseudo-BDU-like use model.

The old WDU hierarchical text flow is still the predominant and the recommended use model. This flow is supplemental to the old WDU flow such that it provides the capability to:

If a flow warrants no need for these advantages, then the old WDU 5x hierarchy should be used.

By utilizing the existing HED WDU 5x configuration settings within a Virtuoso setup, a normal WDU flow with HED 5x libraries and bindings can be achieved. This flow assumes that all WDU text cellviews visible in HED have already been imported and registered within 5x using the usual methods, that is, by using precompiled xmvlog/xmvhdl -use5x scripts or using traditional DFII import techniques (see Importing Text Views into Virtuoso (WDU Libraries)).

Overview

To create a precompiled library, follow these steps:

  1. Create a directory with the name precompiledLibs in the current working directory, as follows:
    mkdir $PWD/precompiledLibs
  2. Set the environment variable XRUN_LIBS, as follows:
    setenv XRUN_LIBS $PWD/precompiledLibs
  3. Navigate to XRUN_LIBS, as follows:
    cd XRUN_LIBS
  4. Create the precompiled, non-5x version of the DFII libraries using a script that calls out multiple xrun -compile, -makelib commands, one for each library and/or file-specific options.
  5. Create and store this script at the $XRUN_LIBS location along with matching cds.lib.
  6. Allow one -makelib statement per 5x library. Create a compile script preCompileLibs.f containing the following statements:
    xrun -compile -makelib <path>:<logical_lib_name> <source files> <source file specific options> -endlib 
    xrun -compile -makelib <path>:<logical_lib_name> <source files> <source file specific options> -endlib
    xrun -compile -makelib <path>:<logical_lib_name> <source files> <source file specific options> -endlib
    where:
    path is the physical location of the precompiled non-5x libraries.
    logical_lib_name is OPTIONAL and the same logical library name of the same 5x DFII WDU library designated in the Virtuoso invoking directory and called out in the path-altered copy of the precompiled, non-5x version of the cds.lib file.
    Example of precompiled script preCompileLibs.f 
    xrun -compile -messages
    -makelib ./DigLib $PROJ_LIBS/source/DIG/*.vhd -v93 -relax -endlib
    xrun -compile -messages
    -makelib ./AMSLib $PROJ_LIBS/source/AMS/*.vhms $PROJ_LIBS/source/AMS/*.vams -endlib
    xrun -compile -messages
    -makelib ./stdLib $PROJ_LIBS/source/STD/*.vhd -v93 -endlib
    xrun -compile -messages
    -makelib ./RTLLib $PROJ_LIBS/source/RTL/*.vhd -v93 -endlib
    xrun -compile -messages
    -makelib ./testLib $PROJ_LIBS/source/test/*.vhd -v93 -relax -endlib
    xrun -compile -messages
    -makelib ./HDLLib $PROJ_LIBS/source/HDL/*.sv -endlib
    …
    Where $XRUN_LIBS is predefined as $PWD/precompiledLibs.
  7. Run the xrun -f preCompileLibs.f script from the $XRUN_LIBS location and then lock down the precompiled library directory as reusable "IP".
  8. Add the precompiled libraries in the Reference Library Setup form by clicking the Pre-compiled libraries (-reflib) Settings button in the AMS Options form.
  9. Remove all other previously referenced xrun -f files that are now referred to with the same reflib library paths/name using the REFLIB/MAKELIB options.

An additional feature has been implemented for automatic and seamless VHDL/SV package collection and compilation for the simulation phase of the UNL flow. The advantage of this feature is the ability to carry through to the xrun simulation stage any precompiled VHDL/SV packages that were found used and precompiled in the design libraries. This removes the need to search and collect all packages required for simulation. The tool does this automatically and efficiently.

The precompiled WDU libraries can now be referenced as reusable "IP" with open access to all AMS design teams working on a project. This allows reusing the libraries as shared and locked-down "IP". Digital design teams can manage these external reference libraries at their own discretion. Changes made to the external text source will be realized by the analog teams running Virtuoso by using the Pre-compiled libraries (-reflib) Settings option in ADE Explorer. This allows for seamless integration between the GUI and command-line use models. Design cycle productivity can be greatly enhanced when using precompiled, external text with this methodology. Time is saved during netlisting and compilation iterations by using external reference libraries.

Supporting Parameterized Bits Using a Pcell Symbol

In digital designs, parameterized port sizes are often used as a design reuse practice. However, in case of AMS Designer, the implementation of symbols does not support this practice. Therefore, in order to use parameterized bits, you need to create a Parameterized Cell (Pcell) symbol for the module instead of a symbol. A Pcell is a programmable cell defined in a way that each instance of the cell can be customized. And a schematic Pcell allows the connectivity of the cell to change according to parameters that are specified for each instance of the cell.

Consider the following module containing an output pin named out:

module xyz (out,in);
parameter integer bits=26;
output[0:bits] out;
input in;
logic out;
logic in;
assign out = ~in;
Endmodule

The module xyz can be reused in several designs with each having a different number of bits. In this case, bits is an integer parameter that controls the variable bus width of the output pin, out. When a Pcell symbol is created for this module, it contains a pin named out<0:26> and changing the value of the instance parameter, bits, changes the bus width of the output pin, out, for that instance of the module. When you change the value of bits, the port name for the Pcell symbol also changes accordingly. Therefore, there can be multiple instances of the same module with varying widths of the bus.

You can either create a new Pcell symbol or convert an existing symbol into a Pcell symbol and then use the Pcell symbol in your design, which can be netlisted in AMS UNL.

To know how to create a Pcell, see Creating SKILL Parameterized Cells in the Virtuoso Parameterized Cell Reference.

To convert an existing symbol into a Pcell symbol, perform the following steps:

  1. Open the symbol in the Virtuoso Schematic Editor and enter the following code in the CIW:
    dbWriteSkill(geGetWindowCellView() "mysymbol.il" "w" "4.4")
    A file named mysymbol.il is created. The code in this file contains all the correct coordinates, matching labels, and the net information.
  2. In the code generated in the mysymbol.il file, the pin name is a fixed pin name as shown below:
    dbD_0xc6384f4 = dbCreateNet(dbD_0xc62882c "out<26:0>" nil)
    Parameterize the pin names in the code as shown below:
    dbD_0xc6384f4 = dbCreateNet(pcCellView sprintf(op "out<%d:0>" bits) nil)

After creating the Pcell, perform the following steps:

  1. Load the file mysymbol.il, which contains the code of the Pcell, in CIW to generate the Pcell symbol.
  2. You can create a new verilogAMS cellview for the Pcell symbol or use an existing verilogAMS cellview of the Pcell symbol.
  3. Netlist the design.

Using the Verilog 2001 Configuration

UNL supports Verilog 2001 (V2001) configuration, which allows you to configure the contents of a design. The V2001 configuration provides the flexibility of configuring every instance in Verilog language.

It is recommended that you compile the Verilog 2001 config using the -compcnfg option as the -libmap option does not support the use of -v/-y xrun options.

Perform the following steps to enable Verilog 2001 in UNL:

  1. Choose Simulation – Options – AMS Simulator.
    The AMS Options form appears.
  2. Perform the following steps:
    • To set the Verilog config block and UNL top as the same-top, wherein the Verilog config top and UNL top have the same top levels, perform the following steps:
      • Specify the following xrun options in the Additional Arguments field on the Main tab: myconfig.v -compcnfg -top cfg1
      • Add the code for cfg1 in the Verilog configuration file, lib.map or myconfig.v, as shown below:

       config cfg1;
  design zambezi45_sim.tb_dut;
  //    Set default library search order
  default liblist  behav_lib analog_lib gate_lib;
  //    Select gate-level implementation for DUT0.m0 instance of MUX
  instance tb_dut.DUT0.m0 liblist analog_lib;
 endconfig

      Ensure that the parameter design in the Verilog configuration file, such as zambezi45_sim.tb_dut in the code for cfg1 given above, is the same as the top-level design unit specified in the config view of HED.
    • To set the Verilog config block as the sub-top, wherein the Verilog config top and UNL top are the same, but Verilog config uses a sub-config which does not match the top , perform the following steps:
      • Specify the following xrun options in the Additional Arguments field on the Main tab: myconfig.v -compcnfg -top cfg1
      • Add the code for cfg1 in the Verilog configuration file, lib.map or myconfig.v, as shown below:

       config cfg1;
  design zambezi45_sim.tb_dut;
  //    Set default library search order
  default liblist  behav_lib analog_lib gate_lib;
  //    Select gate-level implementation for DUT0.m0 instance of MUX
  instance tb_dut.DUT0.m0 liblist analog_lib;
 endconfig

      Ensure that the parameter design in the master Verilog configuration file, such as zambezi45_sim.tb_dut in the code for cfg1 given above, is the same as the top-level design unit specified in the config view of HED.
    • To set the Verilog config block and UNL top as the parallel-top, wherein the Verilog config top and UNL top are at the same level of design, perform the following steps:
      • Specify the following xrun options in the Additional Arguments field on the Main tab: myconfig.v -compcnfg -top cfg1
      • Add the code for cfg1 in the Verilog configuration file, lib.map or myconfig.v. In this case, the parameter design in the Verilog configuration file does not have to be the same as the top-level design unit specified in the config view of HED.
        The additional statement, -top cfg1 is mandatory for using the Verilog 2001 config with UNL.

Exporting IP Blocks in AMS UNL

With AMS UNL, you can export a DUT IP block (database), which includes the netlist, text files, and configuration, and then reuse it later in different testbenches running simulations with the Spectre AMS simulator. It helps simulate the design without having the need to provide absolute paths and then configure the complete design on the System on Chip (SoC) level. By default, the exported IP is saved in your current working directory, however, you can also specify the location where you want to save the IP database.

The exported IP database can be reused after updating the extracted setup files that contain the definitions for the LINUX file paths.
This feature is available only in Xcelium 17.04 or higher versions.

The following figure shows the architecture for IP export in analog and digital design flows:

To export the netlist and other binding information (referred as IP),

To know more, refer to the AMS IP Export Reuse Flow rapid adoption kit on Cadence Online Support.

To know about the runams options used to export the netlist and other binding information, see IP Export Options.

To view the complete list of runams command-line options, see Using the runams Command.

Shorting Devices

You can use Hierarchy Editor (HED) or the shortInstanceList environment variable to short devices when using the AMS Unified Netlister.

See the next topic for information on how to short devices using HED.

Shorting Devices Using Hierarchy Editor

You can set the property unlconn in Hierarchy Editor (HED) to short devices. This property can be set on the cell, instance, or occurrence level in HED.

Currently this property is supported only for devices with two terminals.

Open the config corresponding to your design in HED and perform the following steps:

  1. Choose View – Properties to view the properties applied on each instance.
  2. Choose Edit – Add Property Column to add a new property.
    The Add a Property Column form appears.
    Perform the following steps:
    1. Specify the name of the property as unlconn.
    2. Ensure that String is selected in the Property Type drop down list box.
    3. Click OK or Apply.

    A new property column, unlconn, is added in HED as shown below:
  3. Specify the value short in the unlconn property column next to the cell or instance you want to short, as shown below:

When you netlist the design, the cell or instance, for which you have set the unlconn property, are shorted in the generated netlist.

Other Important Points to Note

Using the sim_stub Property

The sim_stub property removes a bound schematic, Verilog-A, Verilog-AMS, Spectre, or SPICE block from the configuration and replaces the schematic or block with a stub module that is empty except the interfaces and discipline declarations.

By eliminating portions of your design, this property helps you identify the blocks that slow down the simulation. However, your design may not simulate correctly if you eliminate the circuitry for essential functions, such as signal generation.

For more information about this property, see sim_stub Property in Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide.

Stubs are of two kinds:

You can use the -libverbose xrun option to add the design unit resolving information in the xrun.log file.

Creating Simulation Scripts for xrun

Use the Simulation scripts for xrun option to export the simulation files from the netlist directory. This option copies all the files required for running the simulation, and generates the xrunScript file in the export directory. You can run the xrunScript file to run the AMS simulation from the command-line.

The Simulation scripts for xrun option copies all the files from the netlist directory except the definition, model, and stimulus files.

To export the simulation files,

  1. Choose Tools – Export – Simulation scripts for xrun.
    The Export xrun Controls form appears.
  2. In the xrun Export Directory field, specify the directory where the simulation files are to be exported.
  3. In the Data Export Mode field, select one of the following options:
    • Write Absolute paths—Select this option to use the absolute paths in the textInputs file for the text view.
    • Choose Copy Files—Select this option to use relative paths in the textInputs file. This option copies all the files, including the sub-directories, referred in the textInputs file from the cellview directory to the export directory.
      The textInputs file contains the text files for text views in the design.
  4. Regenerate the netlist file and other simulation input files before exporting by selecting the Regenerate Netlist check box.
  5. (Optional) Select the Export AMS Output check box to create an OCEAN file amsOutput.ocn in the specified directory that saves all the output expressions along with the amap file. This amap file is saved in the xrunExportDirectory/netlist directory.
  6. Click OK.

Reusing an Advanced Testbench

The Advanced Testbench Reuse mode lets you reuse an existing verification setup and a top-level module to reduce the verification effort. With this mode, you can reuse a digital super top above the AMSD HED configuration that you are simulating in ADE.

For example, assume that you have created an AMSD ADE testbench with an HED configuration. In parallel, the digital team has created a UVM testbench above the design under test (DUT) simulated in the AMSD ADE flow. Now, if you want to reuse the Digital on Top (DoT) setup from the digital team’s setup, the Advanced Testbench Reuse form lets you do so in an efficient manner.

See Benefits of Reusing an Advanced Testbench for more information.

There are two modes of reusing an advanced testbench:

Perform the following steps to enable the Advanced Testbench Reuse mode and set the required options:

  1. Choose Tools – Advanced Testbench Reuse. The Advanced Testbench Reuse form appears.
  2. To enable this mode, select the Enable Advanced Testbench Mode check box.
  3. Select one of the following modes:
    • Advanced Testbench Reuse Full Mode—Enables the Full Mode for reusing an advanced testbench. This mode is selected by default.
    • Advanced Testbench Reuse Simple Mode—Enables the Simple Mode for reusing an advanced testbench and the following options are displayed.
      In this mode, a SystemVerilog configuration file is not generated. If you have an existing SystemVerilog configuration for your testbench, pass it to xrun using the -f option in the xrun Arguments for Testbench table. Also, define the top cell name using the -top option in the xrun Arguments for Testbench table.
  4. (Optional) In the Add Prefix to Virtuoso Library Name field, specify a prefix for the Virtuoso library name.
  5. In the SYSTEMVERILOG CONFIGURATION OPTIONS section, specify the values for the following options:
    This section appears only when Advanced Testbench Reuse Full Mode is selected.
    • SystemVerilog Configuration Name—Specify a name for the SystemVerilog configuration file to be generated.
    • Testbench Library Name—Specify the name of the library from which the top-level source description is to be used for the SystemVerilog configuration file.
    • Testbench Top Cell Name—Specify the name of the top-level cell from which the source description is to be used for the SystemVerilog configuration file.
    • Default Library List—Specify the libraries to be searched for the source descriptions to be added to the SystemVerilog file. These libraries are searched in the order in which they are specified. By default, all the subinstances of the top-level cell in the specified library are searched, which means that the source descriptions in all the .sv files or .v files mapped to these subinstances are used.
    • Design Top Configuration Mode—This can be set to one of the following:
      • Cell—Select this option if you want all the subinstances in the specified top-level cell to be used for the instance binding of the DUT.
      • Instance—Select this option if you want only specific instances to be used for the instance binding of the DUT.
    • Design Top Cell Name—Displays the name of the design top cell name. This field cannot be edited.
    • Instance Name for Testbench—Specify the names of the instances to be used for the instance binding of the DUT. Separate the names by a space character.
      This field is disabled by default. It is enabled only when the Instance option is selected in the Design Top Configuration Mode field.
    • Configuration Information for Parts in Parallel to the Design Top—In this table, you can specify additional instance or cell bindings for unconfigured design parts in parallel to the DUT.
      If you want the binding information in a row to be added to the generated configuration file, click the Enable check box in that row.
      To move a row up or down, or to delete a row, right-click that row and choose an appropriate option.
  6. In the XRUN OPTIONS section, specify the additional xrun arguments in the xrun Options column of the xrun Arguments for Testbench table.
    If you want the xrun arguments specified in a row to be added to the xrunArgs file, click the Enable check box in that row.
    To move a row up or down, or to delete a row, right-click that row and choose an appropriate option.
  7. Click OK or Apply to save the setup.
    When you netlist the design or run the simulation in this mode, the specified xrun options are added to the xrunArgs file. The xrunArgs file along with the generated or specified SystemVerilog configuration file is then passed to xrun for the top-level verification of complete Systems on Chip (SoCs).

Benefits of Reusing an Advanced Testbench

Examples of Configurations Used in Simple Mode

Following are a few examples of custom SystemVerilog configurations that can be used in the Simple Mode:

Working with DSPF files

The Detailed Standard Parasitic Format files (DSPF files) contain the post-layout data, which includes the designed and parasitic devices in a design. These files are created using the parasitic extraction tools. Therefore, the content and format of each DSPF file is dependent on the extraction tool. To run simulations for designs containing devices represented by DSPF files, ADE Assembler needs to consider these components in a way different than the devices with schematic.

For more details, refer to the section Including DSPF files in the Setup in the Virtuoso ADE Assembler User guide.

Limitations of AMS UNL

The following are the limitations of AMS UNL:

The netlister generates text inputs like the following:

-makelib -specificunit "\InV\" inv.vhd -endlib

This works correctly in UNL.

If the entity name is not escaped (\\) while using -keepcase4use5x, it results in the following 5.x directory structure: library/InV/view

The netlister generates the textInputs file and looks like the following:

-makelib -specificunit "\InV\" inv.vhd -endlib

This does not work in UNL and results in following error:

xmvhdl_p: *W,SPUNFW: specific library unit was never processed 'InV'

It is recommended that you escape ( \ \ ) the entity name if you need to keep the case sensitivity intact for DFII usage with a mixed language (both Verilog and VHDL) use of cellviews. The xmvhdl compiler always converts the cell name to lower case while xmvlog is case sensitive so it may store the cell in a different 5x directory. This causes a problem since this can result in the VHDL information being stored in a different directory than the Verilog module. HED (and other DFII tools) will not be able to find the VHDL information in the same location as the Verilog information (it will be treated as a different cell).

Should an instance that is bound to a symbol view be netlisted in Spectre syntax (using spectre siminfo) or in Verilog syntax?

By default, if an instance in your design configuration is bound to a symbol view, the instance is considered digital, and hence netlisted in Verilog syntax.

If you want a specific instance to be considered analog, and netlisted in Spectre syntax using Spectre siminfo, do the following:

  1. Open your configuration in Hierarchy Editor.
  2. Choose View – Tree.
  3. Right-click the instance and choose Set Instance View – Spectre.

If you want all instances that are bound to a symbol view to be considered analog, do the following:

  1. Choose Simulation – Options – AMS Simulator.
    Th AMS Options form appears. for more informati, see Setting up AMS Options.
  2. Click the Netlister tab.
  3. Add symbol in the Netlist using spectre CDF simInfo field.

Netlisting of inherited connections

Inherited connections allow you to selectively override the global signals in your design. This allows you to use multiple power supplies in a single design. If you want to implement separate power supplies (analog and digital, for example, or +3 V and +5 V) in a hierarchical design, you can assign net expressions to those global signals whose defaults you might want to override. Then you can use netSet properties to specify the new values of the signals. For more information about inherited connections, see the Inherited Connections Flow Guide and the Virtuoso Inherited Connections Tutorial.

The netSet properties are netlisted as cds_net_set attributes and evaluated by the elaborator. For example, the following netSet properties

Property Value

vdd

3.3v!

xground

[@new_ground:%:gnd5!]

will be netlisted as:

(* 
integer cds_net_set
[0:1] = {"xground", "vdd"};
integer xground[0:1] = {"new_ground", "cds_globals.\\gnd5!" } ; 
integer vdd = "cds_globals.\\3.3v!" ;
*)

Important points to note:

Setting Up the AMS Netlister Options

Use the AMS template in Hierarchy Editor to create the configuration for your top-level design. To set the options required for using AMS UNL:

  1. Choose Simulation – Netlist and Run Options.
    The Netlist and Run Options form is displayed.
    The AMS Unified Netlisting with xrun option is selected by default when a new session is opened.
  2. In the Run Options section, specify the run options for the netlister.
    • Compile Incremental
      Select All to compile all modules.
    • Elaborate Incremental
      Select All to elaborate all modules.
    • Simulate
    • Clean snapshot and pak files
    • Compile VerilogA as Verilog-AMS
    • Enable AMS flexible release matrix
    • Spectre path
  3. In the Simulation Mode section:
    1. Select the simulation mode as Batch (normal) or Interactive (debugger)
    2. Select the Enable mixed signal debugger check box to view the SimVision debug environment for AMS simulator
      This option is available only if the Enable AMS flexible release matrix check box is selected.
    3. Select Enable cross selection to select an object in Schematic Editor and have the corresponding simulation object selected in SimVision, and vice versa.
  4. In the Design Capture section, select Enable design capture to trace the files that are accessed by a simulation and package them so that the same setup can be run in a different session.
  5. In the Explorer Save and Restart Options section, select Enable process based save and restart to enable the process-based save and restart flow.
  6. Select Enable save to enable the Save Options group box.
  7. In the Save Options section, specify the options for saving simulation snapshots.
    For more information, see Save Options.
  8. Select Enable restart to enable the Restart Options group box.
  9. In the Restart Options section, specify the options for restarting a simulation from the saved snapshots.
  10. Click OK.

Related Topics

Process-Based Save and Restart (PBSR) flow

Saving Simulation Snapshots at Different Time Points

Saving Simulation Snapshots Periodically

Restarting a Simulation from a Saved Snapshot

Netlist and Run Options Form

Process-Based Save and Restart (PBSR) flow

You can select Enable process based save restart in the Netlist and Run Options form to enable the Process- Based Save and Restart (PBSR) flow for Spectre AMS Designer simulation runs. This lets you save simulation snapshots during a transient analysis simulation run and later restart the simulation from a specific snapshot.

Saving simulation snapshots is especially useful for large simulations where you might want to save the simulation state at regular intervals.

This features lets you:

It is recommended to use the Batch simulation mode while using the PBSR flow. When you use this flow with the Interactive(debugger) simulation mode, AMS prints a statement in the probe.tcl file, as shown below, which pauses the interactive simulation at the SimVision MS console.

stop -create -time 40ns -absolute -execute "save snapshot_40n -overwrite" -continue

If you specify any additional save commands or restart point other than the ones specified in the Netlist and Run Options form, it leads to an unsupported state of the PBSR database.

Saving Simulation Snapshots at Different Time Points

To save simulation snapshots at different time points:

  1. In the Explorer Save and Restart Options section of the Netlist and Run Options form, select Time points.
  2. Specify a prefix for snapshot names in the Snapshot prefix field.
  3. In the Save time points field, specify the time points at which the snapshots must be saved.
    Note the following:
    • Do not use spaces between the time and the unit of time. The default unit of time is seconds.
    • Multiple values must be separated by blank spaces.
    • To save a snapshot for a time point with a unique name, specify the time point in the following format:
      (timePoint snapShotName)
      For example, if you specify the time point as (50n my50nSnapShot), a snapshot named my50nSnapShot is saved at 50n.
  4. In the Save increment field, specify the time interval at which the snapshots must be saved. In Start time and Stop time, specify the respective time points at which the snapshots must start and stop.
    For example, let us consider the following setup.
    In this case, the following four snapshots are saved at 20n, 40n, 50n and 60n.
    • snap_20n
    • snap_40n
    • my50nSnapShot
    • snap_60n

    No snapshot is saved at 65n because after 40n, snapshots are saved only at intervals of 10n
    Do not use spaces between the specified value of time and the unit. The default unit is seconds.
  5. Click OK.
  6. Run a simulation.

Related Topics

Process-Based Save and Restart (PBSR) flow

Saving Simulation Snapshots Periodically

Pre-requisites for Restarting a simulation from a Saved Snapshot

Netlist and Run Options Form

Saving Simulation Snapshots Periodically

To save simulation snapshots periodically:

  1. In the Explorer Save and Restart Options section of the Netlist and Run Options form, select Periodic snapshot.
  2. Specify the base name for the snapshot in the Snapshot base name field.
  3. In the Strobe time field, specify the time interval between saving snapshots.
  4. Select one of the following options to specify the number of snapshots to be saved for each simulation run.
    • Max Number
    • All
  5. Specify the time unit to be used in the Snapshot name time unit field.
  6. Click OK.
  7. Run a simulation.

Related Topics

Process-Based Save and Restart (PBSR) flow

Saving Simulation Snapshots at Different Time Points

Pre-requisites for Restarting a simulation from a Saved Snapshot

Netlist and Run Options Form

Pre-requisites for Restarting a simulation from a Saved Snapshot

You can restart a simulation from an existing snapshot if it meets one of the following criteria:

Restarting a Simulation from a Saved Snapshot

To restart a simulation from a saved snapshot

  1. Select the Enable Restart check box in the Netlist and Run Options form to enable the Restart Options group box.
    The fields Test name and history display the name of the test and the last history associated with the current maestro session, respectively. These fields are not editable.
  2. From the Snapshot name drop-down list, select the snapshot from which you want to restart the simulation.
  3. Click OK.
  4. Run a simulation.

When the simulation completes, a waveform from time 0 to the specified stop time is displayed. This waveform is plotted even if the simulation was started from a later snapshot, and the snapshots were saved during different simulation runs.

Related Topics

Process-Based Save and Restart (PBSR) flow

Saving Simulation Snapshots at Different Time Points

Saving Simulation Snapshots Periodically

Netlist and Run Options Form

Netlist and Run Options Form

The Netlist and Run Options form lets you specify the options required for using AMS UNL.

Field Description

Netlist and Run Mode

Specifies whether you have Xcelium or INCISIVE in your installation path.

AMS Unified Netlister with xrun

Opens the AMS UNL documentation in the Doc Assistant.

The options displayed in the form depend on the installation path. If you have Xcelium in the installation path, Xcelium commands, such as xrun are displayed. If your installation path has INCISIVE, INCISIVE commands, such as irun are displayed.

In case the AMSXLMCOMPATIBLE environment variable is set, INCISIVE commands are displayed in the form even if you have Xcelium in your installation path.

Run Options

Specifies the run options.

Compile Incremental

Compiles just the modules that have been edited since the last compilation.

All

Compiles all modules.

Elaborate Incremental

Elabortaes just the modules that have been edited since the last elaboration.

All

Elaborates all Models.

Simulate

Simulates the design.

Note the following:

  • You can choose to only compile, elaborate or simulate the design, although by default all three are selected.
    For example, if you select only Elaborate, the Simulation – Netlist command only elaborates the design. Compilation and elaboration can be incremental or for the whole design together.
  • A simulation will fail if you choose both Compile and Simulate. You would need to either deselect Simulate or select Elaborate as well.

Clean snapshot and pak files

Deletes any existing simulation snapshot and .pak files before running the simulation.

This option is available for the xrun run mode only.

Compile VerilogA as Verilog-AMS

Indicates that the AMS simulator should compile VerilogA as Verilog-AMS.

This option is available for the xrun run mode only.

On selecting the Netlist using Spectre check box is selected in the AMS Options form, this option gets disabled.

Enable AMS flexible release matrix

Enables the AMS flex flow.

This check box is greyed out and selected automatically with Xcelium 21.02 or a higher release version.

Spectre path

Specifies the path to the Spectre version to be used with AMS flex flow. This lets you use different versions of Spectre for the Xcelium build you are using.

This option is available only when Enable AMS flexible release matrix is selected.

Simulation Mode

Specifies the simulation options.

Simulate

Specifies the simulation mode.

  • Batch (normal): Plots signals in Virtuoso Visualization and Analysis XL.
    This is the default mode.
  • Interactive (debugger): Launches the complete SimVision MS debug environment on top of the current design.
    When this mode is selected, set the DISPLAY shell environment variable in the hostname:portNumber format so that the SimVision environment window is displayed. To ensure that the variable has the value in the correct format, set the addHostNameToDisplayPort environment variable to t.
    When the host mode is set to distributed, the radio button for interactive mode is disabled and batch mode is enabled (only if Interactive mode was selected before).

Enable mixed signal debugger

Displays the SimVision MS debug environment for AMS simulator.

Cadence recommends that you enable the process-based save restart flow through this check box instead of specifying the option -process_save as an additional argument.

This option is available only if the Enable AMS flexible release matrix check box is selected.

Enable cross selection

Lets you select an object in Schematic Editor and have the corresponding simulation object selected in SimVision, and vice versa. This helps in debugging design errors.

Design Capture

Specifies the options for the Design Capture utility.

Enable design capture

Traces the files that are accessed by a simulation and packages them so that the same setup can be run in a different session.

This feature can be used only when:

  • The Batch (normal) simulation mode is selected
  • The settings in the Explorer and Restart Options group box are not being used
  • The settings in the Run Options group box required to compile, elaborate, and simulate the design are selected

Explorer Save and Restart Options

Specifies the save and restart options for ADE Explorer.

When you switch to ADE Assembler, the name of this section changes to Assembler Save and Restart Options.

Enable process based save and restart

Enables the process-based save and restart flow that lets you save the entire simulation setup, and facilitates a smoother restart operation, so that the future simulations can continue from that point.

While restarting the simulation from a saved setup, the following points must be kept in mind:

  • The circuit topology cannot be changed.
  • The product versions used while creating the saved setup must not be altered while restarting the simulation.

Enable save

Enables the Save Options group box.

Save Options

Specifies the options for saving simulation snapshots.

Save mode

Specifies the mode for saving simulation snapshots.

  • Time points: Saves the snapshots at specific time points.
  • Periodic snapshot: Saves the snapshots periodically.
  • HDL save: Represents the system function $save that can be used in the Verilog, Verilog-AMS, and SystemVerilog modules. This enables you to set up the process-based save and restart operation in relation to the design or testbench events specified in the Verilog code.
    Ensure that the HDL save check box is selected when saving a snapshot using $save in a vams file

Snapshot prefix

Specifies the prefix for the snapshot name.

For example, if you specify the prefix as mySnap, snapshots are saved with names such as mySnap_40n, where 40n indicates the timepoint at which the snapshot was saved.

The default prefix is snapshot.

Save time points

Specifies the time points at which snapshots need to be saved.

Note the following:

  • Do not use spaces between the time and the unit of time. The default unit of time is seconds.
  • Multiple values must be separated by blank spaces.
  • To save a snapshot for a time point with a unique name, specify the time point in the following format:
    (timePoint snapShotName)
    For example, if you specify the time point as (50n my50nSnapShot), a snapshot named my50nSnapShot is saved for time point 50n.

Save increment

Specifies the time interval at which the snapshots must be saved.

Start Time

Specifies the starting time point for the snapshots to be taken.

The default unit of time is seconds. Ensure that you do not use spaces between the time and the unit.

Stop Time

Specifies the stopping time point for the snapshots to be taken.

Do not use spaces between the time and the unit. The default unit of time is seconds.

Snapshot base name

Specifies the base name for the snapshot.

The snapshot base name must be alphanumeric with no spaces, underscores, or special characters.

Strobe time

Specifies the time interval between saving snapshots. It can be a numerical value, followed by the unit or a percentage value.

On adding a percentage value, the time interval between saving snapshots is then calculated as the specified percentage of the value of time given in the Stop Time field. The value for this field can be specified in the Choosing Analyses form for transient analysis.

For example, on specifying the stop time as 1u and strobe time as 15%, the equivalent strobe time would be 150n.

Do not use spaces between the time and the unit of time. The default unit is seconds.

Snapshots per run

Specifies the number of snapshots to be saved in one simulation run.

  • Max Number: Lets you specify the maximum number of snapshots to be saved in one simulation run.
    For example, if the value for the Max Number field is set to 4, Strobe time is 20n, and the Snapshot name time unit is us, the screenshots are saved as follows:
    mySnapShot1run1
    mySnapShot1run2
    mySnapShot1run3
    mySnapShot1run4
    The specified number is applicable only if the All option is deselected.
  • All: Specifies that the all the snapshots taken during the time interval specified in the Strobe time field must be saved.

Snapshot name time unit

Specifies the time unit to be used in the snapshot name.

For example, if you specify the strobe time as 0.25u, and the stop time as 1u, a screenshot named mySnapShot_250_NS_run1 is saved.

The changes made to this field are applicable only if the Save all snapshots check box is selected.

Enable restart

Enables the Restart Options group box.

When this check box is selected, the Compile incremental and Elaborate incremental fields are disabled because netlisting, compilation and elaboration are disabled when you restart simulation from a saved snapshot. This ensures that existing snapshots are not overwritten.

Restart Options

Specifies the restart options.

Test name

Displays the name of the test for which the Netlist and Run Options form is opened.

This is not an editable field.

History name

Displays the name of the last history associated with the current maestro session.

In ADE Assembler, this field displays the history select through the Reference Histories form.

This is not an editable field.

Snapshot name

Lets you select the snapshot from which the simulation is to be restarted.

Add

Lets you add the select snapshot to the Snapshot Sweep Information table.

This button is available only when ADE Assembler is used.

Snapshot Sweep Information

Displays the information for the selected snapshots in tabular format.

This table is available only when ADE Assembler is used.

It has the following columns:

  • Enable: Enables or disables the entry for a snapshot.
  • Test: Specifies the name of the test associated with the given snapshot.
  • History: Displays the name of the history associated with the given snapshot.
  • Snapshot: Displays the name of the selected snapshot.
  • tclFile: Lets you specify a Tcl file for the given snapshot.

Related Topics

Setting Up the AMS Netlister Options

Process-Based Save and Restart (PBSR) flow

Saving Simulation Snapshots at Different Time Points

Saving Simulation Snapshots Periodically

Restarting a Simulation from a Saved Snapshot

Simulating the Design Using the xrun Command

AMS UNL supports simulation using the xrun command of the Spectre AMS Designer and Xcelium Mixed-Signal simulator.

The xrun command compiles text using a file extension parser. For example, files with the .v extension are compiled using the xmvlog Verilog compiler, files with the .vhd extension are compiled using the xmvhdl VHDL compiler, and files with the .vams extension are compiled using the xmvlog Verilog compiler with the -ams argument. After the input files are compiled, xrun automatically starts xmelab to elaborate the design and then uses xmsim to simulate the design. For more information about the xrun command, see the Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide.

You need to install XCELIUM 17.10 s007 or a later release to use the xrun command with the AMS UNL flow.

You can specify the options for running xrun using the AMS Options form.

Netlist and Run Command

The Netlist and Run command generates the xrun command using the options specified in the AMS Options form.

After running the Netlist and Run command, you can view the log file named xrun.log using, Simulation – Output Log – xrun Log. All the errors generated for the compiler, elaborator and AMS Designer simulator can be viewed in this log file.

When you run simulation using AMS UNL, the xrun.log file contains hyperlinks to various components for better interaction with the design. You can use these hyperlinks to open the AMS Options form, Simulation Files Setup form, IE Setup form, Hierarchy Editor, and various .vams output files. To disable these hyperlinks from appearing in the xrun.log file, set the UNL_HYPERLINK_LOG environment variable to NO in CIW.

Refer to the following figures to know the available hyperlinks and their functions:

Debugging Verilog-A Instances in AVUM flow

To debug verilog instances in AVUM flow, perform the following steps.

  1. In the Netlist and Run Options form:
    1. Select Compile Verilog-A as Verilog-AMS in the RUN OPTIONS group box
    2. Set the simulation mode to Interactive(debugger)
    3. Select Enable mixed signal debugger
  2. In the AMS Options form, select Read from the Access visibility drop-down list.
  3. Run a simulation.
  4. In the SimVision Design Browser, select the Verilog-A instance you want to plot.

You can then use the SimVision MS to create a TCL probe and plot the instances.

Related Topics

How to probe and debug Verilog-A variables, nets, ports using Tcl in AVUM flow (AMS Designer in ADE flow)

Saving or Plotting Selected Voltages or Currents for AMS Simulation

For AMS simulation, you can use the schematic window to select the nodes or terminals for instances that have a schematic view.

You can use the Hierarchy Editor to select the nodes or terminals for instances:

To specify the nodes and terminals for an instance, which has a schematic view, to be saved or plotted, do the folowing:

  1. Choose Outputs – To Be Saved – Select On Design.
  2. Choose Outputs – To Be Plotted – Select On Design.
    The Schematic window appears.
    If the top-level design is a text design, the Choose an instance to descend form appears instead of the Schematic window. Select an instance in the list and click OK to open the schematic for the instance. You can also double-click an instance to open the schematic.
  3. In the Schematic window, choose one or more nodes or terminals.
    The system circles pins when you choose a current and highlights wires when you choose a net.
    • Click an instance to choose all instance terminals.
    • Click the square pin symbols to choose currents.
    • Click wires to choose voltages.
    • Click and drag to choose voltages by area.
  4. Press the Esc key when you are done.
    Your selections are added in the Outputs list in the simulation window.

To specify the nodes and terminals for an instance, which has a text view, to be saved or plotted, do the folowing:

  1. Choose Outputs – To Be Saved – Select From HED
  2. Choose Outputs – To Be Plotted – Select From HED.
    The Hierarchy Editor appears displaying the instances in the tree view.
    You can select nodes and terminals for instances only in the tree view in Hierarchy Editor. If you are in the table view in Hierarchy Editor, you cannot select nodes and terminals for instances.
  3. Click the instance with the text view.
    In the above figure, instance I3 is selected in Hierarchy Editor.
    The Select Net/Term to Save/Plot form appears.
  4. Do one of the following:
    • Select net to save or plot voltage.
    • Select term to save or plot current.
  5. Select the node or terminal for the instance from the Choose net/term cyclic field.
    You can click the View button to view the module for the instance in a text editor.
    The terminals of a primitive instance will not be displayed in the Choose net/term cyclic field because primitive instances do not have a text view. You can enter the terminal name in the Enter net/term field using the format:
    I3/Y
    Where /I3 is the full instance name and Y is the terminal name.
  6. Do one of the following:
    • Click Apply to add the node or terminal in the Outputs list in the simulation window. Select another net or term for the current instance, or perform steps 3 to 5 to select a net or term for another instance.
    • Click OK to close the Select Net/Term to Save/Plot form and add the node or terminal in the Outputs list in the simulation window.

    If you click OK or Cancel and then want to select nodes or terminals from Hierarchy Editor, you must again choose Outputs – To Be Saved – Select From HED or Outputs – To Be Plotted – Select From HED in ADE Explorer.
    In flex mode, -amsformat is ignored. The default waveform format is a unified database with analog data in PSFXL 1.1 format and digital data in SST2 format. To change the waveform format for analog users, use the rawfmt Spectre option or the -format Spectre command-line argument. In such cases, unified database is disabled and the results will be stored in two different files, one for analog results using the specified Spectre format and one for digital data in SST2 format.

    When you enable the flex mode without PSF XL as the output format, you see a message as follows:
    AMSD flex flow is enabled but the recommended PSF XL unified database format is not enabled.
    The message box offers the following choices:
    • Change the output format to PSF XL. In this case, click Yes.
    • Run the AMSD flex flow with the current output format. In this case, click No.

Adding a Node or Terminal to a Set

To add a node or terminal to the saved or plotted sets:

  1. Choose Outputs – To Be – Select On Design commands in the Simulation window.
  2. In the Schematic window, choose one or more nodes or terminals.
    The system circles pins when you choose a current and highlights wires when you choose a net.
    • Click the square pin symbols to choose currents.
    • Click wires to choose voltages.
    • Click and drag to choose voltages by area.
  3. Press the Esc key when you finish.

To select nodes and terminals in lower-level schematics to be plotted or saved,

  1. In the Simulation window, choose Outputs – To Be – Select On Design.
  2. In the Schematic window, choose Design – Hierarchy – Descend Edit and click an instance.
  3. Click OK in the form that appears.
  4. In the Schematic window, choose one or more nodes or terminals.
  5. Press the Esc key when you finish.

DSPF-in-the-Middle Flow for AMS Simulations

The DSPF-in-the-middle flow allows the use of a digital module inside DSPF and speeds up mixed-signal post-layout simulation. This enables running verification in the early stages.

To enable the DSPF-in-the-middle flow for ADE Explorer or ADE Assembler, select Using HED Config for DSPF Blackbox in the Simulation Files Setup form for AMS simulator. AMS UNL then generates the required files and adds the option -ams_dspf_bbox in the xrunArgs file to enable this feature on the simulator side.

Related Topics

Using DSPF-in-the-Middle

Using the runams Command

The runams command provides command-line support for netlisting the design using the  AMS Unified Netlister (AMS UNL) and running simulations using xrun in batch mode.

By default, the AMS Unified Netlisting with xrun option is selected as the default netlisting choice when a new ADE session is opened. To enable OSS-based netlister as the default choice, specify the following in the .cdsinit file:

If you wish to force the choice of netlister to UNL when loading an existing ADE state with OSS-based setting, specify the following:

envSetVal( "ams.envOpts" "forceUnlOverOSS" 'boolean t)

To make the netlister mode UI read only, specify the following:

envSetVal( "ams.envOpts" "disableNetlisterModeUI" 'boolean t)

runams will read and honor CDS environment variables to invoke the intended netlisting flow.

OCEAN also allows you to netlist and simulate from the command-line. However, runams provides a much simpler use model using command-line options.

The runams command for AMS UNL capability is available in IC 6.1.6 ISR6, and later versions.

The runams command syntax is given below:

runams [-help | -h | -version | -V | -W | -usage] 
| runams -lib libName -cell cellName -view viewName 
  action_options [setup_options] [netlisting_options] [simulation_options]

Use the following command to view information about all the options available in the runams command:

runams -help

Use the following command to view detailed information about each option available in the runams command:

runams -help optionName

Use the following command to view important information you must know when using runams options:

runams -usage

See the following topics for more information about the runams command:

runams Command Options

The following table describes the runams command options and values.

runams Option and Value Description

-h | -help

Displays the description of the runams command and its options.

-h optionName

Displays the detailed description for an option.

-V | -version

Displasy runams version information.

-W

Displays runams subversion information.

-usage

Displays important information you must know when using runams options. For more information, see How to Use runams Options.

-nocdsinit

Skips reading the .cdsinit file.

-lib libName

Specifies the library containing the configuration that you want to netlist.

-cell cellName

Specifies the cell containing the configuration that you want to netlist.

-view viewName

Specifies the cellview name of the configuration that you want to netlist. The view name can also be a cellview state.

-testname testName

Specifies the name of the test to be used from the given maestro view. If not specified, the first test from that maestro view is used.

-spectre_path spectreDirectoryPath

Specifies the path to the Spectre binary.

Action Options

-netlist

Runs the AMS UNL netlister in the specified mode. Default: incremental

incremental

Generates netlists for new or changed cellviews only.

This is the default netlisting mode.

all

Netlists all cellviews in the configuration, whether they have changed since the previous netlisting or not. This is equivalent to Simulation – Netlist – Recreate in ADE L.

If an option effects netlisting changes (for example one of the -netlisteropts), use -netlist all to renetlist the design.

skip

Skips netlisting the design.

Ensure that the netlist is simulatable when you select this mode.

-simulate

Runs simulation (xrun) in the specified mode.

Default: batch

If the simulation mode has been specified through both the options, -state and -simulate, the mode specified through the -simulate option will be used to run the simulation.

batch

Runs xrun in the batch mode. This mode, which does not allow you to interact with the simulator, usually simulates more quickly than the gui mode.

This is the default simulation mode.

gui

Opens the SimVision analysis environment graphical interface that allows you to interact with the simulator using buttons, menus, and Tcl commands.

-savescripts

Saves the runSimulation file in the runDir/netlist directory, but don't simulate.

-clean

Deletes all simulation snapshot files before running simulation. This will run the xrun -clean command to remove the INCA_libs directory under the runDir/netlist directory.

-forcecheck

Enables an in-memory check for schematic connectivity before proceeding to netlisting.

-plot

Invokes the waveform tool to plot the results in the ./runDir/psf directory when simulation is completed.

The waveform tool can be specified using the -wavetool command.

To use the SimVision interactive debugger, run the simulation using -simulate gui option.

If a Tcl file containing database commands is specified using the -tclinput option, ensure that the database -open command in the file is:

open -into ./runDir/psf

If an ADE state file is used, the results will be automatically written to the ./runDir/psf directory without the need to specify a separate Tcl file. If a Tcl file or a state file is not specified, xrun creates a directory named abc.tran.shm in the netlist directory, where abc is the name of the tran statement in the analogcontrol (scs) file. If the specified Tcl file does not have a database -open statement, xrun creates an .shm directory in the netlist directory, such as ncsim.shm. runams will detect this and invoke the waveform tool to plot the results in the abc.tran.shm or ncsim.shm directory.

Setup Options

-cdslib filePath

Specifies the cds.lib file to use.

If the -cdslib option is not specified, the standard Cadence search mechanism (CSF) is used to find the cds.lib file.

Relative paths are resolved with respect to the invocation directory.

-file filePath

Specifies a file that contains runams options.

Each line in the file can have one or more options. Lines in the file that are blank or begin with the comment character # are ignored. Line continuation character is not supported. For filePath, a relative path is resolved with respect to the invocation directory. For the options in the file, a relative path is resolved with respect to the file location.

-log logFileName

Writes output log messages to logFileName. Default: ./runams.log

The logFileName that you specify with this variable interacts with the CDS_LOG_PATH environment variable to determine the log file name that is used. Ensure that the directory specified in the CDS_LOG_PATH environment variable exists.

  • If logFileName is an absolute path, the log file is written to logFileName.
  • If logFileName is a relative path and
    • CDS_LOG_PATH is null, logFileName is placed in the current directory.
    • CDS_LOG_PATH is non-null, the value of CDS_LOG_PATH is prefixed to the logFileName.
  • The CDS_LOG_VERSION environment variable also affects the final name of the log file.

-rundir runDir

Specifies the run directory path to use.
Default: ./libName-cellName-viewName

A netlist directory (where netlisting and simulation are run) and a psf directory (where the results are written) will be created under runDir.

Relative paths are resolved with respect to the invocation directory.

-resultsdir resultsDir

Specifies the results directory path to use.

By default, simulation results are written to the runDir/psf directory. If this option is specified, the simulation results will be written to the resultsDir/psf directory. If both -resultsdir and -tclinput are specified, ensure that the same results directory path is specified for resultsDir/psf and the database -open command in the Tcl file specified using the -tclinput option.

-cdsenv filePath

Specifies the .cdsenv file to use. This is the same .cdsenv file used by ADE.

Relative paths are resolved with respect to the invocation directory.

-cdsinit filePath

Specifies the .cdsinit file to use. This is the same .cdsinit file used by ADE.

Relative paths are resolved with respect to the invocation directory.

You can use the -cdsinit option to specify a file that contains the same settings as the Virtuoso .cdsinit file. For example, if you have a file, testpinchecker, you can specify the file with this option, as shown below:

runams -lib training -cell wx_ams -view maestro -rundir mydirsch -netlist all -testname training:wx_ams:1 -cdsinit testpinchecker

Here, testpinchecker contains the following:

aa = hnlRunPinChecker("WSM_pinCheck" "concatBusMM_tb" "config" ?checkAms t)
unless( aa
exit()
)

In this example, the runams command will run the Pin Checker before the AMS UNL netlisting starts through the runams -netlist option.

-state

stateLoadDir:stateName[:simulatorName]

Specifies the ADE state directory and state name to use.

The final path used to find the state file will be stateLoadDir/libName/cellName/simulatorName/stateName, where libName is the library name specified using the -lib option and cellName is the cell name specified using the -cell option. By default, simulatorName is ams. If simulatorName is specified to be something other than ams, the state for the specified simulator will be loaded for the ams run, and, as with ADE, the options in the state file that are not applicable to ams will be ignored.

Relative paths are resolved with respect to the invocation directory.

stateViewName

Specifies the ADE cellview state to use.

The state files are found in the libName/cellName/stateViewName directory, where libName is the library name specified using the -lib option and cellName is the cell name specified using the -cell option. Ensure that the stateViewName is for an ams state.

-switchto

Allows to specify a different design configuration for the current maestro view.

For example, by using the following setting, you can switch the design configuration file for a test, mylib:mycell:1 from mylib.mycell:config to mylib.mycell:config2.

-switchto mylib.mycell:config2

-wavetool

Specifies the waveform tool to use to plot the results.

Default: simvision

simvision

Uses the SimVision analysis environment to plot the results.

This is the default waveform tool.

viva

Uses the Virtuoso Visualization and Analysis tool to plot the results.

Netlisting Options

-desvar desVars

Specifies additional design variables, or override the value of design variables in the cds_globals.vams file.

The desVars argument is a colon-separated list of name-value pairs, such as name1=val1:name2=val2. During netlisting, information about design variables in the design are written to the cds_globals.vams file. During simulation, the cds_globals.vams file will be automatically sent to xrun.

Use the -desvar option to specify additional design variables you want to add in the cds_globals.vams file, or to specify design variables whose values you want to override in the cds_globals.vams file. This results in a new cds_globals.vams file that will be sent to xrun.

This option can be specified more than once. However, if the same design variable is specified in more than one -desvar statement, the value specified for that variable in the last -desvar statement will be used.

-globalsignals

Specifies a set of global signals, either in a file or as a list of signal names immediately following the option.

sigName[=netType[=netDiscipiline[=isGround]]]

Specifies additional global signals, or override the declaration of design variables in the cds_globals.vams file.

During netlisting, information about global signals in the design are written to the cds_globals.vams file. During simulation, the cds_globals.vams file will be automatically sent to xrun.

Use the -globalsignals option to specify additional global signals you want to add in the cds_globals.vams file, or to specify global signals whose declarations you want to override in the cds_globals.vams file. This results in a new cds_globals.vams file that will be sent to xrun.

The option sigName is mandatory. If netType is not specified, wire will be used. If netDiscipline is not specified, electrical will be used. If isGround is not specified, NO will be used. Use single quotes to enclose the values.

Example: 

-globalsignals 'VDD50! VSS50! VDD30!=wire=electrical=NO VSS30!=wire=electrical=YES'.

This option can be specified more than once. However, if the same global signal is specified in more than one -globalsignals statement, the arguments specified for that signal in the last -globalsignals statement will be used.

sigFile

Specifies the file containing global signal names, each name on its own line in the file.

Each line in the file must be in the format: sigName[=netType[=netDiscipiline[=isGround]]].

Use single quotes to enclose the values. The signals will be placed in the cds_globals.vams file that was created during netlisting, and the resulting new cds_globals.vams file will be sent to xrun.

Example: 

'VDD50! VSS50! VDD30!=wire=electrical=NO VSS30!=wire=electrical=YES'.

-netlisteropts ‘option1:option2‘

Specifies AMS UNL options. The options argument is a colon-separated list of name-value pairs enclosed in single quotes, such as:

-netlisteropts 'amsPortConnectionByNameOrOrder=name:useSpectreInfo=spectre veriloga spice'.

The following netlister options can be set using the
-netlisteropts command:

  • amsPortConnectionByNameOrOrder=name |order
Specify how to print the port connection. Default: name).
  • useSpectreInfo
Specify the list of views that are to be netlisted as spectre. The default is "spectre veriloga spice". You may need to add symbol to this list if you want symbol views to be netlisted as spectre.

This option can be specified more than once. However, if different values are specified for an argument in more than one -netlisteropts statement, the value specified for that argument in the last
-netlisteropts statement will be used.

-portdrill

Enables the port drilling feature for runams. Valid values for this option are all, except_top, and no.

Default: all.

Simulation Options

-solver

Specifies the analog solver to use.

Default: spectre

spectre

Specifies that the Spectre solver is to be used.

This is the default option.

ultrasim

Specifies that the UltraSim solver is to be used.

-analogsolver

Lets you specify a host for Spectre.

Examples:

Runs Spectre on the local host. You can also use a script or a resource scheduler, provided it boots Spectre.

runams -analogsolver "spectre"

Runs Spectre on a remote host.

runams -analogsolver "bsub -R \"OSNAME==Linux &7 OSREL==EE70 && SFIPLATFORM==c0700\" -n 1 -q lnx64 -J spectre"

-amscontrol filePath

Specifies the ams control file to use. Typically this file contains the ams control block. The filePath argument is passed to the simulator.

-analogcontrol filePath

Specifies the analog simulation control file to be used. This file contains the spectre, ultrasim or aps control statements, such as the tran, info or options statements.

The filePath argument is passed to the simulator.

-cdsglobals fileName

Specifies a file that includes the cds_globals module definition.

The cds_globals module declares design variables and global signals. The specified fileName will be sent to xrun.

The cds_globals.vams file that is created during netlisting will not be sent to xrun. The fileName argument is passed to the simulator.

-connectrules

Specifies the built-in and user-defined connect rules to use.

This option can be specified more than once.

[libName.]ruleName[:viewName]

Specifies the built-in connect rule to use in the library.cell:view format, such as:

-connectrules connectLib.connRule_5v_full:connect

userDef:[ruleName][:fileName]

Specifies the user-defined connect rule to use in the rulename:filename format, such as:

-connectrules userDef:connRule_5v_full:/path/file1

The ruleName and fileName are passed to the simulator.

This option can be specified more than once.

-iecard filePath

Specifies the path to an ie_card.scs file that contains information about how the connect rules are used during simulation.

-discipline disciplineName

Specifies the default discipline for digital nets for which a discipline is either not specified or cannot be determined through discipline resolution.

If -discipline is not specified, -discipline logic will be printed in the runSimulation file. Use -discipline none to disable printing of -discipline logic in the runSimulation file.

-f filePath

Specifies the files containing xrun command-line options to be passed as the argument to the xrun -f command.  The filePath argument is a colon-separated list of file paths, such as:

-f filePath1:filePath2

The filePath argument is passed to the simulator.

This option can be specified more than once.

-hdlvar filePath

Specifies the name of the hdl.var file to use.

The filePath argument is passed to the simulator.

-incdir path

Specifies the directory to search for `include files. The path argument is a colon-separated list of directory paths, such as:

-incdir path1:path2

The path argument is passed to the simulator.

This option can be specified more than once.

-irunopts options

Specifies additional xrun command-line options, such as:

-irunopts '-iereport +dr_info'

Use single quotes to enclose the command-line options. These command-line options are passed as is to xrun.

xrun is run in the runDir/netlist directory. Therefore, all paths must be absolute or relative to the netlist directory.

-modelfile modelFiles

Specifies the analog model files and section name. The modelFiles argument is a colon-separated list of files with model section names enclosed in parentheses, such as:

-modelfile 'file1:file2(NN)'

Use single quotes to enclose the value when section names of a model are specified. The modelFiles argument is passed to the simulator.

This option can be specified more than once.

-path path

Specifies the model include directories setup. This is equivalent to the xrun -modelincdir option. The path argument is a colon-separated list of directory paths, such as:

-path path1:path2

The path argument is passed to the simulator.

This option can be specified more than once.

-reportinvalidbinding

Stops the simulation with an error message when an invalid binding is found in an HED view. This option provides the same functionality as the environment variable AMS_UNL_INVALID_BINDING_ACTION.

-tclinput filePath

Specifies a Tcl file to use.

The Tcl file normally contains the database -open command and the probe statements that specify nets and terminals to save for plotting, although any Tcl command that xrun accepts can be specified in the Tcl file.

The database -open command in the Tcl file must open the results database in ./runDir/psf, as this is the directory that will be passed to the waveform tool by the -plot option. The filePath argument is passed to the simulator.

-v filePath

Specifies the Verilog files to be passed as the argument to the xrun -v command.

The filePath argument is a colon-separated list of file paths, such as:

-v filePath1:filePath2

The filePath argument is passed to the simulator.

This option can be specified more than once.

-y path

Specifies the directories to be passed as the argument to the xrun -y command.

The path argument is a colon-separated list of directory paths, such as:

-y path1:path2

The path argument is passed to the simulator.

This option can be specified more than once.

IP Export Options

-export

Enables the Virtuoso IP export reuse flow. The generated export files are placed in the directory specified through the -rundir option

- testbenchtopcell topCellName

Specifies the design library and cell names to be used for System Verilog Configuration File generation.

- iplabel labelName

Specifies the label name to be used for.amsbind.scs file generation.

- v2001configname configName

Specifies the configuration name to be used for System Verilog Configuration File generation

-ipencrypt

Enables encryption for the exported IP. Valid values for this option are yes, no.

-iplabelAddOnLib

Adds the specified IP label name as the prefix to the Virtuoso library name.

-iphierpathtoiptopcell

Specifies the hierarchy path from the top cell to the current IP.

-ipselectsimopt

Specifies the simulation options to be printed in the argument file xrunArgs.

all

Prints all the simulation options to the argument file.

modelsetup

Prints the model file settings to the argument file.

perfsetup

Prints the simulation options from the High Performance Simulation Options form.

iesetup

Prints the IE Card settings from the Interface Element (IE) Setup form.

analogctrlfile

Prints the analog control files.

For example, amsControlSpectre.scs

Note the following:

Relative paths specified using the ~ or . characters will be resolved with respect to the invocation directory (the directory in which you ran the runams command).

How to Use runams Options

This section describes important information you must know when using runams options.

  1. If -help,-version, -V, -W or -usage is specified with other options, those options will be ignored.
  2. To run simulation, you must specify the -cdsenv, -state or -analogcontrol option, or use a cellview state with the -view option.
  3. If -clean is specified without -simulate or -savescripts, the xrun -clean command is run to remove the INCA_libs directory in the netlist directory.
  4. Only the following options can be specified more than once. If other options are specified more than once, the value specified for the last instance of those options will be used.
    -file -desvar -globalsignals -netlisteropts -connectrules -f -incdir -path -modelfile -irunopts -v -y
    For -desvar, if the same design variable is specified in more than one -desvar statement, the value specified for that variable in the last -desvar statement will be used.
    For -globalsignals, if the same global signal is specified in more than one -globalsignals statement, the arguments specified for that signal in the last -globalsignals statement will be used.
    For -netlisteropts, if different values are specified for an argument in more than one -netlisteropts statement, the value specified for that argument in the last -netlisteropts statement will be used.
    If -connectrules, -f, -incdir, -path, -modelfile, -v and -y are specified more than once, the values specified for all instances of the options be used.
  5. If -file option is specified, the options in the file will be appended after other command-line options. Then the rules specified in point 4 above are used to process all the options. For example, the cmdFile file includes:
    "-view config -path path2 -desvar var1=2:var2=3
    and you specify:
    runams -lib lib -cell cell -view view -netlist -desvar var1=1 -path path1 -file cmdFile"
    This is like using:
    runams -lib lib -cell cell -view view -netlist -desvar var1=1 -path path1 -view config -path path2 -desvar var1=2:var2=3
    As per the rules in point 4 above, these commands will be applied as:
    runams -lib lib -cell cell -view config -netlist -path path1:path2 -desvar var1=2:var2=3
  6. If the -lib, -cell and -view options point to a cellview state, runams will first get topLib.topCell:topView from the cellview state, then run runams -lib topLib -cell topCell -view topView -state state_view_name. If the -state option is also specified, runams will ignore the -state option.
  7. If an option is specified in both the .cdsenv file and an ADE state, the option in the ADE state has precedence. However, any option specified in the .cdsenv, that does not have a GUI /state equivalent, will be used from the .cdsenv file.
  8. If -state, -cdsenv, and -analogcontrol or -tclinput are specified, runams reads the .cdsenv file first and reads the state files next. The files specified using the -analogcontrol or -tclinput options will be used instead of the files that would have been created by the state file.
  9. If you specify the -cdsenv and the -analogcontrol options, but do not specify the -state option, the file specified using -analogcontrol option is used. runams will not use the file specified using the -cdsenv option to generate the analog control, Tcl or runSimulation file, but the settings that affect netlisting in the .cdsenv file will take effect during netlisting.
  10. If conflicts occur between the options specified by -irunopts, command-line options and the options in the .cdsenv or a state file, the options specified by -irunopts take precedence, then command-line options, then the options in the .cdsenv or a state file. For example, if there is a conflict in the values specified for the -solver option in the command-line and in the .cdsenv or a state file, the values specified in the command-line options will be used.

runams Command Examples

Viewing the Output Log for AMS

You can view the output logs (netlister.log and xrun.log) from the Simulation – Output Log submenu. Choose Output Log – LogFile Utility to launch the XMBrowse message browser.

You can analyze log files with the XMBrowse utility. The XMBrowse utility lets you select a log file message and view the source code that caused the message. It includes sorting and filtering tools that let you view only those messages that are important to you. You can also use the message browser to print formatted output reports. To know more about the XMBrowse utility, refer to the XM Browse Message Browser User Guide.

Similarly, choose the Netlister Log, Compiler Log, Elaborator Log, Simulator Log, 3-step Log or xrun Log options to view the respective logs in the Results Browser.

Viewing the Error Explanation for AMS

You can view detailed explanation of the error for AMS in the Error Explanation form. Choose Simulation – Output Log – Error Explanation to launch the Error Explanation form.

All the error messages that are present in the log files that are created in the psf directory while a session is being run are listed in the All Error Messages field. To view details about an error message, you can select the Error from All Error Messages field and then click the Explain button. The description for the error appears as shown in the figure above.

You can also enter the error in the Error Message field. If you enter a string, it will be treated as an error string. If you enter two strings, the first string is treated as the tool name and the second string is treated as an error message. If you enter more than two strings, you will get a warning.

The error message description consists of the following:

For all error names, the xmhelp for that error name is printed.

Using the SimVision Debugger

You can set AMS netlister  and simulation run options by choosing Simulation – Netlist and Run Options. This brings up the Netlister And Run Options form.

You can choose to only compile, elaborate or simulate the design, although by default all three are selected as shown in the screenshot. For example, if you select only Elaborate, the Simulation – Netlist command only elaborates the design. Compilation and elaboration can be incremental or for the whole design together. A simulation would fail if you choose both Compile and Simulate. You would need to either deselect Simulate or select Elaborate as well.

The Batch mode is the default mode. In this mode, all signal plotting occurs in the default analog waveform plotting tool– Virtuoso Visualization and Analysis XL.

The Interactive mode launches the complete SimVision debug environment interactively on top of the current design. SimVision is a graphical user interface for Cadence digital and mixed-signal simulators and related full digital debugging tool suite.

Direct Plot and plotting from the Calculator or browser go to the selected waveform tool, regardless of the run mode or whether or not SimVision is up.

ADE Explorer sends Tcl commands to SimVision for the simulation run and to plot the signals listed in the outputs pane. This mode lets you control xmsim and simvision from the console window.

The ADE Explorer window displays the selected mode on the status bar as highlighted in this snapshot.

Note the following:

Setting Up a Cross Selection Menu to Launch the Post Simulation Analysis Form

By default, the Virtuoso Schematic Editor does not have a SimVision menu. To add it to the toolbar, select Launch – Plugins – Mixed Signal Options – SimVision.

In the SimVision menu, click Cross Selection. The Post Simulation Analysis form is displayed.

You can specify the following information in the form. Click the browse button next to a field to select the input data:

Field Description

Cell View

Specify the top-level design cellview.

Simulation Directory

Specify the path of the simulation database.

SimVision Database

Specify the path and filename of the SimVision database .trn file.

Hierarchy Prefix

This field includes the hierarchy prefix used in the testbench, such as test.top or test:top.

You can use a period (.) or a colon (:) as the delimiter in the hierarchy prefix.

Additionally, you can use the following check boxes to migrate from the Virtuoso Schematic Editor to the Virtuoso Verilog Environment for NC-Verilog and vica-versa.

Display Partition

Once you elaborate a design or run a simulation, you can view your data and distinguish between analog instances or nets, digital/real instances or nets, and mixed instances or nets by the color associated with each partition.

  1. To access this feature, choose Launch – Plugins – Mixed Signal Options – AMS in your schematic window. The AMS option appears on the menu bar.
  2. Choose AMS – Display Partition – Initialize. If you choose the Initialize menu item after running a simulation in ADE Explorer, the Display Partition menu items are enabled.
    However, if you do not run the simulation, the Choose PSF Directory form is displayed, as shown below. On this form, type the path to the simulation data directory in the PSF Directory field, or select the results using the Browse button.
  3. Choose AMS – Display Partition – Interactive to view the Partition Display window.
    This feature highlights the analog, digital, and real parts of a schematic in different colors.
    analog indicates that the net or instance is analog in nature. A net or instance is analog throughout a hierarchy if everything under that instance is analog.
    digital indicates that the net or instance is digital in nature. A net or instance is digital throughout a hierarchy if everything under that instance is digital.
    real indicates that the net or instance is wreal in nature. A net or instance is real throughout a hierarchy if everything under that instance is real.
    analog/mixed indicates that the net is mixed in nature. It means that some segments of the net or instance are analog and some are digital in the hierarchy.
    digital/mixed indicates the same as analog/mixed, the difference being that at the current level, the net is digital.
    real/mixed indicates the net is wreal and connecting to R2E, or the instance has both wreal and electrical inside.
    digital/rmixed indicates the net is a logic net connecting to R2L, and R2L is connected to wreal net.
    real/rmixed indicates the net is wreal net connecting to R2L, or the instance has both wreal and logic inside.
    real/mixed/rmixed indicates the net is wreal net connecting to both R2L and R2E, or the instance has wreal,electrical and logic nets inside.
    The schematic reflects these color preferences.
  4. You can see all the IEs in the configuration by choosing AMS – Display Partition – IE Information. This brings up the AMS CMs Display dialog box displaying all IEs.
    You can select an IE and click Go to to see it zoomed-in on the schematic.

Default Digital Discipline Selection

Disciplines denote an object’s domain scope as being electrical or analog (with an electrical discipline, for example) or digital (with a logic discipline, for example). You can define the default disciplines for design objects by using the AMS – Default Digital Discipline Selection command in the Composer window.

This option affects the settings only on the CR/CM setup form and not the IE card setup form.

Default digital discipline selection indirectly controls the selection of a connect module (IE) on mixed domain nets. A discipline denotes an object as analog or digital based on whether it is assigned the electrical or logic type discipline, respectively. When objects of different domains/disciplines are connected, connect rules help determine which connect modules are inserted between the mixed nets/ports.

The inserted connect modules then convert signals to values that are appropriate for each discipline. To customize the conversions for your design, you can use the connect rules to override parameters, such as supply voltage or rise time, that are used in the connect modules.

For more information, see the Mixed-Signal Aspects of Verilog-AMS chapter of the Cadence Verilog-AMS Language Reference.

To specify a default digital discipline for design objects,

  1. Choose Launch – Plugin – Mixed Signal Options – AMS in your schematic window.
    The AMS menu appears on the menu bar.
  2. Choose AMS – Default Digital Discipline Selection.
    A submenu appears showing six options: Library, Cell, Cell Terminal, Net, Instance, Instance Terminal.
  3. Select any of the submenu options to bring up the Default Digital Discipline Selection form. For example, if you select Library, the form comes up as shown here. You can specify disciplines on libraries in this form.
    Alternatively, you can select any of the other options from the Specify discipline on group box. The fields below the Discipline field change as follows depending on the design object selected.
    Design Object Related fields How to specify

    Library

    Library

    Type in a valid value or use the Browse button to specify a library from the Library Browser.

    Cell

    Library
    Cell

    Type in valid values or use the Browse button to specify a library and cell from the Library Browser.

    Cell Terminal

    Library
    Cell
    Terminal

    Type in valid values or use the Select button to select a cell terminal from the schematic.

    Net

    Net

    Type in a valid value or use the Select button to select a net from the schematic.

    Instance

    Instance

    Type in a valid value or use the Select button to select an instance from the schematic.

    Instance Terminal

    Instance Terminal

    Type in a valid value or use the Select button to select an instance terminal from the schematic.
  4. The table lists the types of design objects, their default disciplines, and their names. You can sort this table by Type or Discipline.
  5. To create a new discipline,
    1. Click the Discipline button.
      The Create Discrete Disciplines form appears in which you can create a discipline. The new discipline appears in the Discipline field.
    2. Click the Add button.
  6. To delete one or more disciplines specified on an object,
    1. Select one or more rows in the table.
    2. Click the Delete button.
  7. To change a discipline specified on an object,
    1. Select a row in the table.
      The form refreshes to show the fields pertaining to the selected kind of object.
    2. Change the values as required and click the Change button.
  8. To view a discipline on the schematic,
    1. Select a row from the table.
      Only nets, instances and instance terminals can be highlighted.
    2. Click the Highlight button.
      As shown in the illustration below, the selected discipline, in this case logic_1p2, appears highlighted in the schematic. You can select and highlight multiple objects this way. You can click the Unhighlight All button to remove the highlights.
  9. To copy disciplines from the cellview, click the Copy from Cellview button. Conversely, to copy disciplines from the form to the cellview, click the Copy to Cellview button.
    After copying over disciplines from a cellview, when you click the Discipline button, a form may pop up listing the disciplines that have not been defined and asking if you would like to define them. If you select Yes, the Create Discrete Disciplines form appears showing a list of the undefined disciplines. If you select No, it appears blank.
  10. You can specify connect rules for a selected discipline by using the Connect Rules button to bring up the Select Connect Rules form. You can use this form to create, modify or delete connect rules. This form appears only if ADE Explorer is up and the simulator set to ams. Otherwise, an error message appears.
  11. Click OK.
    The disciplines created are automatically compiled.

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