Product Documentation
Virtuoso Schematic Editor User Guide
Product Version IC23.1, November 2023

10

Checking Designs

This chapter describes the procedures you use for checking your design.

Features of the Check Commands

Before you can pass the design data to any other tools, you must check your design for connectivity, errors, and rule violations.

By default, the connectivity of a design is updated automatically as you create and edit the design. For more details, see Updating Connectivity.

The Cadence netlisters cannot generate the netlist until you check your design and, if necessary, correct any errors found during the check process.

You do not need to correct any warnings found during the check process, but you must review them before you attempt to generate a netlist.

The check commands are as follows:

You can check schematics using the following commands.

Highlighting Errors and Warnings in the CIW

You can use the following environment variables to control whether or not the CIW is raised to the front of other windows to display any errors or warnings that have been issued.

ui raiseCIWonError boolean t/nil
ui raiseCIWonWarning boolean t/nil

Setting the Check Options

Before you run the check commands, you can set options and rules using the following commands:

Check and Check Rules Setup are accessible from both the Options menu and the Check menu.

Setting User Preferences

To set user preferences,

  1. From the schematic window, choose Options – Check.
    The Schematic Check Options form appears.
  2. Specify the options you want to apply to your check.
  3. Click OK.

Setting Schematic Rule Checks

The Schematic Rules Checks form lets you set the rules for running the SRC. Once you set these rules and SRC is enabled on the Schematic Check Options form, you can use any one of the following Check commands to run SRC checks: File – Check and Save, Check – Current Cellview, and Check – Hierarchy.

To set the rules for running the SRC,

  1. From the schematic window, choose Check – Rules Setup.
    The Schematic Rules Checks Setup form appears.
  2. Set the Packaged Checks cyclic field to a specified predefined check.
    The items listed in the Packaged Checks cyclic field are defined by the schSRCPackagedChecks environment variable. Packaged checks are a means of setting a set of severities using a single selection.
  3. Set the severity levels for the following rules:
    • Logical checks the high-level connectivity data
    • Physical checks for unconnected wires, offset labels, and overlapping instances
    • Name checks for syntax and collisions for the Cadence VHDL verification tool or the Verilog®-XL simulator
    • Inherited Connection checks existing or missing inherited connections
    • Constraints checks constraints (for example, mismatched parameters)
    • Signal Type checks input, output and I/O pins
    • RF Implementation checks transmission lines
    • Coloring checks the CDF colors
    • (optional) Custom Checks lets you create your own custom check tabs and associated rules checks
  4. Click OK.
    Used to create and register a new schematic rule checker.

Logical Checks

For more information see the Schematic Rules Checks Setup.

Physical Checks

For more information see the Schematic Rules Checks Setup.

Name Checks

For more information see Schematic Rules Checks Setup.

The following specifics apply to this form:

Use of Regular Expressions for Schematic Rules Checks

Only one regular expression is allowed when setting the Instance Name Expression, Pin Name Expression or Net Name Expression fields.

It is also recommended that you describe the allowed syntax, and negate it with an "!" at the front so that you can specify any exception as a violation.

For example, the following regular expression allows only names that start with an alpha character, and are followed by any occurrence of an alphanumeric character or an underscore, and end with an alphanumeric character, an underscore, or an exclamation mark:

      !^[A-Za-z][A-Za-z0-9_]*[A-Za-z0-9_!]$
Further information on regular expression syntax can be found in the public domain.

Inherited Connections Checks

For more information see the Schematic Rules Checks Setup.

Constraints Checks

Constraints functionality is only available in Virtuoso Schematic Editor XL. For more information on Constraints, see the Virtuoso Unified Custom Constraints User Guide.

Mismatched Parameters

The Constraints tab on the Schematic Rules Checks Setup can be set to check for Mismatched Parameters.

If you set Constraints Checks to yes, the constraints rules checker will test devices that are members of the matchedParameters constraint, confirming, or not, that the parameter has the same value on the devices.

You can choose to check for a mismatched parameter warning or error, or to have this check ignored.

As the Virtuoso Schematic Editor allows parameters to be edited, this Mismatched Parameters check acts as a check as to whether these edits may invalidate a matchedParameters constraint. This will therefore help guard against mismatched parameters impacting simulations or layouts.

The Virtuoso Schematic Editor checker (see Checking and Saving a Design), being cellview based, can be run on either the current cellview or through the design hierarchy. The Mismatched Parameters check looks at all members (that is, all the various cellviews), but only reports violations, by adding markers, on the check cellview. Any cellview that exhibits failure markers will cross-highlight to the appropriate matchedParameters constraint in the Constraint Manager when selected, allowing you to identify other failed devices across cellviews.

Therefore, on each invocation of the schematic checker, all constraint views will be examined for matched parameters, but markers will only be added to the edit cellview.

The hierarchical checker (see Checking a Design Hierarchy) can also be used to add markers to multiple cellviews from a single command.

Signal Types Checks

For more information see the Schematic Rules Checks Setup.

The Signal Type tab has three sub-tabs (Input pins, Output pins, and I/O pins) that contain the same Net Signal Type and Pin Signal Type options. These tabs are grayed out unless the Signal Type Checks checkbox option is selected.

Optical Checks (Virtuoso Photonics Option)

Virtuoso Photonics Solution - You need the Virtuoso_Photonics_Option license to use the functionality discussed in this section. For information about obtaining the required license, contact your local Cadence representative.

The optical checks are controlled by the options on the Optical tab of the Check – Rules Setup – Schematic Rules Checks Setup form. The severity can be updated as carried out for the other signal types.

A connection between an optical net and electrical net results in an error.

Optical nets must have only two connections. Multi mode nets or outputs should not connect to single mode inputs or nets. Conversely, single mode nets or outputs can connect to multi mode inputs or nets.

RF Implementation (Virtuoso RF Solution Option)

For more information see the Schematic Rules Checks Setup and RF Transmission Lines.

Coloring

For more information see the Schematic Rules Checks Setup.

Creating Custom Checks

You can create your own custom check tabs (see Example of How to Create a Custom Check Tab) and associated rules checks, for use within the Schematic Rules Checks Setup form, using the following SKILL functions:

Example of How to Create a Custom Check Tab

The following is an example of how to create a customized tab in the Schematic Rules Checks Setup form:

procedure(CustomCheckCB(cellView ruleObject)
  let(((msg "The gate of instance \"%s\" is connected to a high voltage net."))
    foreach(instance cellView->instances
      ;; Perform checks on instance and report failures...
      schReportCheckFailure(
        ?object    instance
        ?checkRule ruleObject
        ?message   sprintf(nil msg instance->name)
      )
    )
  )
)
procedure(ConfigCheckCB(groupName checkName)
  hiDisplayAppDBox(
    ?name       'ConfigCheckDialogBox
    ?dboxBanner "Configure Custom Check"
    ?dboxText   sprintf(nil "Configure the %L check from the %L tab..." checkName groupName)
  )
)
schRegisterCheckGroup(
  ?name  'CustomChecks
  ?title "Custom"
)
schRegisterCheckRule(
  ?title       "No HV on Gate of Thin Oxide MOS Tx"
  ?name        'CustomNoThinOxideMOSTxGateHV
  ?groupName   'CustomChecks
  ?checkCB     'CustomCheckCB
  ?configCB    'ConfigCheckCB
  ?description "The gate should not have a direct or indirect path to a high voltage net"
)

Checking a Design

There are two modes in which the connectivity of a design is updated: incremental and batch.

Incremental connectivity mode is the default mode. The connectivity in a schematic design is updated automatically as you create and edit a design. Batch connectivity mode is also available.

Regardless of the connectivity mode used, before you can pass the design data to any other tools, you must check your design for connectivity, errors, and rule violations.

You have several options for checking a design:

Related Topics

Updating Connectivity

Checking and Saving a Design

The File – Check and Save command does the following:

To check and save either a schematic or symbol,

  1. From the view, choose File – Check and Save.
    After the check is completed, the Command Interpreter Window (CIW) shows the results of the check, and a dialog box appears.
    Flashing highlighted markers in your schematic indicate the objects that have errors or warnings.
  2. On the dialog box, click Close.
    The Cadence netlisters cannot generate the netlist until you check the design and, if necessary, correct any errors found during the check process.
    You do not need to correct any warnings found during the check process, but you should review them before you attempt to generate a netlist.
    If no errors exist, your design is automatically saved.
    If errors exist, you are prompted to save the cellview. You can change this default behavior by altering the value of the Check and Save Action on Error option on the Schematic Check Options.
  3. Read the check results and reply to the form.
    To find the errors, choose Check – Find Marker.
    If the input and output terminals of a device are connected, the Check and Save option returns a warning message in the CIW. However, if the input and output terminals of a device are connected to the noConn device, the Check and Save option does not give any warning message.

Using the Progress Bar to Measure Processing State

As an aid to establishing the current processing state for a number of specific tasks, a Progress Bar is displayed in the bottom right corner of the VSE status bar.

The Progress Bar will be displayed when processing the following actions:

Checking the Current Cellview

The Check – Current Cellview command does the following:

Before checking a cellview, review the check options.

To check only the current cellview,

  1. From the schematic window, choose Check – Current Cellview.
    The software performs the check. After the check is completed, the CIW displays the results of the check, and a dialog box appears.
  2. Read the check results and reply to the form.
  3. Choose Check – Find Marker to view and resolve each error, if applicable.
    See also Using the Progress Bar to Measure Processing State.
You can register a function to be called before or after a schematic is checked using the SKILL functions schRegPreCheckTrigger or schRegPostCheckTrigger.

Checking a Design Hierarchy

If the design is not opened in the context of a configuration, viewNameList will be used for hierarchy traversal, and pc.db would be used for text views.

See also Using the Progress Bar to Measure Processing State.

The Check – Hierarchy command does the following:

Before checking a hierarchy, review the check options.

To check all schematics in a design hierarchy,

  1. From the schematic window, choose Check – Hierarchy.
    The Check Hierarchy form appears.
    The appearance of this form is different when the schematic is in the context of a design configuration or a hierarchy configuration.
  2. Set the options for your particular needs.
  3. Click OK.
    The system runs the SRC, VIC, and any options you specified on the Schematic Check Options form or Schematic Rules Checks Setup form.

If errors are found, they are listed in the CIW.

If you have errors, the Save Schematics with Errors form appears.

To save time, you can check only those cellviews that have not been checked since the last time you saved your cellview. To customize the view name list, refer to the schCycleViewNameExclusionList variable.

You can register a function to be called before or after a schematic is checked using the SKILL functions schRegPreCheckTrigger or schRegPostCheckTrigger.

Checking a Design Hierarchy in the Configuration Context

If you open a schematic in the context of a hierarchy configuration (configured schematic), the Check – Hierarchy command does not use the view name list. Instead, the command uses the schematic associated with its configuration data through partitioning. Partitioning is the process of separating the cells or blocks of a design into sets that will be simulated in either the digital or analog domain. Refer to “Partitioning Your Design” in Virtuoso Analog Design Environment L User Guide.

If you are checking a hierarchy in the design configuration context, the Check Configuration Hierarchy form appears, and the View Name List field is replaced with two fields that display the configuration name and the name of the top-level cellview.

Checking Multisheet Schematics

To check the current sheet of a multisheet schematic,

To check all the cellviews of a design hierarchy,

To check all sheets of a multisheet schematic,

The offsheet connector check used in multisheet schematics performs the following operations:

Whenever a multisheet schematic is checked using the Check – Current Cellview or File – Check and Save command, an msymbol cellview is created or updated.

Checking a Label Attachment

To highlight the association between a label and its owning object (that is, a wire or an instance):

  1. From the schematic window, choose Check – Label Attachment.
    The Check Label Attachment form appears.
  2. Select which labels that you want to check as being attached to particular objects. Choose from wire, instance, both, or none.
    The system will now apply a highlighted line between the displayed label text and its associated object. A flashing box appears around any labels not attached.
  3. When required, select Close to close the form and remove all label attachments from the canvas.
    This action will also reset the selection to none.

Cross-View Checking

You can check symbols using the Check – Cross View command. It provides the following capabilities:

Checks if supply sensitivity of terminals matches. To check only the interconnection consistency between views,

  1. From the symbol window, choose Check – Cross View.
    The Cross-View Checker form appears.
  2. Specify the options you want to apply to the check.
  3. Click OK.
  4. View your errors or warnings.
    When the check completes,
    • A Cross-View Checker dialog box displays the number of errors and warnings found in the symbol.
    • The software displays blinking highlighted markers in your symbol to indicate the objects with errors or warnings.
    • The CIW displays a one-line explanation of each error and warning.
  5. Click Close.
  6. Choose Check – Find Marker to view and resolve each object error.

Checking Expanded and Unexpanded Buses Across Views

The cross-view checker flags mismatches of expanded and unexpanded buses in symbol and schematic cellviews. If, for example, you place input pins in the schematic editor for bus A as A<1>, A<2>, and A<3>, but in the symbol cellview you unexpand the bus as A<3:1>, cross-view checker issues the following warning message:

Warning: Pin "A<3>" doesn't have an exact match in "cell1 symbol"

To correct this warning, set up the environment variable as follows:

schSetEnv("vicExactPinMatch" nil)

Alternatively, deselect the Match Pin Names Exactly option in the Cross-View Checker form to avoid displayng the warning.

Ignoring Explicitly Inherited Terminals for Text Cellviews

The Cross-View Checker form lets you ignore explicitly inherited terminals for text cellviews, such as functional, systemverilog, verilogams, or symbol cellviews.

For example, consider that you have a cell cellA and it has three views, schematic, symbol, and SystemVerilog.

Here,  

To ignore inherited terminals:

  1. From the schematic window, open the Cross-View checker form.
  2. Select Match Inherited Terminals.
  3. Select Ignore Terminals with Net Expression and no Terminals in the Other View.
  4. Specify a text view type in the View Names field. For example, specify the functional view.
  5. Select the Terminal Names option and specify the name of the terminal in the adjacent field.
  6. Click OK.
  7. Open the view in the Text Editor window and click Check and Save.

The inherited terminals are matched while the explicitly inherited terminals with pin mismatches are ignored for the specified cellviews.

Checking Read-Only Cellviews

The functionality of checking read-only cellviews is available only in Virtuoso Schematic Editor XL.

You can check a schematic or symbol when the cellview is opened in read-only mode. While checking, the temporary markers are placed on the canvas and the files are not checked out in your Design Management system. The error and warning messages are written to the log file. You can only examine a cellview in read-only mode and cannot do any further changes or corrections unless it is editable.

Select one of the following options in the Check Hierarchy to specify the mode for opening cellview during the checks:

You can also use the checkHierOpenMode environment variable to specify the mode in which the cellview is opened for hierarchy checks.

Bypassing Checks

Besides changing check options to ignored, you can bypass floating pin checks and unconnected wire checks.

Bypassing Floating Pin Checks

There are two methods you can use to bypass the floating pin check:

To attach the noConn symbol to unconnected terminals,

  1. From the schematic window, choose Create – Instance.
    The Add Instance form appears.
  2. In the Library field, type basic.
  3. In the Cell field, type noConn. The noConn symbol is attached to the pointer.
  4. Click to place the noConn symbol to an unconnected terminal.
    SRC does not highlight the dangling terminal as an error.

Bypassing Unconnected Wire Checks

There are two methods you can use to bypass the unconnected wire check:

To connect the onPageConn symbol to the wire vertex,

  1. From the schematic window, choose Create – Instance.
    The Add Instance form appears.
  2. Click Browse.
    The appropriate browser appears.
  3. Select the onPageConn symbol from the basic library.
    The onPageConn symbol is attached to the pointer.
  4. Click to place the onPageConn symbol to a wire vertex.
    SRC does not highlight the dangling wire as an error.

Drawing a Custom noConn Symbol

A custom noConn symbol must contain two specific cellview properties, both with the property type string. To define these properties, do the following:

  1. Without anything selected in Virtuoso, type geQuerySelSet() in the CIW.
    The Cellview Property Editor form appears.
  2. Click Add.
    The Add Property form appears.
  3. Add the following string type properties:
    • "nlAction" = "ignore"

    • "schType" = "border"

  4. Draw the custom noConn symbol, ensuring it has exactly one pin named noConn.
    The custom noConn symbol is created.

Resolving Check Errors

When a check command results in errors or warnings,  a flashing highlighted marker is displayed on each object that generated an error or warning.

If your design has errors or warnings, the Check – Find Marker command lets you view them by listing the corresponding error and warning messages in the Find Marker form.

You can use the Find Marker form to narrow your search by limiting the list box display to a particular severity level. You can also use the Find Marker form to expand your search by expanding the scope.

For more information on the connectivity error messages issued, see Troubleshooting Schematic Connectivity.

This section provides information about the following:

Related Topics

Connectivity and Naming Conventions

Troubleshooting Schematic Connectivity

Finding Errors and Warnings in a Design

To search for error markers in your design after you run one of the Check commands,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
    The list box displays a list of all the error and warning messages generated by the check. By default, the first message and the associated marker are highlighted in the design window.
  2. Click the Next and Previous buttons to navigate through the message list.
    If you selected the Zoom To Markers button, the schematic editor zooms in on each associated marker and highlights the marker in the design window.

Mapping an Error Message to a Marker

To find the message that corresponds to a specific marker in the design window,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
  2. Click the flashing marker in the schematic cellview.
    The corresponding message is highlighted in the Find Marker list box.

Managing the Error Message List

After you run a check operation, you can use the Find Marker form to assign an ignoreCheck property to a net, an instance, or an instance terminal in your design. The ignoreCheck property operates in conjunction with the Show Ignored option on the Find Marker form. When you assign the ignoreCheck property to an object and also turn off the Show Ignored option, the software suppresses the display, in the Find Marker form list box, of error and warning messages associated with the object when the following checks are run:

Assigning an ignoreCheck Property

To assign an ignoreCheck property to a net, an instance, or an instance terminal,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
  2. Click the message in the list box.
  3. Click the Ignore button.
    The software assigns an ignoreCheck property to the object and displays an asterisk next to the message in the column in the list box.

Suppressing Message Displays

To suppress the display of all messages that have an ignoreCheck property,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
  2. Turn off the Show Ignored option.
    All the messages that have an ignoreCheck property disappear from the list box.

Deleting an ignoreCheck Property

To delete an ignoreCheck property from an object,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
  2. Turn on the Show Ignored option.
    The list box displays all error and warning messages.
  3. Click an error or a warning message in the list box.
  4. Click the Restore button.
    The software removes the ignoreCheck property and deletes the asterisk from the message in the list box.

Deleting All ignoreCheck Properties

To delete all ignoreCheck properties from all objects,

  1. From the view, choose Check – Find Marker.
    The Find Marker form is displayed.
  2. Turn on the Show Ignored option.
    The list box displays all error and warning messages.
  3. Click the Restore button.
    The software removes all the ignoreCheck properties and deletes the asterisks from the messages in the list box.

Deleting Individual Markers

To delete individual markers in the design window,

  1. From the view, choose Check – Delete Marker.
  2. Click the marker you want to delete.
    You can also choose the Find – Marker command and click the Delete button at the top of the form to delete the current marker.

Deleting All Markers

To find and delete all the markers of a particular severity level, and in a particular cellview or hierarchy,

  1. From the view, choose Check – Delete All Markers.
    The Delete All Markers - OpenAccess version form appears.
  2. Select the Severity types, Search Scope, and the Sources.
  3. In the Options section, select the Cellview Access Mode.
  4. Click OK.

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