Product Documentation
Spectre Classic Simulator, Spectre APS, Spectre X, Spectre XPS, Spectre FMC Analysis, and Legato Reliability Solution User Guide
Product Version 23.1, September 2023

8

Spectre Netlists

This chapter discusses the following topics:

Netlist Statements

A Spectre® circuit simulator netlist describes the structure of circuits and subcircuits by listing components, the nodes that the components are connected to, the parameter values that are used to customize the components, and the analyses that you want to run on the circuit. You can use Verilog®-A to describe the behavior of new components that you can use in a netlist like built-in components. You can also define new components as a collection of existing components by using subcircuits.

A netlist consists of four types of statements:

Before you can create statements for a Spectre netlist, you must learn some basic syntax rules of the Spectre Netlist Language.

Netlist Conventions

These are the netlist conventions followed by the Spectre simulator.

Associated Reference Direction

The reference direction for the voltage is positive when the voltage of the + terminal is higher than the voltage of the – terminal. A positive current arrives through the + terminal and leaves through the – terminal.

Ground

Ground is a common reference point in an electrical circuit. The value of ground is zero.

Node

A node is an infinitesimal connection point. The voltage everywhere on a node is the same. According to Kirchhoff’s Current Law (also known as Kirchhoff’s Flow Law), the algebraic sum of all the flows out of a node at any instant is zero.

Basic Syntax Rules

The following syntax rules apply to all statements in the Spectre Netlist Language:

Spectre Language Modes

The Spectre netlist supports two language modes:

You can specify the language mode for subsequent statements by specifying simulator lang=mode, where mode is spectre or spice.

Spectre mode input is fully case sensitive. In contrast, except for letters in quoted strings, SPICE mode converts input characters to lowercase. You can specify insensitive=yes along with simulator lang=spectre to make the Spectre mode case insensitive.

Creating Component and Node Names

When you create node and component names in the Spectre simulator, follow these rules.

Multiple Namespace

From release 5.0.32 onwards, you need not have unique names for device instances, models, nets, subcircuit parameters, enumerated named values for parameters, and netlist parameters that are expressions. Consider the following example:

simulator lang=spectre
parameters c1=1p c2=2p c10=c1+c2
parameters res=10k
res c10 0 resistor r=res
c10 c10 0 capacitor c=c10
run dc
spectre2 options currents=all

res is used as a parameter and instance name. c10 is used as a node, instance, and parameter name. The Spectre circuit simulator can now read this netlist.

The Spectre circuit simulator can resolve ambiguous statements as shown in the example below:

parameters xyz=1
xyz 1 0 vsource dc=xyz
h1 3 0 ccvs probe=xyz rm=xyz

The Spectre circuit simulator assigns the instance xyz to probe and the parameter xyz to rm.

In the example below,

vcc vcc 0 vsource dc=1
save vcc

the Spectre circuit simulator saves the node vcc rather than the instance vcc. If you want to save the instance vcc, you must assign a different name to it.

Local NameSpace for subckt/model/verilogA

The Spectre circuit simulator supports local namespace for subckt/model/verilogA. The name is valid at the hierarchical level where it is defined and all levels below it. For subckt and model names, the namespace can be defined in the same netlist or in the included file. For verilogA, the namespace can only be invoked by the ahdl_include statement.

Example of model name: 

simulator lang=spectre 
vvdd vdd 0 vsource type=dc dc=1 
I1 vdd 0 cap1 
I2 vdd 0 cap2 
I3 vdd 0 cap3 
subckt cap1 a b 
m1 b a b b nch w=10u l=5u 
model nch bsim3v3 type=n mobmod=1 capmod=2 version=3.1 tox=9e-5 cdsc=1e-3 ends 
subckt cap2 a b 
m1 b a b b nch w=10u l=5u 
model nch bsim3v3 type=n mobmod=1 capmod=2 version=3.2 tox=6.5e-5 cdsc=3e-3 ends 
subckt cap3 a b 
m1 b a b b nch w=10u l=5u 
model nch bsim4 type=n mobmod=0 capmod=2 version=4.21 toxe=3e-9 cdsc=2.58e-4 ends

In the above example, the model name nch cannot be accessed from the top level.

Escaping Special Characters in Names

If you have old netlists that contain names that do not follow Spectre syntax rules, you might still be able to run these netlists with the Spectre simulator. The Spectre Netlist Language permits the following exceptions to its normal syntax rules to accommodate old netlists. Use these features only when necessary.

If you place a backslash (\) before any printable ASCII character, including spaces and tabs, you can include the character in a name.

You can create a name from the following elements in the order given:

A string of digits, followed by

This accommodates model or subcircuit libraries that use names like \2N2222.

Duplicate Specification of Parameters

If a parameter is specified more than once in the netlist, the Spectre circuit simulator uses the last specified value.

Instance Statements

In this section, you will learn to place individual components into your netlist and to assign parameter values for them.

Formatting the Instance Statement

To specify components, you use the instance statement. You format the instance statement as follows:

name [(]node1 ... nodeN[)] master [[param1=value1] ...[paramN=valueN]]

When you specify components with the instance statement, the fields have the following values:

name

The name you give to the statement. (Unlike SPICE instance names, the first character in Spectre instance names is not significant.)

[(]node1...nodeN[)]

The names you give to the nodes that connect to the component. You have the option of putting the node names in parentheses to improve the clarity of the netlist. (See the examples later in this chapter.) You can use the hierarchical operator . to represent nodes inside a subcircuit hierarchy in your netlist. The Spectre circuit simulator supports forward referencing (retaining information about a node that is not defined yet, and mapping it when the node is defined) and relative path referencing (accessing a node with reference to the current scope). Look for examples in the section below. The simulator does not support hierarchical terminals in netlists.

master

This is the name of one of the following:
A built-in primitive (such as resistor)
A model
A subcircuit
An AHDL module (Verilog-A language)

The instance statement is used to call subcircuits and refer to AHDL modules as well as to specify individual components. For more information about subcircuit calls, see “Subcircuits”. For more information about Verilog-A, see the Verilog-A Language Reference manual.

parameter1=value1...parameterN=valueN

This is an optional field you can repeat any number of times in an instance statement. You use it to specify parameter values for a component. Each parameter specification is an instance parameter, followed by an equal sign, followed by your value for the parameter. You can find a list of the available instance parameters for each component in the Spectre online help (spectre -h). As with node names, you can place optional parentheses around parameter specifications to improve the clarity of the netlist. For example, (c=10E-12).

For subcircuits and ahdl modules, the available instance parameters are defined in the definition of the subcircuit or AHDL module. In addition, all subcircuits have an implicit instance parameter m for defining multiplicity. For more details about m, see “Identical Components or Subcircuits in Parallel”.

Examples of Instance Statements

In this example, a capacitor named c1 connects to nodes 2 and 3 in the netlist. Its capacitance is 10E-12 Farads.

C1 (2 3) capacitor c=10E-12F

The following example specifies a component whose parameters are defined in a model statement. In this statement, npn is the name of the model defined in a model statement that contains the model parameter definitions; Q1 is the name of the component; and o1, i1, and b2 are the connecting nodes of the component.

Q1 (o1 i1 b2) npn
The model statement is described in Model Statements. You can specify additional parameters for an individual component in an instance statement that refers to a model statement. You can find a list of available instance parameters and a list of available model parameters for a component in the Spectre online help for that component (spectre -h).

Example of Forward Referencing in Hierarchical Nodes

simulator lang=spectre
...
c1 xa.mid 0 capacitor c=0.2p
...
xa 1 2 buffer

Example of Relative Path Referencing in Hierarchical Nodes

simulator lang=spectre
...
subckt wrapper a b

x1 a b res_in_series

rh x1.int1 x1.int2 resistor r=1

ends
x2 1 0 wrapper

Basic Instance Statement Rules

When you prepare netlists for the Spectre simulator, remember these basic rules:

Identical Components or Subcircuits in Parallel

If your circuit contains identical devices (or subcircuits) in parallel, you can specify this condition easily with the multiplication factor (m).

Specifying Identical Components in Parallel

If you specify an m value in an instance statement, it is as if m identical components are in parallel. For example, capacitances are multiplied by m, and resistances are divided by m. Remember the following rules when you use the multiplication factor:

Example of Using m to Specify Parallel Components

In the following example, a single instance statement specifies four 4000-Ohm resistors in parallel.

Ro    (d    c)    resistor      r=4k      m=4

The preceding statement is equivalent to

Ro    (d    c)    resistor      r=1k

Temperature Rise

The temperature rises from ambient. The trise parameter can be specified as a subcircuit parameter or a primitive parameter. The trise parameter has an accumulated effect for the subcircuit, the same as m has for parallel components.

subckt LoadOutput a b
r1 (a b) resistor r=50k
c1 (a b) capacitor c=2pF
ends LoadOutput
X1 (out 0) LoadOutput trise = 20  

Subcircuit Temperature

The temp parameter can be specified as a subcircuit parameter or a primitive parameter. The temp parameter overwrites all the other temperature values set in options or trise parameter. It is an exclusive effective temperature for a specified subcircuit.

subckt LoadOutput a b 
r1 (a b) resistor r=50k
c1 (a b) capacitor c=2pF 
xx1 (a  b) RCsub trise = 5   
ends LoadOutput 
subckt RCsub 1 2 
    rr1 (1 2) resistor r=10k
    cc1 (1 2) capacitor c=2pF
ends RCsub 
X1 (out 0) LoadOutput  temp  =  100

In the above example, Spectre simulates X1 with temperature at 100 celsius while X1.xx1 is simulated with a temperature at 105 celsius.

Specifying Subcircuits in Parallel

If you place a multiplication factor parameter in a subcircuit call, you model m copies of the subcircuit in parallel. For example, suppose you define the following subcircuit:

subckt LoadOutput a b
    r1 (a b) resistor r=50k
    c1 (a b) capacitor c=2pF
ends LoadOutput

If you place the following subcircuit call in your netlist, the Spectre simulator models five LoadOutput cells in parallel:

x1 (out 0) LoadOutput m=5

Analysis Statements

In this section, you will learn to place analyses into your netlist and to assign parameter values for them. For more information on analyses, see and the Spectre online help (spectre -h).

Basic Formatting of Analysis Statements

You format analysis statements in the same way you format component instance statements except that you usually do not put a list of nodes in analysis statements. You specify most analysis statements as follows:

Name [(]node1 ... nodeN[)] Analysis Type parameter=value

where

Name

The name you give to the analysis.

[(]node1 ... nodeN[)]

Names you give to the nodes that connect to the analysis. You have the option of putting the node names in parentheses to improve the clarity of the netlist. (See the examples later in this chapter.) For most analyses, you do not need to specify any nodes. You can use the hierarchical operator . to represent nodes inside a subcircuit hierarchy in your netlist. The Spectre circuit simulator supports forward referencing (retaining information about a node that is not defined yet, and mapping it when the node is defined) and relative path referencing (accessing a node with reference to the current scope). Look for examples in the section below. The simulator does not support hierarchical terminals in netlists.

Analysis Type

Spectre name of the type of analysis you want, such as ac, tran, or xf. You can find this name by referring to the topics list in the Spectre online help (spectre -h).

parameter=value

List of parameter values you specify for the analysis. You can specify values for any number of parameters. You can find parameter listings for an analysis by referring to the Spectre online help (spectre -h).
The noise, xf, pnoise, and pxf analyses let you specify nodes, p and n, which identify the output of the circuit. When you use this option, you should use the full analysis syntax as follows:
Name> [p n] Analysis Type parameter=value

If you do not specify the p and n terminals, you must specify the output with a probe component.

Examples of Analysis Statements

The following examples illustrate analysis statement syntax.

XferVsTemp xf start=0 stop=50 step=1 probe=Rload param=temp freq=1kHz

This statement specifies a transfer function analysis (xf) with the user-supplied name XferVsTemp. With all transfer functions computed to a probe component named Rload, it sweeps temperature from 0 to 50 degrees in 1-degree steps at frequency 1 kHz. (For long statements, you must place a backslash (\) at the end of the first line to let the statement continue on the second line.)

Sparams sp stop=0.3MHz lin=100 ports=[Pin Pout]

This statement requests an S-parameter analysis (sp) with the user-supplied name Sparams. A linear sweep starts at zero (the default) and continues to .3 MHz in 100 linear steps. The ports parameter defines the ports of the circuit; ports are numbered in the order given.

The following example statement demonstrates the proper format to specify optional output nodes (p n):

FindNoise (out gnd) noise start=1 stop=1MHz

Basic Analysis Rules

When you prepare netlists for the Spectre simulator, remember these basic analysis rules:

Control Statements

The Spectre simulator lets you place a sequence of control statements in the netlist. You can use the same control statement more than once. Spectre control statements are discussed throughout this manual. The following are control statements:

Formatting the Control Statement

Control statements often have the same format as analysis statements. Like analysis statements, many control statements must have unique names. These unique names let the Spectre simulator identify the control statement if there are error messages or other output associated with the control statement. You specify most control statements as follows:

Name Control Statement Type parameter=value

where

Name

Unique name you give to the control statement.

Control Statement Type    

Spectre name of the type of control statement you want, such as alter. You can find this name by referring to the topics list in the Spectre online help (spectre -h).

parameter=value

List of parameter values you specify for the control statement. You can specify values for any number of parameters. You can find parameter listings for a control statement by referring to the Spectre online help (spectre -h).

Examples of Control Statements

SetTemp alter param=temp value=27

The preceding example of an alter statement sets the temperature for the simulation to 27°C. The name for the alter statement is SetTemp, and the name of the control statement type is alter.

You cannot alter a device from one primitive type to another. For example,

inst1 (1 2) capacitor c=1pF
alterfail altergroup{
    inst1 (1 2) resistor r=1k
}

is illegal.

Another example of a control statement is the altergroup statement, which allows you to change the values of any modifiable device or netlist parameters for any analyses that follow. Within an alter group, you can specify parameter, instance, or model statements; the corresponding netlist parameters, instances, and models are updated when the altergroup statement is executed. These statements must be bound within braces. The opening brace is required at the end of the line defining the alter group. Alter groups cannot be nested or be instantiated inside subcircuits. Also, no topology changes are allowed to be specified in an alter group.

The following is the syntax of the altergroup statement:

Name altergroup ... {
netlist parameter statements ...

and/or

device instance statements ...

and/or

 model statements ...

and/or

 parameter statements ...
}

The following is an example of the altergroup statement:

v1 1 0 vsource dc=1
R1 1 0 Resistor R=1k
dc1 dc // this analysis uses a 1k resistance value
a1 altergroup {
    R1 1 0 Resistor R=5k
}
dc2 dc // this analysis uses a 5k value

Model Statements

model statements are designed to allow certain parameters, which are expected to be shared over many instances, to be given once. However, for any given component, it is predetermined which parameters can be given on model statements for that component.

This section gives a brief overview of the Spectre model statement. For a more detailed discussion on modeling issues (including parameterized models. expressions, subcircuits, and model binning), see Chapter 9, “Parameter Specification and Modeling Features”.

Formatting the model Statement

You format the model statement as follows:

model name master [param1=value1 ... [param2=value2 ]]

The fields have the following values:

model

The keyword model (.model is used for SPICE mode).

name

The name you give to the model.

master

The master name of the component, such as resistor, bjt, or tline. This field can also contain the name of an AHDL module.

parameter1=value1 ...<parameterN=valueN>

This is an optional field you can repeat any number of times in a model statement. Each parameter specification is a model parameter, followed by an equal sign, followed by the value of the parameter. You can find a list of the available model parameters for each component in the parameter listings of Spectre online help (spectre -h).

Creating a Model Alias

You can create an alias for a model as follows:

model alias_model original_model

alias_model

Alias for the model.

original_model

Model defined in the current scope.

For example, 

model res resistor r=1K
model alias_res res 
r1 (a b) alias_res

Creating an alias for a Subcircuit

You can also create an alias for a subcircuit (subckt) as follows:

model alias_subckt original_subckt

alias_subckt

Alias for the subcircuit.

original_subckt

Subcircuit defined in the current scope.

For example,

subckt sub a b
r1 (a b) r = 10k
ends
model alias_sub sub
x1 1 0 alias_sub

Examples of model Statements

The following examples give parameters for a tline model named tuner and a bjt model named NPNbjt.

model tuner tline f=1MHz alphac=9.102m dcr=105m 
model NPNbjt bjt type=npn bf=100 js=0.1fA
The backslash (\) is used as a continuation character in this lengthy model statement.
model NPNbjt2 bjt \
    type=npn is=3.38e-17 bf=205 nf=0.978 vaf=22 \
    ikf=2.05e-2 ise=0 ne=1.5 br=62 nr=1 var=2.2 isc=0 \
    nc=1.5 rb=115 re=1 rc=30.5 cje=1.08e-13 vje=0.995 \
    mje=0.46 tf=1e-11 xtf=1 itf=1.5e-2 cjc=2.2e-13 \
    vjc=0.42 mjc=0.22 xcjc=0.1 tr=4e-10 cjs=1.29e-13 \
    vjs=0.65 mjs=0.31 xtb=1.5 eg=1.232 xti=2.148 fc=0.875

The following example creates two instances of a bjt transistor model:

a1 (C B1 E S) NPNbjt
a2 (C B2 E S) NPNbjt2

Using analogmodel for Model Passing (analogmodel)

analogmodel is a reserved word in Spectre that allows you to bind an instance to different masters based on the value of a special instance parameter called modelname. An instance of analogmodel must have a parameter named modelname whose string value will be the name of the master this instance will be bound to. The value of modelname can be passed into subcircuits.

The analogmodel keyword is used by the Cadence Analog Design Environment to enable model name passing through the schematic hierarchy.

Sample Instance Statement

name [(]node1 ... nodeN[)] analogmodel modelname=mastername [[param1=value1] ...[paramN=valueN]]

name

Name of the statement or instance label.

[(]node1...nodeN[)]

Names of the nodes that connect to the component.

analogmodel

Special device name to indicate that this instance will have its master name specified by the value of the modelname parameter on the instance.

modelname

Parameter to specify the master of this instance indicated by mastername. The mastername must either be a valid string identifier or a netlist parameter that must resolve to a valid master name, a primitive, a model, a subckt, or an AHDL module.

param1 param2...

Parameter values for the component. Depending on the master type, these can either be device parameters or netlist parameters. It is optional to specify these parameter values.

Example

    //example spectre netlist to illustrate modelname parameter 
    simulator lang=spectre 
    parameters b="bottom" 
    include "VerilogAStuff.va" 
    topInst1 (out in) top 
    topInst2 (out in) analogmodel modelname="VAMaster" //VAMaster is defined in "VerilogAStuff.va" 
    topInst3 (out in) analogmodel modelname="resistor" //topInst3 binds to a primitive 
    topInst4 (out 0) analogmodel modelname="myOwnRes" //topInst4 binds to modelcard "myOwnRes" defined below
    v1 in 0 vsource dc=1
    model myOwnRes resistor r=100
    subckt top out in 
      parameters a="mid" 
      x1 (out in) analogmodel modelname=a //topInst1.x1 binds to "mid" 
    ends top 
    subckt mid out in 
      parameters c="low" 
      x1 (out in) analogmodel modelname=b //topInst1.x1.x1 binds to "bottom" 
      x2 (out in) analogmodel modelname=c //topInst1.x1.x1.x2 binds to "low" 
    ends mid 
    subckt low out in 
      x1 (out in) analogmodel modelname="bottom" //topInst1.x1.x1.x2.x1 binds to "bottom" 
    ends low 
    subckt bottom out in 
      x1 (out in) analogmodel modelname="resistor" //x1 binds to primitive "resistor"
    ends bottom 
    dc1 dc 
    //"VerilogAStuff.va" 
    include "constants.h" 
    include "discipline.h" 
    module VAMaster(n1, n2); 
    inout n1, n2; 
    electrical n1, n2; 
    parameter r=1k; 
      analog begin 
      I(n1, n2) <+ V(n1, n2)/r; 
      end 
    endmodule

Basic model Statement Rules

When you use the model statement,

Input Data from Multiple Files

If you want to use data from multiple files, use the include statement to insert new files. When the Spectre simulator reads the include statement in the netlist, it finds the new file, reads it, and then resumes reading the netlist file.

If you have older netlist files you want to incorporate into your new, larger netlist, the include statement is particularly helpful. Instead of creating a completely new netlist, you can use the include statement to insert your old files into the netlist at the location you want.

The Spectre simulator always assumes that the file being included is in SPICE language mode unless the extension of the filename is .scs.
The Spectre circuit simulator can also read compressed files included using the include or dspf_include statements. To add the file using the include statement, the file must be compressed using gzip (.gz extension) or bzip2 (.bz2 extension). To add a compressed file using the dspf_include statement, the file must be compressed using the gzip (.gz extension).

Syntax for Including Files

Including Verilog-A Modules

To include Verilog-A modules in your netlist, use the ahdl_include statement. The Spectre circuit simulator compiles the complete module during the initial simulation. The module is re-compiled during subsequent simulations only if it is modified. This may result in a performance improvement. If you are making frequent changes to the Verilog-A in your design, you can turn the one-step compilation off by using the following command:

setenv CDS_AHDLCMI_ENABLE NO

Including Digital Vector Files

You can add a digital vector text file to a Spectre netlist using the following statement

vec_include filename

For a SPICE netlist, use the following statement

.vec filename

For more information on the digital vector file refer to Appendix D, “Digital Vector File Format,”

Including Verilog Value Change Dump Files

You can add a Verilog Value Change Dump (VCD) or an Extended VCD (EVCD) file to a Spectre netlist using the following statements respectively

vcd_include vcd_filename vcd_signal_info
evcd_include evcd_filename evcd_signal_info

For a SPICE netlist, use the following statements

.vcd_include vcd_filename vcd_signal_info
.evcd_include evcd_filename evcd_signal_info

For more information on the digital vector file refer to Appendix E, “Verilog Value Change Dump Stimuli,”

Formatting the include Statement

You can use any of two formatting options for the include statement. When you want to use C preprocessor (CPP) macro-processing capabilities within your inserted file, use the second format (#include). These are the two format options:

include "filename"
#include "filename"

The first option (include) is performed by the Spectre simulator itself. The second option (#include) is performed by the CPP. You must use the #include option when you have macro substitution in the inserted file.

CPP is not supported in Spectre Direct.

Rules for Using the include Statement

Remember the following rules and guidelines when using the include statement:

There are two major differences between using #include and include:

Example of include Statement Use

In the following include statement example, the Spectre simulator reads initial program options and then inserts two files, cmos.mod and opamp.ckt. After reading these files, it returns to the original file and reads further data about power supplies.

// example of using include statement
global gnd vdd vss
simulator lang=spectre
parameters VDD=5
include "cmos.mod"
include "opamp.ckt"
// power supplies
Vdd   vdd   gnd   vsource dc=VDD
Vss   vss   gnd   vsource dc=-VDD

Reading Piecewise Linear (PWL) Vector Values from a File

You could type the following component description into a netlist:

v4 in 0  vsource  type=pwl wave=[0 0 1n 0 2n 5 10n 5 11n 0 12n 0]

You could also enter the vector values and SI scalar values (p, n, u, m, k, M, G, and so on) from a file, in which case the component description might look like this:

v4 in 0  vsource type=pwl file="test.in"

You can use the -I command line option, followed by a path, to have the Spectre simulator look for the inserted files in a specified directory if they cannot be found in the current directory.

If you use an input file, the values in the file must look like the following:

0     0
1e-9     0
2e-9     5
10e-9     5
11e-9     0
12e-9     0

The following is an example of SI scalar values in the input file:

0 0
1u 4m
2u 3m
3u 2m
4u 1m
5u -1m 
6u -2m

The input file may also contain design variables. For example, the input file can have time, value, or both time and value as variables. The expressions may also contain empty spaces. For example:

1u     0
4u     volt1
time1 + 5u     0 
time1+5u     volt2
There should be no ambiguity in the expression, otherwise, Spectre generates an error. For example, Spectre will generate an error if the following expression is specified in the PWL file:
time1 + 4u  +5

Also see vpwlf for a definition of vpwlf source.

Using Library Statements

Another way to insert new files is to use the library statements. There are two statements: one to refer to a library and one that defines the library. A library is a way to group statements into multiple sections and selectively include them in the netlist by using the name of the section.

As for the include statement, the default language of the library file is SPICE unless the extension of the file is .scs; then the default language is the Spectre Netlist Language.

Library Reference

This statement refers to a library section. This statement can be nested. To see more information on including files, see spectre -h include. The name of the section has to match the name of the section defined in the library. The following is the syntax for library reference:

include "file" section=Name

where file is the name of the library file to be included. The library reference statement looks like an include statement, except for the specification of the library section. When the file is being inserted, only the named section is actually included.

Library Definition

The library definition has to be in a separate file. The library has to have a name. Each section in the library has to be named because this name is used by the library reference statement to identify the section to include. The statements within each section can be any valid statement. This is important to remember when using libraries in conjunction with alter groups because the altergroup statement is restrictive in what can be specified.

The optional names are allowed at the end of the section and library. Spectre does not check if these names match the names of the section or library.

The following is the syntax for library definition:

library libraryName
 section sectionName
  statements
 endsection [sectionName]
    section anotherName
  statements
 endsection [anotherName]
endlibrary [libraryName]

One common use of library references is within altergroup statements. For example:

a1 altergroup {
    //change models to "FAST" process corner
    include "MOSLIB" section=FAST
}

Structural Verilog

The Spectre circuit simulator supports structural Verilog netlist files for verification of digital circuits. This approach is typically used for standard cell designs, where the Verilog netlist file is generated by synthesis tools, and SPICE subcircuits are available for all standard cells.

The most common approach is to use a top-level SPICE file that contains the analysis statement, probes, measures, and simulation control statements, and also calls to one or more Verilog netlist files. The Verilog netlist files contain calls of basic cells, which are available in the SPICE netlist file.

You can also include Verilog files by using the vlog_include statement, as shown below.

vlog_include “file.v” supply0=gnd supply1=vdd insensitive=no|yes

Spectre reads the structural Verilog file file.v. The keywords are supply0 and supply1. The supply0 keyword must be set to the ground node used in the Verilog subcircuit and supply1 must be set to the power supply node. If insensitive=yes is specified, the Verilog netlist file is parsed as case insensitive. If insensitive=no is specified, it is parsed as case sensitive. The default value is no.

If the name of a module called by SPICE contains uppercase letters (for example, top_MODULE), then set insensitive=yes to use the vlog_include statement.

Unsupported Structural Verilog Features

Spectre does not support the following structural Verilog features:

Multidisciplinary Modeling

Multidisciplinary modeling involves setting tolerances and using predefined quantities.

Setting Tolerances with the quantity Statement

Quantities are used to hold convergence-related information about particular types of signals, such as their units, absolute tolerances, and maximum allowed change per Newton iteration. With the quantity statement, you can create quantities and change the values of their parameters. You set these tolerances with the abstol and maxdelta parameters, respectively. You can set the huge parameter, which is an estimate of the probable maximum value of any signal for that quantity. You can also set the blowup parameter to define an upward bound for signals of that quantity. If a signal exceeds the blowup parameter value, the analysis stops with an error message.

Generally, a reasonable value for the absolute tolerance of a quantity is 106 times smaller than its greatest anticipated value. A reasonable definition for the huge value of a quantity is 10 to 103 times its greatest expected value. A reasonable definition of the blowup value for a quantity is 106 to 109 times its greatest expected value.

Predefined Quantities

The Spectre Netlist Language has seven predefined quantities that are relevant for circuit simulation, and you can set tolerance values for any of them. These seven predefined quantities are

For more information, see spectre -h quantity.

quantity Statement Example

The electrical potential quantity has a normal default setting of 1 μV for absolute tolerance (abstol) and 300 mV for maximum change per Newton iteration (maxdelta). You can change abstol to 5 μV, reset maxdelta to 600 mV, define the estimate of the maximum voltage to be 1000 V, and set the maximum permitted voltage to be 109 with the following statement:

VoltQuant quantity name="V" abstol=5uV maxdelta=600mV      
 huge=1000V blowup=1e9

VoltQuant is a unique name you give to the quantity statement.

The keyword quantity is the primitive name for the statement.

The name parameter identifies the quantity you are changing. (V is the name for electrical potential.)

abstol, maxdelta, huge, and blowup are the parameters you are resetting.

The quantity statement has other uses besides setting tolerances. You can use the quantity statement to create new quantities or to redefine properties of an existing quantity, and you can use the node statement to set the quantities for a particular node. For more information about the quantity statement, see the Spectre online help (spectre -h quantity). For more information on the node statement, see spectre -h node. The following is an example of a node statement:
setToMagnetic t1 t2 node value="Wb" flow="MMF" strength=insist

Inherited Connections

Inherited connections is an extension to the connectivity model that allows you to create global signals and override their names for selected branches of the design hierarchy. The flexibility of inherited connections allows you to use

You can use an inherited connection so that you can override the default connection made by a signal or terminal. This method can save you valuable time. You do not have to re-create an entire subbranch of your design just to change one global signal.

For more detailed information on how to use inherited connections and net expressions with various Cadence® tools in the design flow, see the Inherited Connections Flow Guide.


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