Product Documentation
Virtuoso Custom Digital Placer User Guide
Product Version IC23.1, March 2023

1

Introduction

The Virtuoso® Custom Digital Placer automatically places transistors, devices, and cells in block and cell designs.

The Custom Digital Placer is a generic placer that can be used for placement in different types of designs such as designs that contain only standard cells, designs that contain only devices, or designs that contain both standard cells and devices. You can also use the placer for generating connectivity and constraint-driven placement.

However, before you can use the placer to automatically place devices, you must generate the layout connectivity and circuit components by using Layout XL editor. The placer uses the schematic design as the connectivity source for placing the components.

This chapter covers the following topics:

Key Features

The following sections contain more information about using the Custom Digital placer.

For information about the placer forms, see Custom Digital Placer Forms.

The Placement Commands

In Layout XL, the placement commands supported by the Virtuoso Custom Digital Placer are available under the Place menu. These commands are:

In addition to the placement commands listed above, the Place menu supports the following commands that can be used for placement:

Other Commands Used with the Placer

Placement Types

The Custom Digital Placer supports the following placement types:

Row-based placement

Row-based placement is a structured placement type that lets you place specific component types within rows. This placement type is most suited for placing standard cells and devices that have at least one “standard” dimension. For this reason, row-based placement is considered most suitable for designs that contain only standard cells.

In addition to providing a structured placement, row-based placement lets you constrain the components within a row to specific orientations and alignments. Given the uniform and structured placement it helps to obtain, row-based placement is considered a more economical and optimal placement type.

You can choose from the following modes for defining rows:

Area-based placement

Area-based placement is less restrictive of the two placement types supported by the Custom Digital Placer.

This placement type places the components anywhere within the available placement boundary, unless the components are locked outside the boundary. Area-based placement does not require component types or constraints to be defined. However, if any individual constraints are placed on the components, they are honored.

If individual constraints on components or groups of components do not exist, the placer only targets to reduce the overall wire length and achieve a balanced placement. Therefore, in the absence of constraints, the components tend to spread out using all the area allowed for placement.

Placement Of Different Component Types

You can use the Custom Digital Placer to place designs that have only standard cells, only devices, or a combination of both, standard cells and devices.

Standard (or custom) cells are placed in horizontal or vertical rows. Depending on their number, the placer can place all the cells within a single row or across multiple rows.

For more information about placing components within rows, see Row-based placement.

Devices follow a row-based MOS, transistor-level placement.

Since MOS devices support diffusion-sharing to enable chaining, you can automatically or interactively chain devices at the time of layout generation to optimize placement. Such placement maximizes the diffusion sharing to minimize the diffusion gaps in the generated layout.

For designs with a mix of component types, such as PMOS, NMOS, STDCELL, STDSUBCONT, and FILLER, depending on the cell type, both row-based and MOS transistor-level placement is followed.

Placing NFIN and PFIN Components (Virtuoso Advanced Node for Layout Standard)

The Custom Digital Placer can be used for placing NFIN and PFIN component types.

Global Snap Pattern Grid Support

VCP has been enhanced to support snap patter pattern (SP) / width spacing snap pattern (WSP) grid definitions:

To support snapping of devices and standard cells to the required snap pattern grid, VCP has undergone the following key enhancements:

Here is an illustration representing how the seed point for row creation during placement planning is different from the point of row creation, which is snapped to the grid specified in the Placement Planning form.

The Placement Flow

The placement flow for row-based designs typically involves the following steps:

  1. Define component types using the Component Type mode of Configure Physical Hierarchy to assign the devices to rows and set the parameters for device chaining and folding.
    See Component Types in the Virtuoso Layout Suite XL User Guide.
  2. (Optional) Generate layout representations for critical components by using the Layout XL Connectivity - Generate - Selected From Source command.
    See Generating Selected components from Source in the Virtuoso Layout Suite XL User Guide.
    Make a preliminary placement of the critical components by using the object editing commands. Critical components should preferably be hand-placed and locked in their final positions to prevent them from being moved during automatic placement.
  3. Generate a layout and a preliminary placement for the remaining design components by using the Connectivity - Generate - All From Source command or the Connectivity - Update - Components and Nets command.
    See Generating All Components from Source and Updating Components And Nets in the Virtuoso Layout Suite XL User Guide.
  4. (Optional) Place and constrain pins by using the Place – Pin Placement command.
    See Pin Planning.
  5. Create rows for placing the components, specify the component types to be placed in them, align the components to the respective rows, and specify the component orientation by using the Placement Planning command.
  6. (Optional) Set the appropriate placement constraints.
    See Pin Placement Constraints.
  7. (Optional) Set the Net Priority routing constraint for assigning higher priority to critical nets.
    See Net Priority in the Virtuoso Custom Constraints User Guide.
  8. Run the automatic placer by using the Place – Custom Digital – Placer command to automatically position the unplaced design components on the layout canvas.
    See Running the Placer.
  9. Examine the placement. If required, update the constraints you set and run the placer again.
For a demonstration of the basic custom digital placer flow, see the Virtuoso Customer Digital Placer flow video.

Setting Up Layout XL for Placement

This section describes some Layout XL environment variables you might want to set and some design-related decisions you should make before you begin working with the placer.

Setting the Netlisting Mode

To enable the placer to correctly handle permutable pins, ensure that the CDF parameters are evaluated correctly by setting the CDS_Netlisting_Mode shell environment variable to Analog or Compatibility.

Do not set the netlisting mode to Compatibility if you intend to chain or fold your devices.

To set the CDS_Netlisting_Mode environment variable for the current session,

To check the mode in which the environment variable is currently set:

If you do not have permutable pins in your design, and make no other use of the CDF data, you can get faster netlisting performance by setting CDS_Netlisting_Mode to Digital.

For more information about the CDS_Netlisting_Mode, see Customizing the Simulation Environment in the Open Simulation System Reference.

Several placement environment variables have equivalent variables to control the Virtuoso custom routers. Placer variables always override their router equivalents during placement.

Defining the Placement Region

The prBoundary object representing the place and route boundary defines the available placement region.The prBoundary can be a single rectangle or a polygon.

Abutting Standard Cells

By default, all standard cells—cells defined with component type STDCELL—are designed to support abutment. This implies that all standard cells abut together without creating design violations. Therefore, when placing abutted standard cells, the placer only checks the design rules between the boundaries of the adjacent standard cells. Rules between the internal objects in a standard cell are not validated.

In other words, the placer considers the boundary of each standard cell as its abutment edge. This ensures that the placement is optimal.

Although the placer does not check the design rules between the objects within a standard cell, it does run a full design rule check between standard cells—devices of component class STDCELL—and devices belonging to other component classes.

The placer determines the cell boundary for each standard cell by using the following precedence:

  1. The list of layer-purpose pairs defined in the vcpCellBoundaryLPPs environment variable.
  2. The (prboundary drawing) layer-purpose pair.
  3. The (prboundary boundary) layer-purpose pair.
  4. The (instance drawing) layer-purpose pair.

If none of the above layer-purpose pairs exists in the cell, a boundary is derived equal in size to the sum of the objects within the cell.

To ensure that the objects within adjacent standard cells can be shared or overlapped during placement without generating any abutment violations, the cell boundary must be defined by using the vcpCellBoundaryLPPs environment variable.

Setting MOS Chaining and Folding Parameters

To place the MOS devices optimally, you must set the following .cdsenv environment variables to chain and fold them before placement.

Using Automatic Abutment During Placement

If switched on in Layout XL, automatic abutment is performed during layout generation for assisted MOS devices. To use automatic abutment:

Setting Placement Constraints

To constrain the placement of devices or pins in your design, you can directly set geometric or pin placement constraints using the Constraint Manager or using an associated SKILL Function.

Geometric Constraints

You can create the following constraints in the Constraint Manager assistant for placement of objects:

Alignment Constraints

The placer supports alignment references on any layer or on the instance bounding box. The first object selected is considered as the alignment reference object and the remaining objects selected are aligned to that reference.

The Custom Digital Placer supports the following Alignment Constraint options:

For more information about the Alignment constraint, see Alignment under Default Constraint Types in the Virtuoso Unified Custom Constraints User Guide.

Cluster Constraints

The placer honors non-hierarchical cluster constraints that are set to specify the logical association among the instances within a cellview. Each cluster is associated with one or more rectilinear cluster boundaries within which the instances associated with that cluster are placed.

Depending on the members it accepts, a cluster can be:

Note:

To define a cluster constraint on a selected set of components, run the Cluster command from the Placement constraints available in the Constraint Manager. To define a boundary for the cluster, select the Create – P&R Objects – Cluster Boundary command. To set the type of a cluster, choose a value for the Type field in the right panel on the Create and Edit Clusters form. To open the form, select the Create – P&R Objects – Clusters command.

For more information about the Alignment constraint, see Cluster under Default Constraint Types in the Virtuoso Unified Custom Constraints User Guide.

Related Topic

Create Cluster Boundary

Distance Constraints

The placer honors the distance constraint between two or more devices. However, when setting constraints for multiple devices, you must define the acceptable distance parameters between each pair of devices for the placer to interpret them.

When a Distance constraint has more than two members, the constraint applies between the first and any of the following objects. That is, each of the second and following objects must be within the specified range from the first object.

You can constrain the devices in one direction—X or Y—but not in both directions simultaneously. However, after the devices have been constrained, the placer aligns them in the orthogonal direction.

The Custom Digital Placer honors the following Distance Constraint attributes:

For more information about the Distance constraint, see Distance under Default Constraint Types in the Virtuoso Unified Custom Constraints User Guide.

Fixed Constraints

The placer honors the fixed constraint that is set to limit the position of one or more components with an allowable set of orientations to a particular x and y location.

The Custom Digital Placer supports the following Fixed Constraint options:

For more information about the Fixed constraint, see Fixed under Default Constraint Types in the Virtuoso Unified Custom Constraints User Guide.

Symmetry Constraints

The placer interprets the order between the device pairs involved in a symmetry constraint. For example, if Q1 and Q2 are constrained along their horizontal line, then the constraint implies that Q1 lies below the horizontal line and Q2 lies above it. If the devices are constrained along a vertical line, based on the symmetry constraint, Q1 should lie to the left of the vertical line and Q2 to the right.

The placer supports the following types of symmetries:

The symmetry axis can be floating as well as fixed.

The Virtuoso Custom Digital Placer supports the following Symmetry Constraint options:

For more information about the Symmetry constraint, see Symmetry under Default Constraint Types in the Virtuoso Unified Custom Constraints User Guide.

VCP honors the database cell symmetry set as an OA cell property on the cell master to derive allowed orientations as per the following table:

Database Cell Symmetry

Allowed Orientation of Devices during Placement

dbcXSymmetry "X"

R0, MX

dbcYSymmetry "Y"

R0, MY

dbcXYSymmetry "XY"

R0, R180, MY, MX

Pin Placement Constraints

There are three ways in which you can set placement constraints on pins. These are:

Setting Pin Placement Constraints using the Constraint Manager Assistant

You can set distance, alignment, grouping, symmetry, and fixed pin constraints by using the Constraint Manager assistant. For information about these constraints and how they are supported by Layout XL and the placer, see Geometric Constraints.

Depending on the requirement of your design, you can set multiple constraints using the Constraint Manager. For example, if you want to constrain pins to an edge of a bounding box with a specified pitch, you must create an alignment constraint and a distance constraint.

Pins that you constrain through the Constraint Manager are moved to their assigned positions in the layout view only when the placer is run.
Cadence recommends that you use any one of the methods for setting all your pin constraints to avoid creating conflicting or redundant constraints.

For more information about setting constraints through the Constraint Manager assistant, see the Virtuoso Unified Custom Constraints User Guide.

Setting Pin Placement Constraints using the Pin Placement Form

The advantage of using the Pin Planner form is that it lets you set and apply multiple constraints on multiple pins simultaneously. After you click Apply, the specified pins are automatically moved to the specified positions.

You can set the following constraints using the Pin Placement form.

The Pin Placement form lets you assign pins to a fixed location or to a particular edge and order them along each edge according to your requirement. You can also specify fixed spacing for a group of pins that you have ordered and aligned to a particular edge.

For example, you have a polygon with six edges and you want to place three pins (pin1, pin2, and pin3) on edge number 5. When you specify this in the pin placer form, it creates an alignment constraint as follows.

Members

PR boundary (reference)
pin1
pin2
pin3

Constraint parameters

side=edgeNumber

Members parameters

side=edgeNumber
edge=5

For more information about setting constraints through the Pin Placement form, see the Pin Planner form.

Setting Pin Placement Constraints using SKILL Functions

You can set placement constraints on pins by using SKILL Functions.

Defining Component Types and Placement Parameters

The information about the “type” of each design component is required to specify the chaining and folding parameters for the components, and to define how the various component types are assigned to rows.

Currently, there is no need to define the component types for placing the components by area. In other words, if the component types are not specified, the components are placed by area.

You can define component types by using the Edit – Component Types command.

Depending on the requirement of your design, you can define the component types at the library level or at the individual cell level.

Irrespective of their type, the components are placed within the place and route boundary unless:

Note:

Defining a Standard Cell Substrate Contact

Standard cell substrate contacts, also called tap cells, are physical-only filler cells that are inserted between devices to limit resistance and to establish connection between the VDD and GND rails, thereby preventing DRC errors and latchup effects.

Standard cell substrate contacts are neither contacts nor vias; they are standard cells assigned to component types with the component class STDSUBCONT.

Standard cell substrate contact insertion is done on a per-row basis. Therefore, the location of standard cell substrate contacts in each row is independent of the placement of standard cell substrate contacts in other rows.

In the above diagram, S1 represents the offset of the first and last substrates from the respective row edges, and S2 represents the distance between two consecutive substrates.

You can specify the maximum and minimum spacing values between two consecutive substrates by using one of the following methods:

The values for S1 range from 0 to half of the value of S2. For example, if you specify 1 and 4 as the minimum and maximum values for S2, the value of S1 can range from 0 to 2. The Auto Placer respects these values during placement.

While running the Auto Placer, the positions of the standard cell substrate contacts might be altered to optimize the overall wire length. Such alterations might result in substrate spacing violations. Use the Annotation Browser to view and manage any violation markers that are generated for the design.

Use the Swap Tap Cells feature to detect tap cells with maximum spacing violations. You can also replace them with tap cells that have valid maximum spacing values.

For more information about this feature, see Swapping Tap Cells.

Defining the Substrate Contact Spacing Properties

To add standard cell substrate contacts, you need to define the following properties:

To define these properties:

  1. Copy an existing filler cell, which is to be used as the basis for the standard cell substrate contact.
  2. Add substrate and well contacts to the cell. You can use oaVia, via instance, or polygons to do this.
  3. Add the lxVcpSubContMaxSpacing and lxVcpSubContMinSpacing properties to the cellview.
    For example, to set lxVcpSubContMaxSpacing, do the following.
    1. From the layout window, choose Edit – Basic – Properties – Cellview.
      The Edit Cellview Properties form appears.
    2. Click the Add button to display the Add Property form.
    3. Specify the property parameters, as indicated in the figure below, and click OK to set the property.
    4. Repeat steps a through c to add the lxVcpSubContMinSpacing property.
    5. Click OK to set the properties and close the Edit Cellview Properties form.
  4. Choose Edit – Component Types to display the Configure Physical Hierarchy window in the Component Types mode.
  5. Assign a component type to the new cell that you created, which has its Component Class set to STDSUBCONT. (Create a new component type, if required.)
  6. (Optional) Specify the view name to be used for placing the cells of class STDSUBCONT.
    If the view name is not defined, the placer traverses through the Physical stop view list in the Global Bindings section of the Configure Physical Hierarchy form to determine the view type to be used.
  7. Run the automatic placer after selecting the Insert Standard Cell Substrate Contacts option selected.
    The placer fills any gaps between the placed cells with the specified standard cell substrate contacts.
You can use the Insert Std Cell Substrate Contacts options in the Auto Placer form to globally override the substrate spacing you had set using the Add Property form. Alternatively, use the subContMaxSpacing or subContMinSpacing environment variables, as required.

Placing Standard Cell Substrate Contacts in Alternate Rows

By default, substrate contacts (tap cells) get placed in consecutive rows. But, if required, you can force them to be placed in alternate rows. However, for this to be supported by the placer, the rows in which the substrate contacts are to be placed must be created in flipped and abutted manner. This means the rail pattern should be PGGP or GPPG and the row-to-row spacing must be zero.

To place substrate contacts in alternate rows:

With substrate contact placement in alternate rows selected, the placer places the substrate contacts in alternate rows, such as the 1st, 3rd, 5th, and so on. But, if the total number of rows created is even, the substrate contacts will also be placed in the top row. For example, if the total number of rows generated is 6, the substrate contacts are placed in the 1st, 3rd, 5th, and the 6th rows.

MOS Transistor Chaining and Folding Parameters

After the devices are assigned a component type, the MOS transistors that need to be chained and folded must have certain parameter values set before you generate a layout.

Troubleshooting Placement

This section discusses common placement problems and some possible solutions.

Room Violations

Room violations are spacing violations that occur when the components placed within a partition are overlapped by another partition or when two partitions overlap.

By default, the VCP engine excludes components that do not belong to the partition to be placed. However, room violations might still be observed if the partition itself is overlapped by another partition.

The markers generated due to room violations in a design are displayed in the Misc tab of the Annotation Browser.

To fix room violations, manually move around the overlapping shapes.


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