Product Documentation
Virtuoso RF Solution Guide
Product Version IC23.1, June 2023

9


Verify the Package

The connectivity, LVS, and DRD checks are being done on the layout. When the package layout is modified, you need to verify that the connectivity of the physical implementation is valid. Markers are created to indicate opens and shorts present in the layout. Batch and interactive DRD checks can work with both curvilinear and regular shapes in a package layout. The DRD checker can be used to verify for the constraint violations in a package layout. Both connectivity extractor and DRD checker take into account void shapes.

Verifying that a design is correct is often the most difficult and yet also the most important aspect of designing a package layout. Additionally, routing paths should be adjusted iteratively until the package is optimized for all constraints. The number of layers depends on power levels and complexity.

Related Topic

Checking Layout

Cross-Fabric Checks Run

Checking Layout Against Schematic

Performing Cross-Fabric Checks

Extracting the Connectivity

Performing DRD Checks

Supported DRD Constraints and Checks


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