Enable Electrical Data Capture for EAD Flow

If the EAD mode is to be enabled or disabled for the selected design under test.

Design Selection

Design Under Test

The library name and cell name of the design for which electromigration analysis is required to be done.

Save Options

Signal Selection

All Signals

The current data is to be saved for all the signals in the specified DUT.

Hierarchy Stop Level

The design hierarchy level up to which the current data for all the signals is to be saved.

Selected Signals

The current data is to be saved for the selected signals only. You can select the signals using the Parasitic and Electrical Setup assistant.

Electromigration Checking

Type

DC Current (Idc)

The direct current data is to be saved.

Average Current (Iavg)

The average current data is to be saved.

Scale

A multiplier by which the direct and average current data is scaled.

Waveforms for RMS and Peak Checks (Isignal)

Directs to save the current waveforms with the simulation data to disk so that it can be processed later while performing RMS and Peak electromigration checks.

Voltage Dependent Rules

Type

Min and Max Voltage (Vmin/Vmax)

That minimum and maximum voltages are to be captured during the simulation run for use in the voltage dependent rules flow.

Scale

A multiplier by which the voltage data is scaled before it is transferred to the layout view. The default is 1.00, which means that voltage data is not scaled.

Create voltage constraints

Whether to create post-simulation voltage constraints.

Environment variable: createVoltageConstraints

Waveform Processing Options

Process Waveforms Inside Simulator

Directs to process the current waveforms during simulation and save only the calculated current data to the disk.

Process Waveforms Post Simulation

Directs to process the current waveforms after simulation

Clip Waveforms

The saved waveform needs to be clipped for the given time interval.

From

The start time of the time interval for which the waveform of the current data is to be saved.

You can also use the VAR expression in this field. For example, VAR("variable_name").

For more information, refer Virtuoso ADE Assembler User Guide.

To

The end time of the time interval for which the waveform of the current data is to be saved.

You can also use the VAR expression in this field. For example, VAR("variable_name").

For more information, refer Virtuoso ADE Assembler User Guide.

Process

Process Settings

The process settings file to be used in the current session.

The Display process settings menu button lets you add, change, or remove process settings files.

Environment variable: processSettings

See Editing Process Settings for more information.

Temperature

The extraction temperature in degrees Celsius.

Environment variable: temperature

Network

Excluded Nets

The nets to be excluded from parasitic extraction. Do one of the following:

• Type in a list of net names (complete, incomplete, power, etc) you do not want to extract. Separate the net names with a space or a comma. You can use wildcards to specify multiple net names.
• Click Select to select nets directly in the layout or schematic canvas.

Environment variable: excludedNets

Except Nets

The nets that are exceptions to the list of nets specified in the Excluded Nets field. The nets specified in this field are extracted or displayed.

Environment variable: excludedNetsExceptions

Exclude Incomplete Nets

That nets with incomplete routing or connectivity are to be excluded from extraction. Use this to skip extraction for all incomplete nets.

Environment variable: includeSkippedNets

Primitives & Excluded Cells

Lib
Cell
View

The cellviews to be excluded from parasitic extraction. Parasitics are extracted up to and including the terminals of the excluded cells, but no extraction is performed inside the specified devices.

Click Add to add a row to the table, and type the required library, cell, and view names into the fields provided (or choose the names from the drop-down lists).

If you do not specify a cell or view name, then all cells or views are excluded. For example, the table below specifies the following exclusions:

• Cellview Two_Stage_Opamp/OpAmp/layout_new
• All views of cell inv_2x_hv in the ether library
• All the cellviews in the em_test library
  
  

Environment variable: extractionPrimitives

Setups

Location

See EAD Setup Options

Name

Engine Controls

Extraction Mode

The types of parasitic networks produced by the EAD extractor.

Choose the mode (RC, C, or R) from the first pull-down and, where appropriate, the capacitance coupling type (coupled, decoupled, or lumped coupled) from the second pull-down.

The default is RC coupled.

Environment variable: type

Hierarchy Levels

Specifies the layout hierarchy depth for RC extraction. For example, if you type in 0, only top-level routing is extracted; if you type in 99 all hierarchy levels are extracted (nets that are wholly contained in lower levels are also extracted and reported).

Environment variable: hierarchyLevels

Net Levels

Specifies the layout hierarchy depth for the lookup of nets for RC extraction. Value for this field should be less than or equal to the value of Hierarchy Levels.

Environment variable: netHierarchyLevels

Inst Term Hierarchy Levels

Specifies the layout hierarchy depth from which the instance terminals are to be extracted during RC extraction. By default, the instance terminals at the bottom of the hierarchy are extracted. Value for this field should be less than or equal to the value of Hierarchy Levels.

Environment variable: instTermHierarchyLevels

Erosion Effects

Specifies whether erosion effects are applied only to resistances (R), only to capacitances (C), to resistances and capacitances (RC), or to neither resistances nor capacitances (none).

Environment variable: enableErosionEffects

Stop at Device Boundary

Controls whether EAD extracts parasitics for shapes that are part of device terminals; for example, metal shapes in the source/drain regions of a transistor. This applies for instances at the level specified by the Hierarchy Levels setting.

By default, EAD extracts parasitics for such shapes. But when this option is switched on, extraction stops at the device boundary, which means that terminals on Pcells and instances are treated as background shapes and are not extracted.

Environment variable: promotePorts

Threads

The number of threads to use in multi-threaded R and C engines, both Fast and High Precision. It is applied only when multiple nets are being processed.

Environment variable: threads

Stop on LVS Mismatch

Select this check box if you want to skip extraction when there is an LVS mismatch.

Use Quantus timing mode

Select this check box if you want to run Quantus extraction in timing mode. In this mode, simulation is faster but there are less details available for debugging.

Thresholds

Max Resistor Length

The maximum length of resistor that will be extracted.

Specify a value >= 0.5 in the text box.

Resistors that are longer than the specified length are fractured into multiple resistors.

The unit for this value is microns.

Environment variable: maxResistorLength

Minimum Coupling Cap

A minimum coupling capacitance value in femtoFarad (fF). Capacitance values below the specified threshold are ignored during extraction. This lets you filter out small capacitance values that are likely to be inconsequential in any analysis.

Environment variable: couplingCThreshold

Resistance Scaling Factor

Scaling factor to be applied on the extracted resistances.

Environment variable: resScaleFactor

Gnd Cap Scaling Factor

Scaling factor to be applied on the extracted ground capacitances.

Environment variable: gndCapScaleFactor

Coupling Cap Scaling Factor

Scaling factor to be applied to the extracted coupling capacitances.

Environment variable: couplingCapScaleFactor

High Precision C Solver

Use for All Nets

That the high precision C solver is to be enabled for all nets. Use the Threads option to specify the number of processing threads to be used.

Environment variable: tileExtractor

Engine

The engine to used for extracting parasitics.

See the iQuantus FS C Extraction (Advanced Nodes Layout EAD Only) section for more information.

Default Convergence Target

The convergence goal (standard deviation) of the high precision C solver. It means that HPC will stop the random walk calculation process when it determines that standard deviation error has reached this convergence goal. In other words, if calculation continues with more walks, there is 99.7% probability that the result will fall into three sigma bounds comparing with the obtained values.

Environment variable: convergenceCThreshold

Metal Fill Modeling Method

Controls how the EAD extraction treats fill shapes in the layout.

• floating – Treat fill shapes as floating (unassigned to any net)
• ground – Treat fill shapes as if they are connected to ground
• none – Ignore fill shapes altogether

Environment variable: fillType

Via Effects

Enables or disables via capacitance effects in the high precision C extraction.

Environment variable: modelViaCapacitanceEffect

Threads Per Net

The number of processing threads to be used by the high precision C solver for each net. This is another level of threading from the net-based processing.

Setting this value to auto means that you want to use all the threads on the machine.

For example, on a 16-core machine, 16 threads will be used.

If you set this variable to a non-zero value, it will use the specified number of threads. The maximum number of threads that can be used will always be equal to the number of cores on the machine, regardless of the user-specified setting.

For example, on a 16-core machine, if you set this variable to 8, only 8 threads will be used. But on the same machine, if you set this variable to 32, a maximum of 16 threads will be used regardless of the user-specified setting.

Environment variable: tileExtractorThreadCount

High Precision R Solver

Use for All Nets

That the high precision R solver is to be used for all nets. Use the Default Mesh Density option to specify the mesh density to be used by the extractor.

Default Mesh Density

The mesh density to be used by the high precision R solver. The default value is 1.0.

Environment variable: resistanceMeshDensity

Threads Per Net

The number of processing threads to be used by the high precision R solver for each net. This is another level of threading from the net-based processing.

Setting this value to auto means that you want to use as many threads as supported by the CPU.

For example, on a 16-core machine, 16 threads will be used.

If you set this variable to a non-zero value, it will use the specified number of threads. The maximum number of threads that can be used will always be equal to the number of cores on the machine, regardless of the user-specified setting.

For example, on a 16-core machine, if you set this variable to 8, only 8 threads will be used. But on the same machine, if you set this variable to 32, a maximum of 16 threads will be used regardless of the user-specified setting.

Location

See EAD Setup Options

Name

Temperature

EM Temperature

The EM temperature in degrees Celsius. This should be based on EM rules specified by the foundry.

Environment variable: temperature

Use Dataset Value

That the temperature specified in the simulation dataset is to be used when computing EM effects.

If the temperature value specified in the dataset is not valid, the default value specified in the EM Temperature field is used. ADE Assembler can correctly read a valid temperature if it is specified as a numerical value or as a variable using the VAR syntax.

Environment variable: useDatasetTemperature

Delta T

The increase (in degrees Celsius) in junction temperature due to joule heating.

Environment variable: deltaT

Current

Default

The default terminal current to use when computing EM effects when there is no electrical data available from ADE Assembler.

Environment variable: defaultCurrent

Minimum

The minimum threshold limit for Idc and Iavg currents of the terminals and instance terminals of a net for using that net in EM calculation. If the current of all terminals and instance terminals of a net is below the threshold, EM calculation is skipped for that net.

This minimum value is considered for the EM calculation of DC Op and Static-Avg current. It is not considered for the calculation of Dynamic-Rms and Dynamic-Peak current.

Environment variable: minCurrent

Scaling Factor

The scaling factor to be used to scale currents when computing EM effects. All terminal currents are scaled by this value.

Environment variable: scalingFactor and scale

Resistor

Resistor Limit

The maximum resistor limit against which the resistor count is compared while running EM checks.

Ignore Resistor Limit

Controls the comparison of the resistor count against the specified resistor limit while running EM checks.

Environment variable: ignoreResistorLimit

Aging Effects

Lifetime

The lifetime to be used for risk-based EM analysis. In risk-based EM analysis, MTTF (Mean Time To Failure) is first calculated using Black's equation. The calculated value is then used together with the specified lifetime to determine the probability of EM failure.

Specify the value in the text field and choose either years or hours from the pull-down list.

Environment variable: lifetime and lifetimeUnits

Note: This field is disabled when the EM Data Source is set to EM data files in the EAD Process Settings – Corners form.

Dynamic Analysis

Enables dynamic EM analysis. Use the From and To fields to limit dynamic analysis to a specific time period in the simulation results.

Environment variable: dynamicAnalysis

When enabled, you can right-click in the Dynamic Peak and Dynamic Rms columns in EM tab and choose Plot Terminal Currents to view the currents associated with the terminals of the selected net or Plot Resistor Currents to view the intermediate currents through the selected resistor. Plots are displayed in a separate Virtuoso Visualization and Analysis XL window.

From

Start time for dynamic analysis (default is 0).

To

End time for dynamic analysis (default is the last time point in the simulation results).

Use Dataset Value

Specifies if the information about the time interval for which the clipped waveform is to be used for EM analysis is to be taken from the dataset

Environment variable: useDatasetClipInfo

Enable Self Heating Effects

Enables the use of self heating effects in EAD.

Environment variable: enableSelfHeatingEffects

When the self heating effects are used, Virtuoso Layout EAD calculates the delta-T values for devices by using the delta-T values saved in simulation result datasets and the RMS current. This calculation uses certain constant values that you can provide in a setup file specified by the sheSetupFile environment variable.

To know about how to view the delta T results in EAD Browser, refer to Viewing EM Information in the EAD Browser.

Setups

Location

See EAD Setup Options

Name

Job Setup

Default Job Policy

The job policy to be used for all the nets. The default job policy is localhost.

Click Edit job policies ( ) to open the EAD Job Policy Editor form, where you can set up, edit, and delete a job policy.

See the Working with Job Policies section for more information.

Wait For All Jobs To Complete

Waits for all the jobs to finish before showing the extraction or EM results.

EM Violation Highlighting

% of Limit

The EM violation ranges used to highlight violations in the EAD Browser.

Environment variable: violationLevels

Color

The colors used to highlight different violation levels in the EAD Browser. These are fully customizable, allowing you to color code the table display based on how much current capacity is being used by each wire.

EAD Browser Customization

Highlight Selected Nets

That nets selected in the EAD Browser are automatically highlighted in the layout window as well.

Environment variable: highlightSelectedNets

Select Nets in Layout

That nets selected in the EAD Browser are automatically selected in the layout window as well.

Environment variable: selectNetsInLayout

Detailed Parasitic Tables

Displays detailed resistance and capacitance tables in the EAD Browser.

When enabled,

• If you select a capacitance value, the browser shows an extra table of individual coupling capacitance values
• If you select a resistance value, the browser shows an additional table of individual resistance values along each path

Environment variable: detailedParasiticTables

Setups

Location

See EAD Setup Options

Name

Location

The directories where the setup files and process settings are stored.

The list of locations includes all the .cadence directories found in the paths specified in the Cadence setup.loc file and in any additional directories specified by the auxSearchPaths environment variable; for example,

Process settings:
<directory>/.cadence/[<user>]/dfII/EAD/[<version>]/process/<process_settings_files>

Setups:
<directory>/.cadence/[<user>]/dfII/EAD/[<version>]/setup/<setup_files>

Also listed are any technology-dependent setup files stored in a subdirectory with the same name as the technology library for the design.

For more information, see “Understanding the .cadence Hierarchy” in the Virtuoso Design Environment User Guide.

Name

The name of the setup file.

Use the buttons to perform the action required:

• Save To saves the current settings to the specified setup file
• Load From loads the settings from the specified setup file for use in the current EAD session
• Delete deletes the specified setup file

Quantus CCL File Path

The file path to the Quantus CCL file that is generated after a Quantus run.

PVS GUI Log File Path

The file path to the PVS GUI log file that is generated after a PVS run.

EM Data Source

The source for EM rules. Choose any of the following:

• Virtuoso techfile: to read the EM data from the Virtuoso technology file
• ICT files: to read the EM data directly from the ICT file or QRC technology file specified in the EAD Tech File column
  
  If you are performing pre-adoption testing of the EAD flow, you can directly use the EM data from a QRC technology file, but it cannot be used for fast C extraction. Therefore, in production use, it is recommended to generate an EAD technology file from the QRC technology file.
• ICT-EM: to read the EM rules from partial ICT files that contain only the content required to define the EM rules for EM analysis. You can use this data source in the following scenarios:
  • When you have an EAD technology file that contains process settings, but you need to load different sets of EM rules to test the design against different EM operating conditions.
  • When the ICT file does not contain the final set of EM rules that are provided separately in partial ICT files. In this case, instead of modifying the ICT file to include the EM rules, you can load them from the EM rules file.
  
  When choosing this option, specify the name of the ICT file in the EAD Tech File column and the partial ICT file in the EM Data File column of the table given on this tab.
  
  A partial ICT file uses the ICT syntax to define the EM parameters in the process section, and the EM models in the conductor and via layer sections.
  Also see: Using Custom Variables in ICT-EM Files
• EM data files (same as VAVO/VAEO) to add the EM Data File column where you can specify an EM data file to use
• iRCX-EM: to read the EM data directly from the iRCX-EM file without the need to update the existing EAD technology file or to first convert the iRCX-EM file to the ICT-EM file.

Name

The name of a corner.

EAD Tech File

The location of the EAD technology file to be used for the specified corner.

Type the path to the file into the field, or use the Browse button to locate it on the disk.

For more details on the EAD tech file, refer to Generating an EAD Technology File.

ICT-EM Data File

The location of the ICT-EM data file to be used.

When using an ICT-EM data file, ensure that the layer names in the EAD technology file and the given ICT-EM data file match. If the layer names in these files do not match, you must provide an EM Layer Map file along with the ICT-EM data file. The EM Layer Map file provides the missing layer mapping information.

EM Layer Map File

The location the EM Layer Map file that contains the layer mapping information.

Double click the cell in the column to specify the path either by typing or by clicking the ellipsis (...) button. You can also specify this file using the ictemLayerMapFile environment variable.

EM Data File

The location of the EM data file for the corner in question.

Type the path to the file into the field, or use the Browse button to locate it on disk.

Note: This field is visible only when EM Data Source is set to EM data files.

iRCX-EM Data File

The location of the iRCX-EM data file to be used for the specified corner.

Double click the cell in the column to specify the path either by typing or by clicking the ellipsis (...) button.

When using an iRCX-EM file, ensure that the layer names in the EAD technology file and the given iRCX-EM file match. If the layer names in these files do not match, you must provide an iRCX-RC file along with the iRCX-EM file. The iRCX-RC file provides the missing layer mapping information.

iRCX-RC Layer Map File

The location of the iRCX-RC file that contains the layer mapping information.

Double click the cell in the column to specify the path either by typing or by clicking the ellipsis (...) button.

ICT Layer

The name of the layer in the ICT file.

Virtuoso Layer

The name of the corresponding layer in the Virtuoso technology file. The specified layers can be original layers or Virtuoso layers derived from the techDerivedLayers section of the technology file. An ICT file can have multiple poly layers for different devices, but the Virtuoso technology file has only a single poly layer. You need to derive and map additional poly layers.

If there is no obvious mapping, this entry is left blank. Type in or choose the layer you need by double-clicking on the entry in the table. The drop-down list shows only those layers that are relevant to extraction.

Via Instance Mode

The clustering style to be used. Choose one of the following:

• cluster: Clustering parameters are applied inside each via instance. No clustering occurs across hierarchical boundaries.
• flatten: Flattens all via instances (across hierarchy) and then applies clustering parameters
• one_resistor: Extracts one resistor for each via instance. Clustering parameters not followed, there is no clustering across hierarchical instance or Pcell boundaries. Flat vias follow cluster parameters.

Environment variable: viaInstanceMode

Also see: viaShapesScanMode

Layer

The via layer name.

Max Spacing

The maximum spacing allowed between vias. If the space between vias for a given layer is below the specified value, they are clustered.

Max Spacing = 2 * minSpacing + minWidth - (1/DBUperUU)

If minSpacing value is not defined in the Virtuoso technology file for the via layer, no clustering is performed, which means that one resistor is extracted for each via shape.

DBUPerUU is database units per user unit specified in the technology file.

Max Cuts

Maximum number of vias that are clustered.

Default value: 100

Lib
Cell
View

The cellviews containing the shapes to be specified.

Type the required library, cell, and view names into the fields provided (or choose the names from the drop-down lists).

If you do not specify a cell or view name, then all cells or views are assumed. you can also use an asterisk as a wildcard as shown in the examples below.

Term

A terminal name. If you do not specify a terminal name, then all terminals are assumed.

Layer

A layer name.

You can either type in a layer name or choose a layer name from the drop-down list. The list shows only those layers that are relevant to extraction.

If you do not specify a layer name, then all layers are assumed.

Shape Type

How a shape is treated during extraction:

• regular refers to shapes that have a net assignment. EAD extracts coupling capacitance to these shapes
• background refers to shapes that do not have a net assignment. EAD extracts grounded capacitance to these shapes (exception: for “background” shapes on device or instance terminals, EAD extracts coupling capacitance)
• invisible: Shapes are ignored by the extraction engine

Environment variable: hierarchyShapeType

Job Policy Name

Displays the currently selected job policy.

Distribution Method

One of the following distribution methods:

• Command
• LBS
• Local
• Remote-Host

Command

The bsub command to submit a job for batched execution by a distributed load-sharing batch system

Queue

The name of queue to which the distributed job is submitted.

Hosts

The list of remote hosts to be used for evaluating the submitted jobs.

Max Jobs

Maximum number of simultaneous jobs

Job Policy

Displays the currently selected job policy for a net.

The <default> policy indicates that the policy that is selected as the Default Job Policy in the Job Setup section on the Environment tab of the EAD Options form is also selected for the net.

You can also select different policies for different nets.

Click the Edit job policies icon next to the Job Policy field to open the EAD Job Policy Editor form.

Library

Name of the library

Cell

Name of the cell

View

Name of the view

Device M Factor Parameter Names

Names of the parameters that define m factor for devices

Device Finger Parameter Names

Names of the parameters that define the number of fingers for devices

Netlist View Name

Specifies the name of the view to be used to create a netlist that includes parasitics or LDE parameters from the layout view.

Both LDE parameters and layout parasitics can be added to the same netlist view.

Layout Lib Name for Parasitics & LDE

Name of the library of the design that contains a layout cellview with layout parasitics.

Layout Cell Name for Parasitics & LDE

Name of the design cell that contains a layout view with layout parasitics.

Layout View Name for Parasitics & LDE

Name of the layout view that contains layout parasitics to be used in resimulation of a design. This can be a partial or a complete layout view.

When you specify a layout name in this field, select Include Parasitics From Layout option in the Parasitics section on the Layout tab or the Layout View option in the LDE section on the Layout tab. This is helpful in the EAD or LDE flow.

You can choose to include both the LDE parameters and the layout parasitics from the same layout view.

Parasitics

This section contains fields to be used while including parasitics from a layout view. This is required while simulating a design with layout dependent effects or in the Electrically Aware Design flow.

Include parasitics from

Specifies the source of parasitics. You can select any one of the following three sources:

• None - No parasitics are used. This is the default option.
• Schematic Estimates - Includes estimates from the Parasitics & Electrical assistant. These are the same estimates used in the Schematic Estimates mode. This option allows the use of LDE with estimated parasitics
• Layout - Includes parasitic estimates from the layout view specified in the Layout View Name for Parasitics & LDE field.

When you choose to include layout parasitics in simulation, you also need to change the parasitic mode to Layout (Parasitics/LDE).

Extraction Setup for Layout Parasitics

When you choose to include parasitics from the specified layout view, names of the all the extracted corners for that layout are listed in this field. Select name of the desired corner.

Extraction Corner

When you choose to include parasitics from the specified layout view, names of the all the extracted corners for that layout are listed in this field. Select name of the desired corner.

The extraction corner that is selected in the EAD Browser is displayed as the default corer in this drop-down list.

The default extraction corner is defined in the process settings file (.ini file) that is saved to the specified location, for example:

/.cadence/dfII/EAD/1/process/gpdk045.ini

Reference Net for Grounded C

Specifies name of the ground net to be used for grounded capacitance. You can either type a name in this field or click Select from Schematic to select a net from the design schematic.

Important Points

• A reference net for grounded C is not required if you are extracting only R estimates or if you are stitching only R estimates from RC extraction.
• You can specify name of a global net that does not exist in the design under test. The net will be created in the netlist view as an inherited connection so that you can use a netSet property on the cell instance to specify the net to identify it with. The netSet property name is the same as the net name.
• You can use the msps.layout referenceNet environment variable to set the initial default value of the reference net field.

Expand Devices with M-Factor

Specifies if it is required to expand the devices with multiple factors before generating a netlist.

When this option is selected, the m-factor parameter on the schematic device is then used to create multiple parallel devices in the netlist view. This allows the parasitics for the nets between each m-factor instance in the layout to be brought into the netlist view for simulation. If this check box is disabled, the device is represented as a single instance in the netlist view, and the parasitics between m-factor instances will not be included.

LDE

This section contains fields to be used while including layout dependent effects from a layout view. This is required while re-simulating a design in the Layout Dependent Effects flow.

When you choose to include LDE parameters in simulation, you also need to change the parasitic mode to Layout (Parasitics/LDE).

Include LDE From

Specifies the source of LDEs. You can choose any one of the following options:

• None - This is the default option, which specifies that no parameters from layout or MODGEN constraints are to be used.
• MODGEN Constraints - Includes LDEs extracted from the Modgen constraints defined for the given constraint cellview.
• Layout View - Includes estimates from the layout view specified in the Layout View Name for Parasitics & LDE field.

If you include parasitics from layout in the Parasitics section, you cannot choose to use LDEs defined in MODGEN constraints. This is because parasitics and LDE parameters must come from the same source.

Include LDE from Layout View

Includes estimates from the layout view into the netlist view.

Device M-Factor parameter Names

While generating a netlist with parasitics, if the tool finds any cell with parameter names listed in field, it expands the cell if the Expand Devices with M-Factor check box is selected. However, when using LDE parameters, cells will be expanded according to the multiple factors used in the layout or MODGEN constraint. In both cases, the m-factor value on the individual expanded devices in the netlist is reset to 1.

Device Finger Parameter Names

While generating a netlist with parasitics, if the tool finds any cell with the given finger parameter names, it expands the cell if the Expand Devices with M-Factor check box is selected. However, when using LDE parameters, cells will be expanded according to the multiple fingers used in the layout or MODGEN constraint.

Ignore Dummies Back-Annotated to Schematic

Specifies that if there are any dummy cells backannotated from layout to the schematic view, they need to be ignored while generating a netlist for simulation.

For more details on backannotated dummy instances, refer to Dummy Instances Backannotation.

DSPF File Name

Name of the DSPF file. The default file name is <cellName>.dspf.

The file is saved in the cellview directory.

Related environment variable: dspfFileName

Subnode Delimiter

The delimiter to be used while writing subnodes in the DSPF file.

Default value: #

Related environment variables: dspfSubNodeDelimiter

dspfWriteSubNodes

Coupling Capacitance Prefix

The default prefix to be used for the coupling capacitance values in the DSPF file.

Related environment variable: dspfCouplingCapPrefix

Ground Capacitance Prefix

The default prefix to be used for the ground capacitance values in the DSPF file

Related environment variable: dspfGroundCapPrefix

Unit

The unit for capacitance values to be written in the DSPF file.

Default value: f

Related environment variable: dspfCapUnits

Resistance Prefix

The default prefix to be used for the resistance values in the DSPF file.

Related environment variable: dspfResistorPrefix

Unit

The unit for resistance values to be written in the DSPF file.

Default value: ohm

Related environment variable: dspfResUnits

Write Instances

Specifies whether to write instances in the DSPF file.

Related environment variable: dspfWriteInstances

Stack Twigs

Adjusts the width of a twig that has an EM violation by performing stacked stranding. When this option is deselected, twigs with EM violations are ignored. By default this option is deselected

Twig stacking is only supported when the optimization mode is Expand to Fix EM violations or Shrink and Expand. It is not supported when the optimization mode is Shrink Oversized Trunks.

Fill Stacked Trunks with Vias

Applies to widening of trunks using Stacked Stranding. This command inserts the maximum possible additional vias after a trunk is widened using stacked stranding. By default this option is deselected.

Prefer DRC Violations to EM Violations

Allows DRC violations (shorts and spacing errors) when widening the trunks, twigs, and vias. By default this option is deselected. This means that no DRC violations are allowed.

Extraction Setup

Specifies the path to the file containing the setup options.

For example: "./cadence/dfII/EAD/1/setup/gpdk45.ini"

Environment Variables: useSetup

Extraction Corner

Specifies the extraction corner that is mapped to an ICT file or eadTechFile to be used for extraction and the source of the EM models to be used for EM Checking.

For example, nominal.

Environment Variables: useCorner

Pre-EM Check Layers

Specifies the comma-separated list of layers on which pre-EM check is performed.

For example, Via1, Via2, Via3

Environment Variables: preEMCheckLayers