Physical Hierarchy Generation Methods

Allows you to generate a physical hierarchy from the logical hierarchy in a schematic. It also creates soft layouts and soft abstracts in the layout canvas corresponding to the configuration view generated by CPH.

Reinitializing a Floorplan

Makes a collection of design objects based on their cellType and places them around the design boundary. You can use the command to reinitialize a layout and alter the state of different design objects simultaneously.

I/O Planning and Placement

Allows you to optimize the IO position, placing I/Os and macros.

Block Placement

Enables you to automatically place all hard and soft blocks in a design and minimize the wire length and chip area.

Soft Blocks

Allows you to update soft blocks, remove soft block overlaps, snap soft blocks to the routing grid or manufacturing grid, pull soft blocks to the core area, and to push the top-level implementation of power structures, including metal shapes and poly layers, into the block level.

Pin Group Guides

Allows you to create pin groups, assign them to full or partial edge(s), and apply process constraints, such as layer range and spacings, to the entire pin group through a dedicated pin group guide constraint.

Pin Tool

Enables you to perform all pin-related tasks, such as creating pins, resizing pins, planning and optimizing pins, editing pin attributes, and setting their location constraints.

Pin Optimization

Positions the pins of blocks in a manner that helps obtain the shortest possible net length at a particular level in the design.

Auto-Create Pins

Searches for net shapes in a design and creates boundary and buried pins automatically on these net shapes.