Product Documentation
Virtuoso Studio What's New
Product Version IC23.1, November 2023

20

What’s New in Virtuoso Floorplanner


This topic provides a high-level overview of the new features in the IC23.1 release.


IC23.1 ISR3


Moving Pin Labels to Stamp Label Layers Defined in the Technology File

During Assisted Move, you can now move labels to the stamp label layers that are defined in the technology file. The Match Label Layer section in the Pin Tool Options form now includes the Use Stamp Label Layers option, which you can select to honor the stamp label layer definition in the technology file while running Assisted Move. 

The related environment variable astPinMoveMatchLabelLayerChoice now accepts a new option, Use Stamp Label Layers.


Aligning Connected Pins in the Pin Tool

While running various pin-related operations in the Pin Tool, you might want to quickly align pins. Earlier, you had to use an object alignment solution outside the Pin Tool.

The Pin Tool is now enhanced to let you select the required pins in the Pins Browser and quickly align connected pins using the Align to Connected Pin command in the shortcut menu.


Usability Enhancements in the Pin Connectivity Settings Form

The Pin Connectivity settings form has been further enhanced for your convenience. 


Specifying the Offset of IO PADs in IO Rows

As part of IO planning, IO PADs are placed in IO rows. Earlier, the positions of IO PADs were determined by the PAD spacing you specified in the IO PAD Placement form. In addition to this, the form now includes an Offset section, which lets you define the position of the first IO PAD along each edge. Now, Offset determines the position of the first IO PAD and Spacing determines the positions of the remaining IO PADs in each direction.


IC23.1 ISR2


Matching Label Layer Purpose Pair in the Pin Tool

(Layout EXL Only) You can use the Match Label LPP shortcut menu option in the Label Browser of Pin Tool to match the label layer purpose pair to the associated pin labels.


Shorting and Unshorting Terminals

The terminals that belong to the same net are called shorted terminals. The Pin Connectivity Setting form lets you short terminals in three ways - using the drag and drop operation, using the Short Terminals and Unshort Terminals options from the shortcut menu, or by editing the net name. You can also use the form to unshort the shorted terminals. 


Pushing Fill and Routing Blockages

Use the pibCreateBlockageType environment variable to push routing objects as both fill and routing blockages simultaneously when you run the Push Into Blocks command.


Specifying Spacing Constraints for IO Pad Cells

In the IO PAD Placement form, the Custom option is renamed to the Custom Sites option, which denotes the number of sites instead of the absolute distance between consecutive IO PADs for pad placement.

You can use this option to provide different spacing for IO pad cells within the same row. Custom site values are mapped to the pitch value specified in the alignment constraint.


Usability Enhancements in the Pin Tool Browser

The Pin Tool Browser now supports the following enhancements:

  • You can use the Signal Type column to view the signal type of the net connected with a pin.
  • The Type column is renamed to the Direction column.
  • The PGG column is now hidden by default. 



IC23.1 ISR1


Inserting Multiple Filler Cells

Inserting multiple filler cells is now simpler because of the following enhancements to the Select Filler Cells section of the Insert Filler Cells form:

  • You can filter lib:cell:view names for the filler cell by using the Filter button.
  • The right arrow button lets you add the specified lib:cell:view as a filler and the left arrow button lets you delete the selected lib:cell:view from the filler table. You can now select multiple filler cells at a time.
  • The Browse, Add Filler, and Remove Filler buttons are no longer available.


Placing Corner Pads in the Inner I/O Rows

The Corner Pad Placement form now supports the Place Corner Pads On Inner Row(applicable for Two Rows Per Side) option to place the corner pads aligned to the inner rows in a two-row-per-side layout design.


Creating Boundary or Buried Pin on Whole Shapes

You can now create a boundary or buried pin on the largest whole shape that is present inside the PR boundary.


Copying Unattached Labels from Source to Target Cellview

(Layout EXL Only) The Load Physical View form now supports the Update Unattached Label option that lets you copy the unattached labels from the source to the target cellview.

Related SKILL function:  vfpLoadPhysicalView


Spacing I/O Rows During I/O Row Creation

You can now use the Row Spacing option in the Create IO Row form to create spacing between two IO rows in Two Rows mode. This ensures DRC correctness between the IO rows.


IC23.1 Base


Modifying the Site Definition Width During I/O Row Creation

You can now change the width of the site definitions to abut rows during IO row creation.

This allows you to have some overlapped rows to ensure that pad placements are abutted. In case of IO placement for two rows, if the cells are of exact height as the rows, then adjusting the siteDefs allows abutted placement.


Customizing Pin Layer in the Pin Planner

Use the vfpTopLevelRouteEnableCustomPinLayer environment variable to enable custom pin layer when aligning level-1 pins to top-level route in the Pin Planner.


Display Enhancements in the Analyze Connectivity Form

You can now view the change in net count and line width in Block mode when you switch between All, Common, and Exclusive options in Net count and length field of the Analyze Connectivity form.

When multiple blocks are selected in Block mode, the net count and length is displayed at the center of the larger block.


Adding Pins On Different Purposes in the Pin Tool

Use the Add Pin On Different Purposes form to add any existing pin on specific purposes from Pin Tool.


Usability Enhancements in the Analyze Connectivity Form

The Analyze Connectivity form now supports three new options:

  • Use Mode to select Block or Net mode to display connectivity information or net selection between the selected objects.

  • Use Critical nets only to show connectivity information only for nets you consider to be critical in the design.
  • Use Supply nets to filter the connectivity information or net selection based on the selected type of net - Power, Ground, or Global.


Promote Pins Form Reorganized for Better Usability

In the Promote Pins form, all the pin promotion fields have been reorganized into a separate progressive disclosure for improved usability.


Usability Enhancements in the Pin Checker Form

The Pin Checker form now supports two new options:

  • Use Pin to wire overlap to check for physical overlaps between pins and wires.
  • Use Check duplicate pins to check for duplicate pins in the layout. 


Customizing Pin Dimensions for Moving Pin to Top-Level Route

You can use the vfpTopLevelRouteEnableCustomPinSize environment variable to enable custom pin sizing while moving a pin to a top-level route using the Pin Planner.


Controlling the 'PIN_ON_ROUTE' Property

You can use the vfpTopLevelRouteCreatePinOnRouteProp environment variable to control the creation of the PIN_ON_ROUTE property. The PIN_ON_ROUTE property can be set when the pin placement edge is set to top-Level Route.


Creating a Pin for Back Side Metal Layer Shapes

You can now use the autoPinTopBackMetalLayer environment variable to consider back side metal layer as the top metal layer and create pins for the specified shapes.


Snapping Promoted Pins

(Layout EXL Only) You can now use the Promote Pins form to snap the pins and labels to match the direction of target LPP. This feature is applicable only for advanced node designs that contain WSP tracks.


Adding Pins and Geometries for Layers and Nets

(Layout EXL Only) The Load Physical View form now supports two new options:

  • Use Add Pins and Geometries for Specified Layers to selectively transfer pins, wires, and shapes on the specified metal and poly layers.
  • Use Add Pins and Geometries for Selected Nets to selectively transfer pins, wires, and shapes on the selected nets.


Usability Enhancements in the Pin Spacing Form

You can now use Pin Offset option in the Pin Spacing form to set the pin spacing offset value from the specified PR boundary edge.


Creating Pin and Via Stacks using the Pin Tool

(Layout EXL Only) You can now use the new Create Stacked Pin form to create a stack of pins and vias on the selected metal layers using the Pin Tool.


Specifying the Blockage Type for Routing Objects

The Push Into Blocks command now honors the pibCreateBlockageType environment variable when it pushes the routing objects into the block level as routing blockages. This environment variable sets the blockage type for these routing structures.


Mapping Layer Purpose Pairs in the Load Physical View Form

(Layout EXL Only) You can now map instances, pin layers, and layer purpose pairs for selected pins and shapes using one of the following methods:

  • Selecting Mapping File on the Load Physical View form.
  • Using the vfpLoadPhysicalView SKILL function. The function now supports the updateSelectedNets and mapperFile arguments.


Support for Layer Independent Pin Spacing

You can now specify the layers on which pin spacing settings must be applied by using one of the following methods:

  • Selecting Layer Options on the Pin Spacing form.
  • Enabling the pinLayerOption environment variable.


Displaying Soft Block Cell Types in Block Annotations

You can now display the cell types of soft blocks in block annotations using one of the following methods:

  • Selecting Cell Type on the Block Annotations Options form.
  • Enabling the blockAnnotationCellType environment variable.







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