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Flows in Virtuoso RF Solution
There are many flows and sub-flows in the Virtuoso RF Solution, which involve various products such as, Cadence EMX® Planar 3D Solver, Clarity 3D Solver, Cadence Quantus™ Extraction Solution, and Allegro Package Designer Plus SiP Layout Option. You are recommended to follow the basic use model described below to create package layouts in Virtuoso and simulate IC in context of the package:
- Import the technology information, libraries, and ICs before creating the schematic and layout. This task is performed by the librarian of the project, who enables the environment for creating the package schematic and layout.
- Create a package schematic by instantiating SMD instances, die or IC instances, and transmission lines, creating attachments and connecting them to the package connectors, and simulating the schematic.
- Create a package layout by generating a layout from source, creating bond wires, bump attachments, embedded dies, and die stacks, and creating voids using dynamic shapes. Edit-in-Concert by opening layouts from multiple fabrics simultaneously represented as various tabs in Virtuoso layout. Thereafter, perform interactive routing, EM analysis, and post-layout simulation. Additionally, create the extracted schematic using S-parameters from Clarity, EMX, and AXIEM.
- Perform the connectivity, LVS, DRD, and DRC checks on the layout after importing from Allegro.
- Export the package layout to the SiP layout by using the Allegro® translators. Place parts in SiP and route in the package layout and incrementally update the Virtuoso layout from SiP.
Related Topics
Virtuoso RFIC EMX Quantus Flow
Virtuoso RF Schematic-Driven Flow
Virtuoso RF Library Import Flow
Virtuoso Schematic Editor Driven SiP Layout Flow
Virtuoso Stacked Silicon Solution Flow
SiP to Virtuoso Layout Assisted Import and Export Flows
Multi-Technology Enablement Flow
SiP Layout Option to Virtuoso Schematic Editor Flow
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